move sys timer setup from main to timer.c

[z180-stamp.git] / avr / z80-if.c

diff --git a/avr/z80-if.c b/avr/z80-if.c
index 08d417b832bd5b69c3675afd553775205b1c745c..7a953f06e9017b384615b69b0f6cb5fd5dda7c2e 100644 (file)
--- a/avr/z80-if.c
+++ b/avr/z80-if.c
@@ -78,6 +78,7 @@
 #define BUSACK         6
 #define DDR_BUSACK     DDRD
 #define P_RST          PORTD
+#define PIN_RST                PIND
 #define DDR_RST                DDRD
 #define RST            5
 
@@ -106,6 +107,7 @@
 #define Z80_O_BUSREQ   SBIT(P_BUSREQ, 7)
 //#define Z80_O_NMI    SBIT(P_NMI, )
 #define Z80_O_RST      SBIT(P_RST, 5)
+#define Z80_I_RST      SBIT(PIN_RST, 5)
 #define Z80_I_BUSACK   SBIT(PIN_BUSACK, 6)
 //#define Z80_I_HALT   SBIT(P_HALT, )
 
@@ -134,12 +136,18 @@
 #define MASK(n)        ((1<<(n))-1)
 #define SMASK(w,s) (MASK(w) << (s))
 
+void z80_bus_request_or_exit(void)
+{
+       if (!(z80_bus_cmd(Request) & ZST_ACQUIRED))
+               cmd_error(CMD_RET_FAILURE, EBUSTO, NULL);
+}
 
 static zstate_t zstate;
 static volatile uint8_t timer;         /* used for bus timeout */
+static bool reset_polarity;
 
 /*---------------------------------------------------------*/
-/* 10Hz timer interrupt generated by OC4A                  */
+/* 10Hz timer interrupt generated by OC5A                  */
 /*---------------------------------------------------------*/
 
 ISR(TIMER5_COMPA_vect)
@@ -197,12 +205,27 @@ static void z80_dbus_set_out(void)
        DDR_DB = 0xff;
 }
 
+static void z80_reset_active(void)
+{
+       if (reset_polarity)
+               Z80_O_RST = 1;
+       else
+               Z80_O_RST = 0;
+}
+
+static void z80_reset_inactive(void)
+{
+       if (reset_polarity)
+               Z80_O_RST = 0;
+       else
+               Z80_O_RST = 1;
+}
 
 static void z80_reset_pulse(void)
 {
-       Z80_O_RST = 0;
+       z80_reset_active();
        _delay_us(10);
-       Z80_O_RST = 1;
+       z80_reset_inactive();
 }
 
 
@@ -210,9 +233,9 @@ void z80_setup_bus(void)
 {
        ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
 
-               /* /ZRESET: Output and low */
+               /* /ZRESET: Input, no pullup */
+               DDR_RST &= ~_BV(RST);
                Z80_O_RST = 0;
-               DDR_RST |= _BV(RST);
 
                /* /BUSREQ: Output and high */
                Z80_O_BUSREQ = 1;
@@ -232,6 +255,10 @@ void z80_setup_bus(void)
                        DDR_SS = (DDR_SS & ~_BV(WAIT)) | _BV(RUN) | _BV(STEP);
                }
 
+               reset_polarity = Z80_I_RST;
+               z80_reset_active();
+               DDR_RST |= _BV(RST);
+
                zstate = RESET;
        }
 
@@ -322,8 +349,11 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
        case Reset:
                z80_dbus_set_in();
                z80_addrbus_set_in();
-               Z80_O_RST = 0;
+               z80_reset_active();
                Z80_O_BUSREQ = 1;
+               timer = BUS_TO;
+               while (Z80_I_BUSACK == 0 && timer)
+                       ;
                zstate = RESET;
                break;
 
@@ -331,7 +361,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
                switch (zstate) {
                case RESET:
                        Z80_O_BUSREQ = 0;
-                       Z80_O_RST = 1;
+                       z80_reset_inactive();
                        timer = BUS_TO;
                        while (Z80_I_BUSACK == 1 && timer)
                                ;
@@ -339,7 +369,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
                                z80_addrbus_set_out();
                                zstate = RESET_AQRD;
                        } else {
-                               Z80_O_RST = 0;
+                               z80_reset_active();
                                Z80_O_BUSREQ = 1;
                        }
                        break;
@@ -367,14 +397,20 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
                case RESET_AQRD:
                        z80_dbus_set_in();
                        z80_addrbus_set_in();
-                       Z80_O_RST = 0;
+                       z80_reset_active();
                        Z80_O_BUSREQ = 1;
+                       timer = BUS_TO;
+                       while (Z80_I_BUSACK == 0 && timer)
+                               ;
                        zstate = RESET;
                        break;
                case RUNNING_AQRD:
                        z80_dbus_set_in();
                        z80_addrbus_set_in();
                        Z80_O_BUSREQ = 1;
+                       timer = BUS_TO;
+                       while (Z80_I_BUSACK == 0 && timer)
+                               ;
                        zstate = RUNNING;
                        break;
                default:
@@ -385,7 +421,8 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
        case Run:
                switch (zstate) {
                case RESET:
-                       Z80_O_RST = 1;
+                       _delay_ms(20);          /* TODO: */
+                       z80_reset_inactive();
                        zstate = RUNNING;
                        break;
 
@@ -436,6 +473,41 @@ void z80_setaddress(uint32_t addr)
        PIN_ADB = (((addr >> 16) << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT;
 }
 
+int32_t z80_memsize_detect(void)
+{
+       const uint8_t PATTERN_1 = 0x55;
+       const uint8_t PATTERN_2 = ~PATTERN_1;
+       uint32_t addr;
+
+       if (!(z80_bus_cmd(Request) & ZST_ACQUIRED))
+               return  -EBUSTO;
+
+       uint8_t ram_0 = z80_read(0);
+       uint8_t ram_1 = z80_read(1);
+
+       z80_write(0, ram_0 ^ 0xff);
+       z80_write(1, ram_1);
+       if ((z80_read(0) ^ ram_0) != 0xff) {
+               addr = 0;
+       } else {
+               z80_write(0, PATTERN_1);
+               for (addr=1; addr < CONFIG_SYS_RAMSIZE_MAX; addr <<= 1) {
+                       uint8_t ram_i = z80_read(addr);
+                       z80_write(addr, PATTERN_2);
+                       if (z80_read(0) != PATTERN_1 || z80_read(addr) != PATTERN_2)
+                               break;
+                       z80_write(addr, ram_i);
+               }
+       }
+
+       z80_write(0, ram_0);
+       z80_bus_cmd(Release);
+
+       return addr;
+}
+
+/*--------------------------------------------------------------------------*/
+
 void z80_write(uint32_t addr, uint8_t data)
 {
        z80_setaddress(addr);
@@ -535,6 +607,7 @@ void z80_read_block (uint8_t *dest, uint32_t src, size_t length)
        Z80_O_MREQ = 1;
 }
 
+/*--------------------------------------------------------------------------*/
 
 /*
   0179'                         rx.bs_mask:    ds      1               ; (buf_len - 1)
@@ -675,3 +748,31 @@ void z80_memfifo_putc(fifo_t f, uint8_t val)
        z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
        z80_bus_cmd(Release);
 }
+
+/*--------------------------------------------------------------------------*/
+
+void z80_load_mem(int_fast8_t verbosity,
+                               const FLASH unsigned char data[],
+                               const FLASH unsigned long *sections,
+                               const FLASH unsigned long address[],
+                               const FLASH unsigned long length_of_sections[])
+{
+       uint32_t sec_base = 0;
+
+       if (verbosity > 1)
+               printf_P(PSTR("Loading Z180 memory... \n"));
+
+       for (unsigned sec = 0; sec < *sections; sec++) {
+               if (verbosity > 0) {
+                       printf_P(PSTR("   From: 0x%.5lX to: 0x%.5lX    (%5li bytes)\n"),
+                                       address[sec],
+                                       address[sec]+length_of_sections[sec] - 1,
+                                       length_of_sections[sec]);
+               }
+
+               z80_write_block_P((const FLASH unsigned char *) &data[sec_base],  /* src */
+                               address[sec],                  /* dest */
+                               length_of_sections[sec]);      /* len */
+               sec_base += length_of_sections[sec];
+       }
+}