TRUE equ NOT FALSE\r
\r
\r
-DEBUG equ true\r
-\r
banked equ true\r
\r
;-----------------------------------------------------\r
mrx.fifo_len equ 64\r
mrx.fifo_id equ 1\r
\r
-ci.fifo_len equ 32 ;AVRCON Character I/O via AVR\r
+ci.fifo_len equ 32 ;AVRCON (USB0) Character I/O via AVR\r
ci.fifo_id equ 2\r
co.fifo_len equ 32\r
co.fifo_id equ 3\r
\r
+s0.rx_len equ 128 ;Serial 0 (ASCI0) buffers\r
+s0.rx_id equ 4 ;\r
+s0.tx_len equ 128 ;\r
+s0.tx_id equ 5 ;\r
+\r
s1.rx_len equ 128 ;Serial 1 (ASCI1) buffers\r
-s1.rx_id equ 4 ;\r
+s1.rx_id equ 6 ;\r
s1.tx_len equ 128 ;\r
-s1.tx_id equ 5 ;\r
+s1.tx_id equ 7 ;\r
\r
AVRINT5 equ 4Fh\r
AVRINT6 equ 5Fh\r
;PMSG equ 80h\r
\r
+IDEBASE equ 60h\r
+\r
;-----------------------------------------------------\r
; Definition of (logical) top 2 memory pages\r
\r