*/
#include <avr/io.h>
-#include <util/delay.h>
#include <util/atomic.h>
#include <stdio.h>
#include "debug.h"
z80_dbus_set_in();
z80_addrbus_set_tristate();
- ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
+ ATOMIC_BLOCK(ATOMIC_FORCEON) {
Z80_O_BUSREQ = 1;
Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */
Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */
} fifo_dsc[NUM_FIFOS];
-void z80_memfifo_init(const fifo_t f, uint32_t adr)
+void z80_memfifo_init(const fifo_t f, uint32_t addr)
{
+ fifo_dsc[f].base = addr;
-DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, adr);
+ if (addr != 0) {
- fifo_dsc[f].base = adr;
+DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr);
- z80_bus_cmd(Request);
-
- fifo_dsc[f].mask = z80_read(adr + FIFO_BUFSIZE_MASK);
- fifo_dsc[f].idx_in = z80_read(adr + FIFO_INDEX_IN);
- fifo_dsc[f].idx_out = z80_read(adr + FIFO_INDEX_OUT);
-
- z80_bus_cmd(Release);
+ z80_bus_cmd(Request);
+ fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
+ fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
+ fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
+ z80_bus_cmd(Release);
+ }
}
{
int rc = 1;
- if (((Stat & S_MSG_PENDING) || f != fifo_in) && fifo_dsc[f].base != 0)
- {
+ if (fifo_dsc[f].base != 0) {
uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
uint8_t idx;
return rc;
}
-uint8_t z80_memfifo_getc(const fifo_t f)
+
+uint8_t z80_memfifo_getc_wait(const fifo_t f)
{
uint8_t rc, idx;
return rc;
}
+int z80_memfifo_getc(const fifo_t f)
+{
+ int rc = -1;
+
+ if (fifo_dsc[f].base != 0) {
+ uint8_t idx = fifo_dsc[f].idx_out;
+ z80_bus_cmd(Request);
+ if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
+ rc = z80_read(fifo_dsc[f].base+idx);
+ fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
+ z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
+ }
+ z80_bus_cmd(Release);
+ }
+
+ return rc;
+}
+
void z80_memfifo_putc(fifo_t f, uint8_t val)
{