+/*
+ * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
/**
*
* Pin assignments
*
- * | Z180-Sig | AVR-Port | Dir | Special Function |
+ * | Z180-Sig | AVR-Port | Dir | Special Function |
* +------------+---------------+-------+-----------------------+
- * | A0 | PA 0 | O | |
- * | A1 | PA 1 | O | |
- * | A2 | PA 2 | O | |
- * | A3 | PA 3 | O | |
- * | A4 | PA 4 | O | |
- * | A5 | PA 5 | O | |
- * | A6 | PA 6 | O | |
- * | A7 | PA 7 | O | |
- * | A8 | PC 0 | O | |
- * | A9 | PC 1 | O | |
- * | A10 | PC 2 | O | |
- * | A11 | PC 3 | O | |
- * | A12 | PC 4 | O | |
- * | A13 | PC 5 | O | |
- * | A14 | PC 6 | O | |
- * | A15 | PC 7 | O | |
- * | A16 | PE 2 | O | |
- * | A17 | PE 3 | O | |
- * | A18 | PE 4 | O | |
- * | D0 | PF 0 | I/O | |
- * | D1 | PF 1 | I/O | |
- * | D2 | PF 2 | I/O | |
- * | D3 | PF 3 | I/O | |
- * | D4 | PF 4 | I/O | |
- * | D5 | PF 5 | I/O | |
- * | D6 | PF 6 | I/O | |
- * | D7 | PF 7 | I/O | |
- * | RD | PD 3 | O | |
- * | WR | PD 2 | O | |
- * | MREQ | PD 4 | O | |
- * | RST | PD 5 | O | |
- * | BUSREQ | PD 7 | O | |
- * | BUSACK | PD 6 | I | |
- * | IOCS1 | PE 5 | I | |
- * |* HALT | P | | |
- * |* NMI | P | | |
- * | | P | | |
- * | | P | | af1 USART1_TX |
- * | | P | | af1 USART1_RX |
- * | | P |JTDI | remap SPI1_NSS' |
- * | | P |JTDO | remap SPI1_SCK' |
- * | | P |JTRST | remap SPI1_MISO' |
- * | | P | | remap SPI1_MOSI' |
- * | | P | | af1 OSC32 |
- * | | P | | af1 OSC32 |
-
+ * | A0 | PA 0 | O | |
+ * | A1 | PA 1 | O | |
+ * | A2 | PA 2 | O | |
+ * | A3 | PA 3 | O | |
+ * | A4 | PA 4 | O | |
+ * | A5 | PA 5 | O | |
+ * | A6 | PA 6 | O | |
+ * | A7 | PA 7 | O | |
+ * | A8 | PC 0 | O | |
+ * | A9 | PC 1 | O | |
+ * | A10 | PC 2 | O | |
+ * | A11 | PC 3 | O | |
+ * | A12 | PC 4 | O | |
+ * | A13 | PC 5 | O | |
+ * | A14 | PC 6 | O | |
+ * | A15 | PC 7 | O | |
+ * | A16 | PE 2 | O | |
+ * | A17 | PE 3 | O | |
+ * | A18 | PE 4 | O | |
+ * | D0 | PF 0 | I/O | |
+ * | D1 | PF 1 | I/O | |
+ * | D2 | PF 2 | I/O | |
+ * | D3 | PF 3 | I/O | |
+ * | D4 | PF 4 | I/O | |
+ * | D5 | PF 5 | I/O | |
+ * | D6 | PF 6 | I/O | |
+ * | D7 | PF 7 | I/O | |
+ * | RD | PD 3 | O | |
+ * | WR | PD 2 | O | |
+ * | MREQ | PD 4 | O | |
+ * | RST | PD 5 | O | |
+ * | BUSREQ | PD 7 | O | |
+ * | BUSACK | PD 6 | I | |
+ * | IOCS1 | PE 5 | I | |
+ * |* HALT | P | | |
+ * |* NMI | P | | |
+ * | | P | | |
+ * | | P | | af1 USART1_TX |
+ * | | P | | af1 USART1_RX |
+ * | | P |JTDI | remap SPI1_NSS' |
+ * | | P |JTDO | remap SPI1_SCK' |
+ * | | P |JTRST | remap SPI1_MISO' |
+ * | | P | | remap SPI1_MOSI' |
+ * | | P | | af1 OSC32 |
+ * | | P | | af1 OSC32 |
*/
-#include <avr/io.h>
-#include <util/delay.h>
+
+#include "common.h"
#include <util/atomic.h>
-#include <stdio.h>
#include "debug.h"
#include "z80-if.h"
-/* Number of array elements */
-#define NELEMS(x) (sizeof x/sizeof *x)
-
-struct bits {
- uint8_t b0:1;
- uint8_t b1:1;
- uint8_t b2:1;
- uint8_t b3:1;
- uint8_t b4:1;
- uint8_t b5:1;
- uint8_t b6:1;
- uint8_t b7:1;
-} __attribute__((__packed__));
-
-typedef struct bits pbit_t;
-
-#define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin)
-
//#define P_ZCLK PORTB
//#define ZCLK 5
//#define Z80_I_HALT SBIT(P_HALT, )
+#define BUS_TO 20
+
+
#define MASK(n) ((1<<(n))-1)
#define SMASK(w,s) (MASK(w) << (s))
static zstate_t zstate;
+static volatile uint8_t timer; /* used for bus timeout */
+
+/*---------------------------------------------------------*/
+/* 10Hz timer interrupt generated by OC4A */
+/*---------------------------------------------------------*/
+
+ISR(TIMER4_COMPA_vect)
+{
+
+ uint8_t i = timer;
+
+ if (i)
+ timer = i - 1;
+}
/*--------------------------------------------------------------------------*/
z80_dbus_set_in();
zstate = RESET;
+
+ /* Timer 4 */
+ PRR1 &= ~_BV(PRTIM4);
+ OCR4A = F_CPU / 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */
+ TCCR4B = (0b01<<WGM42)|(0b101<<CS30); /* CTC Mode, Prescaler 1024 */
+ TIMSK4 = _BV(OCIE4A); /* Enable oca interrupt */
+
}
z80_dbus_set_in();
z80_addrbus_set_tristate();
- ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
+ ATOMIC_BLOCK(ATOMIC_FORCEON) {
Z80_O_BUSREQ = 1;
Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */
Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */
}
if (zstate & ZST_ACQUIRED) {
- while(Z80_I_BUSACK == 1)
+ timer = BUS_TO;
+ while (Z80_I_BUSACK == 1 && timer)
;
- z80_addrbus_set_active();
+ if (Z80_I_BUSACK == 0)
+ z80_addrbus_set_active();
}
}
/*
- + | | | | |
+ + | | | | |
+ State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD |
- + | | | | |
- + | 0 | 1 | 2 | 3 |
-Event + | | | | |
+ + | | | | |
+ + | 0 | 1 | 2 | 3 |
+Event + | | | | |
----------------+---------------+---------------+---------------+---------------+
- | | | | |
-Reset | 0 | 0 | 0 | 0 |
- | | | | |
- | | | | |
-Request | 1 | | 3 | |
- | | | | |
- | | | | |
-Release | | 0 | | 2 |
- | | | | |
- | | | | |
-Run | 2 | 3 | | |
- | | | | |
- | | | | |
-Restart | | | 2 | 3 |
- | | | | |
- | | | | |
-M_Cycle | | | | 3 |
- | | | | |
- | | | | |
+ | | | | |
+Reset | 0 | 0 | 0 | 0 |
+ | | | | |
+ | | | | |
+Request | 1 | | 3 | |
+ | | | | |
+ | | | | |
+Release | | 0 | | 2 |
+ | | | | |
+ | | | | |
+Run | 2 | 3 | | |
+ | | | | |
+ | | | | |
+Restart | | | 2 | 3 |
+ | | | | |
+ | | | | |
+M_Cycle | | | | 3 |
+ | | | | |
+ | | | | |
*/
zstate_t z80_bus_cmd(bus_cmd_t cmd)
case RESET:
Z80_O_BUSREQ = 0;
Z80_O_RST = 1;
- while(Z80_I_BUSACK == 1)
+ timer = BUS_TO;
+ while (Z80_I_BUSACK == 1 && timer)
;
- z80_addrbus_set_active();
- zstate = RESET_AQRD;
+ if (Z80_I_BUSACK == 0) {
+ z80_addrbus_set_active();
+ zstate = RESET_AQRD;
+ } else {
+ Z80_O_RST = 0;
+ Z80_O_BUSREQ = 1;
+ }
break;
case RUNNING:
Z80_O_BUSREQ = 0;
- while(Z80_I_BUSACK == 1)
+ timer = BUS_TO;
+ while (Z80_I_BUSACK == 1 && timer)
;
- z80_addrbus_set_active();
- zstate = RUNNING_AQRD;
+ if (Z80_I_BUSACK == 0) {
+ z80_addrbus_set_active();
+ zstate = RUNNING_AQRD;
+ } else {
+ Z80_O_BUSREQ = 1;
+ }
break;
default:
case M_Cycle:
switch (zstate) {
case RUNNING_AQRD:
- z80_busreq_hpulse();
+ z80_busreq_hpulse(); /* TODO: */
break;
default:
break;
{
z80_dbus_set_out();
Z80_O_MREQ = 0;
+ P_DB = data;
while(length--) {
z80_setaddress(addr++);
+ Z80_O_WR = 0;
+ Z80_O_WR = 0;
+ Z80_O_WR = 1;
+ }
+ Z80_O_MREQ = 1;
+}
+
+void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length)
+{
+ uint8_t data;
+
+ z80_dbus_set_out();
+ Z80_O_MREQ = 0;
+ while(length--) {
+ z80_setaddress(dest++);
+ data = *src++;
P_DB = data;
P_DB = data;
Z80_O_WR = 0;
Z80_O_MREQ = 1;
}
-void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length)
+void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length)
{
uint8_t data;
Z80_O_MREQ = 1;
}
+void z80_read_block (uint8_t *dest, uint32_t src, size_t length)
+{
+ uint8_t data;
+
+ Z80_O_MREQ = 0;
+ z80_dbus_set_in();
+ while(length--) {
+ z80_setaddress(src++);
+ Z80_O_RD = 0;
+ Z80_O_RD = 0;
+ Z80_O_RD = 0;
+ data = PIN_DB;
+ Z80_O_RD = 1;
+ *dest++ = data;
+ }
+ Z80_O_MREQ = 1;
+}
+
+
/*
0179' rx.bs_mask: ds 1 ; (buf_len - 1)
017A' rx.in_idx: ds 1 ;
} fifo_dsc[NUM_FIFOS];
-void z80_memfifo_init(const fifo_t f, uint32_t adr)
+void z80_memfifo_init(const fifo_t f, uint32_t addr)
{
+ fifo_dsc[f].base = addr;
-DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, adr);
-
- fifo_dsc[f].base = adr;
-
- z80_bus_cmd(Request);
-
- fifo_dsc[f].mask = z80_read(adr + FIFO_BUFSIZE_MASK);
- fifo_dsc[f].idx_in = z80_read(adr + FIFO_INDEX_IN);
- fifo_dsc[f].idx_out = z80_read(adr + FIFO_INDEX_OUT);
+DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr);
- z80_bus_cmd(Release);
+ if (addr != 0) {
+ z80_bus_cmd(Request);
+ fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
+ fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
+ fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
+ z80_bus_cmd(Release);
+ }
}
{
int rc = 1;
- if (((Stat & S_MSG_PENDING) || f != fifo_in) && fifo_dsc[f].base != 0)
- {
+ if (fifo_dsc[f].base != 0) {
uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
uint8_t idx;
int z80_memfifo_is_full(const fifo_t f)
{
- int rc = 1;
+ int rc = 0;
if (fifo_dsc[f].base != 0) {
z80_bus_cmd(Request);
return rc;
}
-uint8_t z80_memfifo_getc(const fifo_t f)
+
+uint8_t z80_memfifo_getc_wait(const fifo_t f)
{
uint8_t rc, idx;
return rc;
}
+int z80_memfifo_getc(const fifo_t f)
+{
+ int rc = -1;
+
+ if (fifo_dsc[f].base != 0) {
+ uint8_t idx = fifo_dsc[f].idx_out;
+ z80_bus_cmd(Request);
+ if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
+ rc = z80_read(fifo_dsc[f].base+idx);
+ fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
+ z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
+ }
+ z80_bus_cmd(Release);
+ }
+
+ return rc;
+}
+
void z80_memfifo_putc(fifo_t f, uint8_t val)
{
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