+
+ /* SPI as master */
+ PRR0 &= ~_BV(PRSPI);
+ SPI_DDR = (SPI_DDR & ~_BV(SPI_MISO))
+ | _BV(SPI_MOSI) | _BV(SPI_SCK) | _BV(SPI_SS);
+ SPI_PORT = (SPI_PORT & ~(_BV(SPI_MOSI) | _BV(SPI_SCK)))
+ | _BV(SPI_SS);
+
+ /* INT5, INT6: falling edge */
+ EICRB = (EICRB & ~((0b11 << ISC50) | (0b11 << ISC60))) |
+ (0b10 << ISC50) | (0b10 << ISC60);
+ /* Reset pending ints */
+ EIFR |= _BV(INTF5) | _BV(INTF6);
+ /* Enable INT5, and INT6 */
+ EIMSK |= _BV(INT5) | _BV(INT6);