#define WR 2
#define P_BUSREQ PORTD
#define BUSREQ 7
+#define PIN_BUSREQ PIND
#define DDR_BUSREQ DDRD
#define P_BUSACK PORTD
#define PIN_BUSACK PIND
#define Z80_O_RD SBIT(P_RD, 3)
#define Z80_O_WR SBIT(P_WR, 2)
#define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
+#define Z80_I_BUSREQ SBIT(PIN_BUSREQ, 7)
//#define Z80_O_NMI SBIT(P_NMI, )
#define Z80_O_RST SBIT(P_RST, 5)
#define Z80_I_RST SBIT(PIN_RST, 5)
return zstate;
}
+void z80_toggle_reset(void)
+{
+ Z80_I_RST = 1;
+}
+
+void z80_toggle_busreq(void)
+{
+ Z80_I_BUSREQ = 1;
+}
+
static void z80_busreq_hpulse(void)
{
busack_cycles = 0;
busack_cycles_ovl = 0;
ATOMIC_BLOCK(ATOMIC_FORCEON) {
- //z80_reset_inactive();
Z80_I_RST = 1; /* Toggle RESET --> inactive */
OCR4B = TCNT4;
TIFR4 = _BV(OCF4B); /* Clear compare match flag */
+// TIMSK4 &= ~_BV(OCIE4A); /* Disable Output Compare A interrupt */
}
TIMSK4 |= _BV(OCIE4B); /* Enable compare match interrupt */
ovl_cnt = busack_cycles_ovl;
ifr = TIFR4;
TIMSK4 &= ~_BV(OCIE4B); /* Disable compare match interrupt */
+// TIMSK4 |= _BV(OCIE4A); /* Enable Output Compare A interrupt */
}
if (Z80_I_BUSACK == 0) {
if ((ifr & _BV(OCF4B)) && !(tcnt & (1<<15)))