FALSE equ 0\r
TRUE equ NOT FALSE\r
\r
+\r
+DEBUG equ true\r
+\r
banked equ true\r
\r
;-----------------------------------------------------\r
FOSC equ AVRCLK/2 ;Oscillator frequency [KHz]\r
PHI equ FOSC*2 ;CPU frequency (clock doubler enabled)\r
\r
+;----------------------------------------------------------------------\r
+; Baudrate Generator for x16 clock mode:\r
+; TC = (f PHI / (32 * baudrate)) - 2\r
+;\r
+; PHI [MHz]: 9.216 18.432\r
+; baudrate TC TC\r
+; ----------------------\r
+; 115200 - 3\r
+; 57600 3 8\r
+; 38400 - 13\r
+; 19200 13 28\r
+; 9600 28 58\r
+\r
+\r
;-----------------------------------------------------\r
; Programmable Reload Timer (PRT)\r
\r
;-----------------------------------------------------\r
; MMU\r
\r
-COMMON_SIZE equ 4*1024 ;Common Area size in bytes\r
+COMMON_SIZE equ 16*1024 ;Common Area size in bytes\r
;must be multiple of 4K\r
\r
if (COMMON_SIZE mod 1000h)\r
endif\r
\r
\r
-DRSTNUM equ 30h ;DDTZ Restart vector (breakpoints)\r
+DDTZRSTVEC equ 030h ;DDTZ Restart vector (breakpoints)\r
\r
+INIDONE equ 03Fh ;CP/M skip hw init, if this address\r
+INIDONEVAL equ 080h ; is set to this value.\r
\r
-mtx.fifo_len equ 32 ;Message transfer fifos\r
-mtx.fifo_id equ 0 ; This *must* have #0\r
+mtx.fifo_len equ 32 ;Message transfer fifos\r
+mtx.fifo_id equ 0 ; This *must* have #0\r
mrx.fifo_len equ 32\r
-mrx.fifo_id equ 1\r
+mrx.fifo_id equ 1\r
\r
ci.fifo_len equ 32 ;AVRCON Character I/O via AVR\r
ci.fifo_id equ 2\r
; Definition of (logical) top 2 memory pages\r
\r
sysram_start equ 0FE00h\r
-stacksize equ 80\r
+bs$stack$size equ 80\r
\r
isvsw_loc equ 0FEE0h\r
\r
dseg\r
ds ??ps.len\r
endm\r
+\r
+;-----------------------------------------------------\r
+\r
+b0call macro address\r
+ call _b0call\r
+ dw address\r
+ endm\r