include config.inc\r
include z180reg.inc\r
include z180.lib\r
- \r
+\r
;CR equ 0dh\r
\r
\r
\r
cseg\r
\r
- jp start \r
+ jp start\r
\r
; restart vectors\r
\r
dmclrt: ;clear ram per dma\r
db dmct_e-dmclrt-2 ;\r
db sar0l ;first port\r
- dw nullbyte ;src (fixed) \r
+ dw nullbyte ;src (fixed)\r
nullbyte:\r
db 000h ;src\r
dw romend ;dst (inc), start after "rom" code\r
dw 0-romend ;count (64k)\r
dmct_e:\r
\r
-\r
INIWAITS defl CWAITIO\r
if ROMSYS\r
INIWAITS defl INIWAITS+CWAITROM\r
jp bpent ;0044 yes, handle\r
\r
??st01:\r
- ld a,i ;0047 I register == 0 ? \r
+ ld a,i ;0047 I register == 0 ?\r
jr z,??st02 ;004b yes, harware reset\r
- pop af ;004d \r
+ pop af ;004d\r
jp bpent ;004e no, allready set up\r
\r
??st02:\r
ld a,CWAITIO\r
out0 (dcntl),a ; wait states\r
\r
+ ld a,M_NCD ;No Clock Divide\r
+ out0 (ccr),a\r
+ ld a,M_X2CM ;X2 Clock Multiplier\r
+ out0 (cmr),a\r
+\r
; search warm start mark\r
\r
ld ix,mark_55AA ;00b8 ; top of common area\r
ld a,071h ;00bc\r
ex af,af' ;00be ;for cbr = 0x70 downto 0x40\r
swsm_l:\r
- ex af,af' ;00bf \r
+ ex af,af' ;00bf\r
dec a ;00c0\r
cp 03fh ;00c1\r
jr z,kstart ;00c3 ; break (mark not found)\r
??f_0:\r
out0 (cbr),a ;00f9\r
\r
- ld (ix+0),a ;0103 \r
+ ld (ix+0),a ;0103\r
cpl\r
- ld (ix+1),a ;0103 \r
+ ld (ix+1),a ;0103\r
cpl\r
add a,8 ;010a next 'bank'\r
cp 078h ;010c stop at 078000\r
add a,8\r
cp 078h ; stop at 078000\r
jr nz,??cp_0\r
- \r
+\r
;\r
; ram test found 1 or more error free blocks (32k)\r
;\r
alloc:\r
out0 (cbr),c ;01de\r
ld sp,$stack ;01e1\r
- \r
+\r
; Clear RAM using DMA0\r
\r
ld hl,dmclrt ;load DMA registers\r
out0 (dmode),a ;01f1\r
\r
ld b,512/64\r
- ld a,062h ;01f4 enable dma0, \r
+ ld a,062h ;01f4 enable dma0,\r
??cl_1:\r
out0 (dstat),a ;01f9 clear (up to) 64k\r
djnz ??cl_1 ; end of RAM?\r
- \r
+\r
; Init bank manager\r
- \r
+\r
ld hl,banktabsys ;020f\r
ld (hl),c ; Common area\r
inc hl ;0213\r
ld (hl),0e0h ; mark as sys ("rom"/monitor)\r
inc hl\r
djnz ??a_0\r
- \r
+\r
rr d ; shift out bit for block 0\r
rr e ;\r
ld c,15 ;022c 15*32k remaining blocks\r
rr d ;\r
rr e\r
adc a,0 ; ==> 0xff : block ok\r
- ld b,32/4 ; 32k == 8 * 4k \r
+ ld b,32/4 ; 32k == 8 * 4k\r
l0236h:\r
ld (hl),a ;\r
inc hl ;\r
djnz l0236h ;\r
dec c ;\r
jr nz,l022eh ;next 32k block\r
- \r
+\r
ld hl,memalv+0ch ;memalv+0ch\r
ld a,(banktabsys) ;\r
call add_hl_a\r
ld (hl),0efh ;alloc common\r
call gencrc_alv\r
\r
- ld hl,0000h ;bank # \r
+ ld hl,0000h ;bank #\r
ld bc,0f0fh ; size (?) (4k blocks)\r
xor a ;\r
call sub_0420h ;alloc mem for bank 0\r
call prt0_init\r
\r
\r
- call bufferinit\r
+;;; call bufferinit\r
\r
\r
call $coninit\r
call $cists ;0287\r
or a ;028a\r
call nz,$ci ;028d\r
- \r
- ld a,(banktab) ; \r
- ld e,a ; \r
+\r
+ ld a,(banktab) ;\r
+ ld e,a ;\r
jp ddtz ;0290\r
- \r
+\r
\r
;\r
;----------------------------------------------------------------------\r
;\r
\r
- extrn msginit,msg.sout,msg_fifo\r
- extrn tx.buf,rx.buf\r
-\r
-\r
;TODO: Make a ringbuffer module.\r
\r
global buf.init\r
- \r
+\r
buf.init:\r
ld (ix+o.in_idx),0\r
ld (ix+o.out_idx),0\r
\r
;----------------------------------------------------------------------\r
\r
+.comment *\r
+\r
+ extrn msginit,msg.sout,msg_fifo\r
+ extrn tx.buf,rx.buf\r
+\r
+\r
bufferinit:\r
call msginit\r
- \r
+\r
ld hl,buffers\r
ld bc,0300h\r
bfi_1:\r
rept 20\r
db 0\r
endm\r
- \r
+\r
buffers:\r
dw msg_fifo\r
dw tx.buf\r
dw rx.buf\r
- \r
-inimsg: \r
+\r
+inimsg:\r
db inimsg_e - $ -2\r
db PMSG\r
db 81h\r
db 0\r
dw 0\r
db 0\r
-inimsg_e\r
+inimsg_e:\r
+\r
+ *\r
\r
;\r
;----------------------------------------------------------------------\r
ld d,high sp.int0\r
ld a,low sp.int0\r
ld b,9\r
-ivt_i1: \r
+ivt_i1:\r
ld (hl),a\r
inc l\r
ld (hl),d\r
djnz ivt_i1\r
ret\r
\r
+;----------------------------------------------------------------------\r
\r
prt0_init:\r
ld a,i\r
ld hl,prt0itab\r
call io.ini.m\r
ret\r
- \r
+\r
prt0itab:\r
db prt0it_e-prt0itab-2\r
db tmdr0l\r
db M_TIE0+M_TDE0 ;enable timer 0 interrupt and down count.\r
prt0it_e:\r
\r
+\r
;\r
;----------------------------------------------------------------------\r
;\r
inc hl\r
ld c,(hl)\r
inc hl\r
- otimr \r
- pop bc \r
+ otimr\r
+ pop bc\r
ret\r
- \r
+\r
io.ini.l:\r
;\r
\r
pop hl ;041e\r
ret ;041f\r
\r
+;----------------------------------------------------------------------\r
+\r
;\r
; alloc\r
;\r
;\r
; ret:\r
; a: 0 == ok\r
-; 1 == \r
+; 1 ==\r
; 2 == no bank # in requested range\r
; ff == crc error\r
;\r
sub_0420h:\r
call checkcrc_alv ;0420\r
jr nz,l049ch ;0424 crc error, tables corrupt\r
- \r
+\r
call sub_049dh ;0427 bank # in req. range available?\r
jr c,l0499h ;042a\r
push ix ;042c\r
djnz l043dh ;0442\r
jr l0464h ;0444\r
l0446h:\r
- push hl ;0446 \r
+ push hl ;0446\r
pop ix ;0447 free blocks start here\r
ld e,000h ;0449\r
jr l0451h ;044b\r
djnz l044dh ;0453\r
jr l0464h ;0455\r
\r
-; end of free blocks run. \r
+; end of free blocks run.\r
\r
l0457h:\r
ld a,d ;0457\r
cp e ;0458 nr of blocks >= requested ?\r
- jr nc,l0441h ;0459 \r
+ jr nc,l0441h ;0459\r
\r
ld d,e ;045b\r
push ix ;045c\r
inc e ;04a1 test next #\r
ld a,d ;04a2\r
cp e ;04a3\r
- jr c,l04b1h ;04a4 \r
+ jr c,l04b1h ;04a4\r
ld a,e ;04a6\r
ld hl,memalv ;04a7\r
ld bc,alv_len ;04aa\r
;\r
; OP: ahl = (a<<12) + (d<<8) + e\r
;\r
-;out ehl: Phys. (linear) Address\r
+;out ahl: Phys. (linear) Address\r
\r
\r
log2phys:\r
mlt bc ;bc = a<<4\r
ld l,d ;\r
ld h,0 ;\r
- add hl,bc ;bc + d == a<<4 + d \r
+ add hl,bc ;bc + d == a<<4 + d\r
ld a,h ;\r
ld h,l ;\r
ld l,e ;\r
;\r
\r
add_hl_a:\r
- add a,l \r
- ld l,a \r
- ret nc \r
- inc h \r
- ret \r
+ add a,l\r
+ ld l,a\r
+ ret nc\r
+ inc h\r
+ ret\r
\r
; ---------------------------------------------------------\r
\r
; Trampoline for interrupt routines in banked ram.\r
; Switch stack pointer to "system" stack in top ram\r
; Save cbar\r
- \r
+\r
isv_sw: ;\r
ex (sp),hl ; save hl, return adr in hl\r
push de ;\r
\r
; ---------------------------------------------------------\r
\r
+\r
iprt0:\r
push af\r
push hl\r
tim_ms: db 0\r
tim_s: dw 0\r
.dephase\r
- \r
+\r
;-----------------------------------------------------\r
\r
dseg\r
alv_len equ $-memalv\r
crc_len equ $-banktabsys\r
\r
-crc_memalv: \r
+crc_memalv:\r
ds 2 ;\r
\r
cseg\r