#define WR 2
#define P_BUSREQ PORTD
#define BUSREQ 7
+#define PIN_BUSREQ PIND
#define DDR_BUSREQ DDRD
#define P_BUSACK PORTD
#define PIN_BUSACK PIND
#define Z80_O_RD SBIT(P_RD, 3)
#define Z80_O_WR SBIT(P_WR, 2)
#define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
+#define Z80_I_BUSREQ SBIT(PIN_BUSREQ, 7)
//#define Z80_O_NMI SBIT(P_NMI, )
#define Z80_O_RST SBIT(P_RST, 5)
#define Z80_I_RST SBIT(PIN_RST, 5)
static zstate_t zstate;
static volatile uint8_t timer; /* used for bus timeout */
-static bool reset_polarity;
+
+
+static volatile uint16_t busack_cycles_ovl;
+
+static uint32_t busack_cycles;
+
+ISR(TIMER4_COMPB_vect)
+{
+ busack_cycles_ovl++;
+}
/*---------------------------------------------------------*/
/* 10Hz timer interrupt generated by OC5A */
ISR(TIMER5_COMPA_vect)
{
-
uint8_t i = timer;
if (i)
static void z80_reset_active(void)
{
- if (reset_polarity)
+ if (Stat & S_RESET_POLARITY)
Z80_O_RST = 1;
else
Z80_O_RST = 0;
static void z80_reset_inactive(void)
{
- if (reset_polarity)
+ if (Stat & S_RESET_POLARITY)
Z80_O_RST = 0;
else
Z80_O_RST = 1;
DDR_SS = (DDR_SS & ~_BV(WAIT)) | _BV(RUN) | _BV(STEP);
}
- reset_polarity = Z80_I_RST;
+ if (Z80_I_RST)
+ Stat |= S_RESET_POLARITY;
+ else
+ Stat &= ~S_RESET_POLARITY;
z80_reset_active();
DDR_RST |= _BV(RST);
}
+uint32_t z80_get_busreq_cycles(void)
+{
+ return busack_cycles;
+}
+
zstate_t z80_bus_state(void)
{
return zstate;
}
+void z80_toggle_reset(void)
+{
+ Z80_I_RST = 1;
+}
+
+void z80_toggle_busreq(void)
+{
+ Z80_I_BUSREQ = 1;
+}
+
static void z80_busreq_hpulse(void)
{
z80_dbus_set_in();
z80_addrbus_set_in();
z80_reset_active();
+ _delay_us(10);
Z80_O_BUSREQ = 1;
timer = BUS_TO;
while (Z80_I_BUSACK == 0 && timer)
switch (zstate) {
case RESET:
Z80_O_BUSREQ = 0;
- z80_reset_inactive();
- timer = BUS_TO;
+ timer = 255; //BUS_TO;
+
+ uint16_t tcnt;
+ uint16_t ovl_cnt;
+ uint8_t ifr;
+ busack_cycles = 0;
+ busack_cycles_ovl = 0;
+ ATOMIC_BLOCK(ATOMIC_FORCEON) {
+ Z80_I_RST = 1; /* Toggle RESET --> inactive */
+ OCR4B = TCNT4;
+ TIFR4 = _BV(OCF4B); /* Clear compare match flag */
+// TIMSK4 &= ~_BV(OCIE4A); /* Disable Output Compare A interrupt */
+ }
+ TIMSK4 |= _BV(OCIE4B); /* Enable compare match interrupt */
+
while (Z80_I_BUSACK == 1 && timer)
;
+
+ ATOMIC_BLOCK(ATOMIC_FORCEON) {
+ tcnt = TCNT4 - OCR4B;
+ ovl_cnt = busack_cycles_ovl;
+ ifr = TIFR4;
+ TIMSK4 &= ~_BV(OCIE4B); /* Disable compare match interrupt */
+// TIMSK4 |= _BV(OCIE4A); /* Enable Output Compare A interrupt */
+ }
if (Z80_I_BUSACK == 0) {
+ if ((ifr & _BV(OCF4B)) && !(tcnt & (1<<15)))
+ ovl_cnt++;
+ busack_cycles = tcnt + ((uint32_t) ovl_cnt << 16);
z80_addrbus_set_out();
zstate = RESET_AQRD;
+// debug("### ovl: %u, ifr: %u, beg: %u, end: %u\n", ovl_cnt,
+// (ifr & _BV(OCF4B)) != 0, OCR4B, tcnt);
} else {
z80_reset_active();
Z80_O_BUSREQ = 1;
z80_dbus_set_in();
z80_addrbus_set_in();
z80_reset_active();
+ _delay_us(10);
Z80_O_BUSREQ = 1;
timer = BUS_TO;
while (Z80_I_BUSACK == 0 && timer)
return zstate;
}
+/*--------------------------------------------------------------------------*/
+
+#define DEBUG_FREQ 0 /* set to 1 to debug */
+
+#define debug_cpu(fmt, args...) \
+ debug_cond(DEBUG_FREQ, fmt, ##args)
+
+#if 0
+static
+char * ulltoa (uint64_t val, char *s)
+{
+ char *p = s;
+
+ while (val >= 10) {
+ *p++ = (val % 10) + '0';
+ val = val / 10;
+ }
+ *p++ = val + '0';
+ *p = '\0';
+
+ return strrev(s);
+}
+#endif
+
+uint32_t z80_measure_phi(uint_fast8_t cycles)
+{
+ uint16_t ref_stop;
+ uint16_t ref_ovfl;
+ uint8_t x_ovfl;
+ uint32_t x_freq;
+
+
+ PRR1 &= ~_BV(PRTIM3);
+ TCCR3A = 0;
+ TCCR3B = 0b000<<CS30; /* stop counter */
+ TCNT3 = 0;
+ x_ovfl = 0;
+ TIFR3 = _BV(TOV3);
+ ref_ovfl = 0;
+
+ ATOMIC_BLOCK(ATOMIC_FORCEON) {
+ EIFR = _BV(INTF6); /* Reset pending int */
+ while ((EIFR & _BV(INTF6)) == 0) /* Wait for falling edge */
+ ;
+ OCR4B = TCNT4;
+ TCCR3B = 0b110<<CS30; /* Count falling edges on T3 (==INT6) */
+ TIFR4 = _BV(OCF4B); /* clear compare match flag */
+
+ while (ref_ovfl < 60) {
+ if ((TIFR4 & _BV(OCF4B)) != 0) {
+ TIFR4 = _BV(OCF4B);
+ ++ref_ovfl;
+ }
+ if ((TIFR3 & _BV(TOV3)) != 0) {
+ TIFR3 = _BV(TOV3);
+ ++x_ovfl;
+ }
+ }
+
+ EIFR = _BV(INTF6);
+ for (;;) {
+ if (EIFR & _BV(INTF6)) {
+ TCCR3B = 0b000<<CS30; /* stop counter */
+ ref_stop = TCNT4;
+ break;
+ }
+ if ((TIFR4 & _BV(OCF4B)) != 0) {
+ TIFR4 = _BV(OCF4B);
+ ++ref_ovfl;
+ }
+ }
+ }
+
+ if ((TIFR3 & _BV(TOV3)) != 0) {
+ TIFR3 = _BV(TOV3);
+ x_ovfl++;
+ }
+
+ uint32_t ref_cnt = (ref_stop - OCR4B) + ((uint32_t)ref_ovfl << 16);
+ uint32_t x_cnt = TCNT3 + ((uint32_t) x_ovfl << 16);
+ uint64_t x_tmp = (uint64_t) 100000 * (x_cnt * cycles);
+
+ /* Stop Timer */
+ TCCR3B = 0;
+ PRR1 |= _BV(PRTIM3);
+
+ debug_cpu("\nx_ovfl: %6u, TCNT3: %6u, cycles: %3u\n", x_ovfl, TCNT3, cycles);
+ debug_cpu("ref_ovfl: %6u, ref_...: %6u\n", ref_ovfl, ref_stop-OCR4B);
+ debug_cpu("x_cnt: %9lu, ref_cnt: %9lu\n", x_cnt, ref_cnt);
+
+ x_tmp = (x_tmp * getenv_ulong(PSTR(ENV_FMON), 10, F_CPU) + (ref_cnt / 2)) / ref_cnt;
+
+ /* round to 5 decimal digits */
+ int_fast8_t sc = 5;
+ for ( ; sc > 0 || x_tmp >= 100000; sc--) x_tmp = (x_tmp + 5)/10;
+ x_freq = x_tmp;
+ for ( ; sc < 0; sc++) x_freq *= 10;
+
+ return x_freq;
+}
/*--------------------------------------------------------------------------*/
return addr;
}
+/*--------------------------------------------------------------------------*/
+
void z80_write(uint32_t addr, uint8_t data)
{
z80_setaddress(addr);
Z80_O_MREQ = 1;
}
+/*--------------------------------------------------------------------------*/
/*
0179' rx.bs_mask: ds 1 ; (buf_len - 1)
z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
z80_bus_cmd(Release);
}
+
+/*--------------------------------------------------------------------------*/
+
+void z80_load_mem(int_fast8_t verbosity,
+ const FLASH unsigned char data[],
+ const FLASH unsigned long *sections,
+ const FLASH unsigned long address[],
+ const FLASH unsigned long length_of_sections[])
+{
+ uint32_t sec_base = 0;
+
+ if (verbosity > 1)
+ printf_P(PSTR("Loading Z180 memory... \n"));
+
+ for (unsigned sec = 0; sec < *sections; sec++) {
+ if (verbosity > 0) {
+ printf_P(PSTR(" From: 0x%.5lX to: 0x%.5lX (%5li bytes)\n"),
+ address[sec],
+ address[sec]+length_of_sections[sec] - 1,
+ length_of_sections[sec]);
+ }
+
+ z80_write_block_P((const FLASH unsigned char *) &data[sec_base], /* src */
+ address[sec], /* dest */
+ length_of_sections[sec]); /* len */
+ sec_base += length_of_sections[sec];
+ }
+}