X-Git-Url: http://cloudbase.mooo.com/gitweb/z180-stamp.git/blobdiff_plain/51dd0948df5ed53b11cab4e909e19ee7cee363c5..aea51b6c4c93c56715f50e64d424e1181c6d0242:/avr/z80-if.c

diff --git a/avr/z80-if.c b/avr/z80-if.c
index 5d88842..5a4104d 100644
--- a/avr/z80-if.c
+++ b/avr/z80-if.c
@@ -72,6 +72,7 @@
 #define WR		2
 #define P_BUSREQ	PORTD
 #define BUSREQ		7
+#define PIN_BUSREQ	PIND
 #define DDR_BUSREQ	DDRD
 #define P_BUSACK	PORTD
 #define PIN_BUSACK	PIND
@@ -105,6 +106,7 @@
 #define Z80_O_RD	SBIT(P_RD, 3)
 #define Z80_O_WR	SBIT(P_WR, 2)
 #define Z80_O_BUSREQ	SBIT(P_BUSREQ, 7)
+#define Z80_I_BUSREQ	SBIT(PIN_BUSREQ, 7)
 //#define Z80_O_NMI	SBIT(P_NMI, )
 #define Z80_O_RST	SBIT(P_RST, 5)
 #define Z80_I_RST	SBIT(PIN_RST, 5)
@@ -145,14 +147,15 @@ void z80_bus_request_or_exit(void)
 static zstate_t zstate;
 static volatile uint8_t timer;		/* used for bus timeout */
 
-#if 0
-static volatile uint16_t req_cycles_ovl;
+
+static volatile uint16_t busack_cycles_ovl;
+
+static uint32_t busack_cycles;
 
 ISR(TIMER4_COMPB_vect)
 {
-	req_cycles_ovl++;
+	busack_cycles_ovl++;
 }
-#endif
 
 /*---------------------------------------------------------*/
 /* 10Hz timer interrupt generated by OC5A                  */
@@ -282,11 +285,26 @@ void z80_setup_bus(void)
 }
 
 
+uint32_t z80_get_busreq_cycles(void)
+{
+	return busack_cycles;
+}
+
 zstate_t z80_bus_state(void)
 {
 	return zstate;
 }
 
+void z80_toggle_reset(void)
+{
+	Z80_I_RST = 1;
+}
+
+void z80_toggle_busreq(void)
+{
+	Z80_I_BUSREQ = 1;
+}
+
 
 static void z80_busreq_hpulse(void)
 {
@@ -373,13 +391,39 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
 		switch (zstate) {
 		case RESET:
 			Z80_O_BUSREQ = 0;
-			z80_reset_inactive();
-			timer = BUS_TO;
+			timer = 255; //BUS_TO;
+
+			uint16_t tcnt;
+			uint16_t ovl_cnt;
+			uint8_t ifr;
+			busack_cycles = 0;
+			busack_cycles_ovl = 0;
+			ATOMIC_BLOCK(ATOMIC_FORCEON) {
+				Z80_I_RST = 1;					/* Toggle RESET  --> inactive */
+				OCR4B = TCNT4;
+				TIFR4 = _BV(OCF4B);				/* Clear compare match flag */
+//				TIMSK4 &= ~_BV(OCIE4A);		/* Disable Output Compare A interrupt */
+			}
+			TIMSK4 |= _BV(OCIE4B);				/* Enable compare match interrupt */
+
 			while (Z80_I_BUSACK == 1 && timer)
 				;
+
+			ATOMIC_BLOCK(ATOMIC_FORCEON) {
+				tcnt = TCNT4 - OCR4B;
+				ovl_cnt = busack_cycles_ovl;
+				ifr = TIFR4;
+				TIMSK4 &= ~_BV(OCIE4B);			/* Disable compare match interrupt */
+//				TIMSK4 |= _BV(OCIE4A);		/* Enable Output Compare A interrupt */
+			}
 			if (Z80_I_BUSACK == 0) {
+				if ((ifr & _BV(OCF4B)) && !(tcnt & (1<<15)))
+					ovl_cnt++;
+				busack_cycles = tcnt + ((uint32_t) ovl_cnt << 16);
 				z80_addrbus_set_out();
 				zstate = RESET_AQRD;
+//				debug("### ovl: %u, ifr: %u, beg: %u, end: %u\n", ovl_cnt,
+//								(ifr & _BV(OCF4B)) != 0,	OCR4B, tcnt);
 			} else {
 				z80_reset_active();
 				Z80_O_BUSREQ = 1;