X-Git-Url: http://cloudbase.mooo.com/gitweb/z180-stamp.git/blobdiff_plain/72f5882239bb88b8a68f305802e0dde37a975604..4bc81323e51ac138e733c14eeb6f283ae706e904:/avr/z80-if.c diff --git a/avr/z80-if.c b/avr/z80-if.c index 9ee9cb0..392597e 100644 --- a/avr/z80-if.c +++ b/avr/z80-if.c @@ -55,6 +55,7 @@ #include #include +#include #include #include "debug.h" #include "z80-if.h" @@ -137,39 +138,6 @@ struct bits { //#define Z80_I_HALT SBIT(P_HALT, ) -#if 0 -void z80_busreq(level_t level) -{ - Z80_O_BUSREQ = level; -} -#endif - -void z80_reset(level_t level) -{ - Z80_O_RST = level; - if (level) - Stat |= S_Z180_RUNNING; - else - Stat &= ~S_Z180_RUNNING; -} - - -void z80_reset_pulse(void) -{ - Z80_O_RST = 0; - _delay_us(10); - Z80_O_RST = 1; - Stat |= S_Z180_RUNNING; -} - -#if 0 -int z80_stat_halt(void) -{ - return Z80_I_HALT; -} -#endif - - #define MASK(n) ((1<<(n))-1) #define SMASK(w,s) (MASK(w) << (s)) @@ -180,7 +148,9 @@ typedef union { uint16_t w[2]; uint8_t b[4]; } addr_t; - + + +static zstate_t zstate; /*--------------------------------------------------------------------------*/ @@ -216,18 +186,27 @@ static void z80_setup_addrbus_active(void) } - static void z80_setup_dbus_in(void) { DDR_DB = 0; P_DB = 0; } + static void z80_setup_dbus_out(void) { DDR_DB = 0xff; } + +static void z80_reset_pulse(void) +{ + Z80_O_RST = 0; + _delay_us(10); + Z80_O_RST = 1; +} + + void z80_setup_bus(void) { /* /ZRESET: Output and low */ @@ -249,34 +228,163 @@ void z80_setup_bus(void) z80_setup_addrbus_tristate(); z80_setup_dbus_in(); - Stat &= ~S_Z180_RUNNING; + zstate = RESET; } -/*--------------------------------------------------------------------------*/ -void z80_request_bus(void) +zstate_t z80_bus_state(void) { - Z80_O_BUSREQ = 0; - - if (!(Stat & S_Z180_RUNNING)) - Z80_O_RST = 1; - - while(Z80_I_BUSACK == 1); - z80_setup_addrbus_active(); + return zstate; } -void z80_release_bus(void) + +static void z80_busreq_hpulse(void) { z80_setup_dbus_in(); z80_setup_addrbus_tristate(); - if (!(Stat & S_Z180_RUNNING)) - Z80_O_RST = 0; + ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { + Z80_O_BUSREQ = 1; + Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */ + Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */ + } - Z80_O_BUSREQ = 1; - //while(Z80_I_BUSACK == 0); + if (zstate & ZST_ACQUIRED) { + while(Z80_I_BUSACK == 1) + ; + z80_setup_addrbus_active(); + } } + +/* + + + | | | | | + + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD | + + | | | | | + + | 0 | 1 | 2 | 3 | +Event + | | | | | +----------------+---------------+---------------+---------------+---------------+ + | | | | | +Reset | 0 | 0 | 0 | 0 | + | | | | | + | | | | | +Request | 1 | | 3 | | + | | | | | + | | | | | +Release | | 0 | | 2 | + | | | | | + | | | | | +Run | 2 | 3 | | | + | | | | | + | | | | | +Restart | | | 2 | 3 | + | | | | | + | | | | | +M_Cycle | | | | 3 | + | | | | | + | | | | | +*/ + +zstate_t z80_bus_cmd(bus_cmd_t cmd) +{ + switch (cmd) { + + case Reset: + z80_setup_dbus_in(); + z80_setup_addrbus_tristate(); + Z80_O_RST = 0; + Z80_O_BUSREQ = 1; + zstate = RESET; + break; + + case Request: + switch (zstate) { + case RESET: + Z80_O_BUSREQ = 0; + Z80_O_RST = 1; + while(Z80_I_BUSACK == 1) + ; + z80_setup_addrbus_active(); + zstate = RESET_AQRD; + break; + + case RUNNING: + Z80_O_BUSREQ = 0; + while(Z80_I_BUSACK == 1) + ; + z80_setup_addrbus_active(); + zstate = RUNNING_AQRD; + break; + + default: + break; + } + break; + + case Release: + switch (zstate) { + case RESET_AQRD: + z80_setup_dbus_in(); + z80_setup_addrbus_tristate(); + Z80_O_RST = 0; + Z80_O_BUSREQ = 1; + zstate = RESET; + break; + case RUNNING_AQRD: + z80_setup_dbus_in(); + z80_setup_addrbus_tristate(); + Z80_O_BUSREQ = 1; + zstate = RUNNING; + break; + default: + break; + } + break; + + case Run: + switch (zstate) { + case RESET: + Z80_O_RST = 1; + zstate = RUNNING; + break; + + case RESET_AQRD: + z80_setup_dbus_in(); + z80_setup_addrbus_tristate(); + z80_reset_pulse(); + z80_setup_addrbus_active(); + zstate = RUNNING_AQRD; + break; + default: + break; + } + break; + + case Restart: + switch (zstate) { + case RUNNING: + case RUNNING_AQRD: + z80_reset_pulse(); + break; + default: + break; + } + break; + + case M_Cycle: + switch (zstate) { + case RUNNING_AQRD: + z80_busreq_hpulse(); + break; + default: + break; + } + } + return zstate; +} + + /*--------------------------------------------------------------------------*/ static @@ -398,13 +506,13 @@ DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, adr); fifo_dsc[f].base = adr; - z80_request_bus(); + z80_bus_cmd(Request); fifo_dsc[f].mask = z80_read(adr + FIFO_BUFSIZE_MASK); fifo_dsc[f].idx_in = z80_read(adr + FIFO_INDEX_IN); fifo_dsc[f].idx_out = z80_read(adr + FIFO_INDEX_OUT); - z80_release_bus(); + z80_bus_cmd(Release); } @@ -417,9 +525,9 @@ int z80_memfifo_is_empty(const fifo_t f) uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN; uint8_t idx; - z80_request_bus(); + z80_bus_cmd(Request); idx = z80_read(adr); - z80_release_bus(); + z80_bus_cmd(Release); rc = idx == fifo_dsc[f].idx_out; } @@ -431,10 +539,10 @@ int z80_memfifo_is_full(const fifo_t f) int rc = 1; if (fifo_dsc[f].base != 0) { - z80_request_bus(); + z80_bus_cmd(Request); rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask) == z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT); - z80_release_bus(); + z80_bus_cmd(Release); } return rc; } @@ -446,12 +554,12 @@ uint8_t z80_memfifo_getc(const fifo_t f) while (z80_memfifo_is_empty(f)) ; - z80_request_bus(); + z80_bus_cmd(Request); idx = fifo_dsc[f].idx_out; rc = z80_read(fifo_dsc[f].base+idx); fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask; z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out); - z80_release_bus(); + z80_bus_cmd(Release); return rc; } @@ -464,12 +572,12 @@ void z80_memfifo_putc(fifo_t f, uint8_t val) while (z80_memfifo_is_full(f)) ; - z80_request_bus(); + z80_bus_cmd(Request); idx = fifo_dsc[f].idx_in; z80_write(fifo_dsc[f].base+idx, val); fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask; z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in); - z80_release_bus(); + z80_bus_cmd(Release); } /*--------------------------------------------------------------------------*/ @@ -535,9 +643,9 @@ void z80_init_msg_fifo(uint32_t addr) DBG_P(1, "z80_init_msg_fifo: %lx\n", addr); - z80_request_bus(); + z80_bus_cmd(Request); z80_write(addr+FIFO_INDEX_OUT, z80_read(addr+FIFO_INDEX_IN)); - z80_release_bus(); + z80_bus_cmd(Release); msg_fifo.base = addr; } @@ -553,9 +661,9 @@ int z80_msg_fifo_getc(void) msg_fifo.count = 0; if (msg_fifo.base != 0) { - z80_request_bus(); + z80_bus_cmd(Request); z80_write(msg_fifo.base+FIFO_INDEX_OUT, msg_fifo.count); - z80_release_bus(); + z80_bus_cmd(Release); } } #endif