X-Git-Url: http://cloudbase.mooo.com/gitweb/z180-stamp.git/blobdiff_plain/72f5882239bb88b8a68f305802e0dde37a975604..8a7deceacd30529e5c32082b2c719eb055841d0d:/avr/z80-if.c diff --git a/avr/z80-if.c b/avr/z80-if.c index 9ee9cb0..9492c28 100644 --- a/avr/z80-if.c +++ b/avr/z80-if.c @@ -54,7 +54,7 @@ */ #include -#include +#include #include #include "debug.h" #include "z80-if.h" @@ -63,12 +63,6 @@ /* Number of array elements */ #define NELEMS(x) (sizeof x/sizeof *x) - -#define CONCAT(x,y) x ## y -#define EVALUATOR(x,y) CONCAT(x,y) - -#define GPIO_(X) CONCAT(GPIO, X) - struct bits { uint8_t b0:1; uint8_t b1:1; @@ -80,10 +74,14 @@ struct bits { uint8_t b7:1; } __attribute__((__packed__)); -#define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin) +typedef struct bits pbit_t; +#define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin) +//#define P_ZCLK PORTB +//#define ZCLK 5 +//#define DDR_ZCLK DDRB #define P_MREQ PORTD #define MREQ 4 #define DDR_MREQ DDRD @@ -127,6 +125,7 @@ struct bits { //#define ADB_PORT PORTE +//#define Z80_O_ZCLK SBIT(P_ZCLK, 5) #define Z80_O_MREQ SBIT(P_MREQ, 4) #define Z80_O_RD SBIT(P_RD, 3) #define Z80_O_WR SBIT(P_WR, 2) @@ -137,55 +136,23 @@ struct bits { //#define Z80_I_HALT SBIT(P_HALT, ) -#if 0 -void z80_busreq(level_t level) -{ - Z80_O_BUSREQ = level; -} -#endif - -void z80_reset(level_t level) -{ - Z80_O_RST = level; - if (level) - Stat |= S_Z180_RUNNING; - else - Stat &= ~S_Z180_RUNNING; -} - - -void z80_reset_pulse(void) -{ - Z80_O_RST = 0; - _delay_us(10); - Z80_O_RST = 1; - Stat |= S_Z180_RUNNING; -} - -#if 0 -int z80_stat_halt(void) -{ - return Z80_I_HALT; -} -#endif - - #define MASK(n) ((1<<(n))-1) #define SMASK(w,s) (MASK(w) << (s)) - typedef union { uint32_t l; uint16_t w[2]; uint8_t b[4]; } addr_t; - + + +static zstate_t zstate; /*--------------------------------------------------------------------------*/ -static void z80_setup_addrbus_tristate(void) +static void z80_addrbus_set_tristate(void) { /* /MREQ, /RD, /WR: Input, no pullup */ DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR)); @@ -201,8 +168,8 @@ static void z80_setup_addrbus_tristate(void) DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT); } - -static void z80_setup_addrbus_active(void) + +static void z80_addrbus_set_active(void) { /* /MREQ, /RD, /WR: Output and high */ Z80_O_MREQ = 1; @@ -216,18 +183,27 @@ static void z80_setup_addrbus_active(void) } - -static void z80_setup_dbus_in(void) +static void z80_dbus_set_in(void) { DDR_DB = 0; P_DB = 0; } -static void z80_setup_dbus_out(void) + +static void z80_dbus_set_out(void) { DDR_DB = 0xff; } + +static void z80_reset_pulse(void) +{ + Z80_O_RST = 0; + _delay_us(10); + Z80_O_RST = 1; +} + + void z80_setup_bus(void) { /* /ZRESET: Output and low */ @@ -246,40 +222,169 @@ void z80_setup_bus(void) DDR_IOCS1 &= ~_BV(IOCS1); P_IOCS1 &= ~_BV(IOCS1); - z80_setup_addrbus_tristate(); - z80_setup_dbus_in(); + z80_addrbus_set_tristate(); + z80_dbus_set_in(); - Stat &= ~S_Z180_RUNNING; + zstate = RESET; } -/*--------------------------------------------------------------------------*/ -void z80_request_bus(void) +zstate_t z80_bus_state(void) { - Z80_O_BUSREQ = 0; + return zstate; +} - if (!(Stat & S_Z180_RUNNING)) - Z80_O_RST = 1; - while(Z80_I_BUSACK == 1); - z80_setup_addrbus_active(); +static void z80_busreq_hpulse(void) +{ + z80_dbus_set_in(); + z80_addrbus_set_tristate(); + + ATOMIC_BLOCK(ATOMIC_FORCEON) { + Z80_O_BUSREQ = 1; + Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */ + Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */ + } + + if (zstate & ZST_ACQUIRED) { + while(Z80_I_BUSACK == 1) + ; + z80_addrbus_set_active(); + } } -void z80_release_bus(void) + +/* + + + | | | | | + + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD | + + | | | | | + + | 0 | 1 | 2 | 3 | +Event + | | | | | +----------------+---------------+---------------+---------------+---------------+ + | | | | | +Reset | 0 | 0 | 0 | 0 | + | | | | | + | | | | | +Request | 1 | | 3 | | + | | | | | + | | | | | +Release | | 0 | | 2 | + | | | | | + | | | | | +Run | 2 | 3 | | | + | | | | | + | | | | | +Restart | | | 2 | 3 | + | | | | | + | | | | | +M_Cycle | | | | 3 | + | | | | | + | | | | | +*/ + +zstate_t z80_bus_cmd(bus_cmd_t cmd) { - z80_setup_dbus_in(); - z80_setup_addrbus_tristate(); + switch (cmd) { - if (!(Stat & S_Z180_RUNNING)) + case Reset: + z80_dbus_set_in(); + z80_addrbus_set_tristate(); Z80_O_RST = 0; - - Z80_O_BUSREQ = 1; - //while(Z80_I_BUSACK == 0); + Z80_O_BUSREQ = 1; + zstate = RESET; + break; + + case Request: + switch (zstate) { + case RESET: + Z80_O_BUSREQ = 0; + Z80_O_RST = 1; + while(Z80_I_BUSACK == 1) + ; + z80_addrbus_set_active(); + zstate = RESET_AQRD; + break; + + case RUNNING: + Z80_O_BUSREQ = 0; + while(Z80_I_BUSACK == 1) + ; + z80_addrbus_set_active(); + zstate = RUNNING_AQRD; + break; + + default: + break; + } + break; + + case Release: + switch (zstate) { + case RESET_AQRD: + z80_dbus_set_in(); + z80_addrbus_set_tristate(); + Z80_O_RST = 0; + Z80_O_BUSREQ = 1; + zstate = RESET; + break; + case RUNNING_AQRD: + z80_dbus_set_in(); + z80_addrbus_set_tristate(); + Z80_O_BUSREQ = 1; + zstate = RUNNING; + break; + default: + break; + } + break; + + case Run: + switch (zstate) { + case RESET: + Z80_O_RST = 1; + zstate = RUNNING; + break; + + case RESET_AQRD: + z80_dbus_set_in(); + z80_addrbus_set_tristate(); + z80_reset_pulse(); + z80_addrbus_set_active(); + zstate = RUNNING_AQRD; + break; + default: + break; + } + break; + + case Restart: + switch (zstate) { + case RUNNING: + case RUNNING_AQRD: + z80_reset_pulse(); + break; + default: + break; + } + break; + + case M_Cycle: + switch (zstate) { + case RUNNING_AQRD: + z80_busreq_hpulse(); + break; + default: + break; + } + } + return zstate; } + /*--------------------------------------------------------------------------*/ -static +static //inline __attribute__ ((always_inline)) void z80_setaddress(uint32_t addr) { @@ -294,7 +399,7 @@ void z80_write(uint32_t addr, uint8_t data) { z80_setaddress(addr); Z80_O_MREQ = 0; - z80_setup_dbus_out(); + z80_dbus_set_out(); P_DB = data; P_DB = data; Z80_O_WR = 0; @@ -309,7 +414,7 @@ uint8_t z80_read(uint32_t addr) z80_setaddress(addr); Z80_O_MREQ = 0; - z80_setup_dbus_in(); + z80_dbus_set_in(); Z80_O_RD = 0; Z80_O_RD = 0; Z80_O_RD = 0; @@ -323,7 +428,7 @@ uint8_t z80_read(uint32_t addr) void z80_memset(uint32_t addr, uint8_t data, uint32_t length) { - z80_setup_dbus_out(); + z80_dbus_set_out(); Z80_O_MREQ = 0; while(length--) { z80_setaddress(addr++); @@ -339,8 +444,8 @@ void z80_memset(uint32_t addr, uint8_t data, uint32_t length) void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length) { uint8_t data; - - z80_setup_dbus_out(); + + z80_dbus_set_out(); Z80_O_MREQ = 0; while(length--) { z80_setaddress(dest++); @@ -360,7 +465,7 @@ void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length) 017B' rx.out_idx: ds 1 ; 017C' rx.buf: ds rx.buf_len ; 018B' rx.buf_end equ $-1 ; last byte (start+len-1) - + 018C' tx.bs_mask: ds 1 ; (buf_len - 1) 018D' tx.in_idx: ds 1 ; 018E' tx.out_idx: ds 1 ; @@ -389,22 +494,22 @@ static struct { idx_in, mask; } fifo_dsc[NUM_FIFOS]; - -void z80_memfifo_init(const fifo_t f, uint32_t adr) -{ -DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, adr); - - fifo_dsc[f].base = adr; +void z80_memfifo_init(const fifo_t f, uint32_t addr) +{ + fifo_dsc[f].base = addr; - z80_request_bus(); + if (addr != 0) { - fifo_dsc[f].mask = z80_read(adr + FIFO_BUFSIZE_MASK); - fifo_dsc[f].idx_in = z80_read(adr + FIFO_INDEX_IN); - fifo_dsc[f].idx_out = z80_read(adr + FIFO_INDEX_OUT); +DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr); - z80_release_bus(); + z80_bus_cmd(Request); + fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK); + fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN); + fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT); + z80_bus_cmd(Release); + } } @@ -417,9 +522,9 @@ int z80_memfifo_is_empty(const fifo_t f) uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN; uint8_t idx; - z80_request_bus(); + z80_bus_cmd(Request); idx = z80_read(adr); - z80_release_bus(); + z80_bus_cmd(Release); rc = idx == fifo_dsc[f].idx_out; } @@ -429,30 +534,49 @@ int z80_memfifo_is_empty(const fifo_t f) int z80_memfifo_is_full(const fifo_t f) { int rc = 1; - + if (fifo_dsc[f].base != 0) { - z80_request_bus(); + z80_bus_cmd(Request); rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask) == z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT); - z80_release_bus(); + z80_bus_cmd(Release); } return rc; } -uint8_t z80_memfifo_getc(const fifo_t f) + +uint8_t z80_memfifo_getc_wait(const fifo_t f) { uint8_t rc, idx; - + while (z80_memfifo_is_empty(f)) ; - z80_request_bus(); + z80_bus_cmd(Request); idx = fifo_dsc[f].idx_out; rc = z80_read(fifo_dsc[f].base+idx); fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask; z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out); - z80_release_bus(); - + z80_bus_cmd(Release); + + return rc; +} + +int z80_memfifo_getc(const fifo_t f) +{ + int rc = -1; + + if (fifo_dsc[f].base != 0) { + uint8_t idx = fifo_dsc[f].idx_out; + z80_bus_cmd(Request); + if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) { + rc = z80_read(fifo_dsc[f].base+idx); + fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask; + z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out); + } + z80_bus_cmd(Release); + } + return rc; } @@ -460,105 +584,14 @@ uint8_t z80_memfifo_getc(const fifo_t f) void z80_memfifo_putc(fifo_t f, uint8_t val) { int idx; - + while (z80_memfifo_is_full(f)) ; - z80_request_bus(); + z80_bus_cmd(Request); idx = fifo_dsc[f].idx_in; z80_write(fifo_dsc[f].base+idx, val); fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask; z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in); - z80_release_bus(); -} - -/*--------------------------------------------------------------------------*/ -/* - TODO: Rewrite msg_fifo routines for AVR -*/ - -static struct { - uint32_t base; - //uint8_t idx_out, idx_in; - uint16_t count; - uint8_t buf[256]; - } msg_fifo; - -/*--------------------------------------------------------------------------*/ - -#if 0 - -static void tim1_setup(void) -{ - RCC_APB2RSTR |= RCC_APB2RSTR_TIM1RST; - RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM1RST; - - TIM1_CR1 = 0; - - TIM1_SMCR = 0 - /* | TIM_SMCR_ETP */ - /* | TIM_SMCR_ETF_CK_INT_N_2 */ - | TIM_SMCR_TS_ETRF - | TIM_SMCR_SMS_OFF - ; - - TIM1_DIER = TIM_DIER_TDE; - - - TIM1_CCMR1 = 0 - | TIM_CCMR1_OC1M_FORCE_LOW - | TIM_CCMR1_CC1S_OUT; - - TIM1_SMCR |= TIM_SMCR_SMS_TM; -} - -#endif - -/*--------------------------------------------------------------------------*/ - -void z80_setup_msg_fifo(void) -{ -// gpio_set_mode(P_BUSACK, GPIO_MODE_INPUT, -// GPIO_CNF_INPUT_FLOAT, GPIO_BUSACK | GPIO_IOCS1); - -//... - -// msg_fifo.count = NELEMS(msg_fifo.buf); - msg_fifo.count = 0; - msg_fifo.base = 0; - -} - - -void z80_init_msg_fifo(uint32_t addr) -{ - -DBG_P(1, "z80_init_msg_fifo: %lx\n", addr); - - z80_request_bus(); - z80_write(addr+FIFO_INDEX_OUT, z80_read(addr+FIFO_INDEX_IN)); - z80_release_bus(); - msg_fifo.base = addr; -} - - -int z80_msg_fifo_getc(void) -{ - int c = -1; - -#if 0 - if (msg_fifo.count != (NELEMS(msg_fifo.buf) /*- DMA1_CNDTR4 */ )) { - c = msg_fifo.buf[msg_fifo.count]; - if (++msg_fifo.count == NELEMS(msg_fifo.buf)) - msg_fifo.count = 0; - - if (msg_fifo.base != 0) { - z80_request_bus(); - z80_write(msg_fifo.base+FIFO_INDEX_OUT, msg_fifo.count); - z80_release_bus(); - } - } -#endif - - return c; + z80_bus_cmd(Release); }