X-Git-Url: http://cloudbase.mooo.com/gitweb/z180-stamp.git/blobdiff_plain/9b6b4b31e8cb284ad6a68fe16d458e36bbfb46fa..refs/tags/hexrel-6.4:/avr/z80-if.c

diff --git a/avr/z80-if.c b/avr/z80-if.c
index 207aed1..21ffeac 100644
--- a/avr/z80-if.c
+++ b/avr/z80-if.c
@@ -1,89 +1,74 @@
+/*
+ * (C) Copyright 2014 Leo C. <erbl259-lmu@yahoo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
 /**
  *
  * Pin assignments
  *
- * | Z180-Sig 	|   AVR-Port	| Dir	|   Special Function	|
+ * | Z180-Sig   |   AVR-Port    | Dir   |   Special Function    |
  * +------------+---------------+-------+-----------------------+
- * |	A0	| PA 	0	|  O	|			|
- * |	A1	| PA 	1	|  O	|			|
- * |	A2	| PA 	2	|  O	|			|
- * |	A3	| PA 	3	|  O	|			|
- * |	A4	| PA 	4	|  O	|			|
- * |	A5	| PA 	5	|  O	|			|
- * |	A6	| PA 	6	|  O	|			|
- * |	A7	| PA 	7	|  O	|			|
- * |	A8	| PC 	0	|  O	|			|
- * |	A9	| PC 	1	|  O	|			|
- * |	A10	| PC 	2	|  O	|			|
- * |	A11	| PC 	3	|  O	|			|
- * |	A12	| PC 	4	|  O	|			|
- * |	A13	| PC 	5	|  O	|			|
- * |	A14	| PC 	6	|  O	|			|
- * |	A15	| PC 	7	|  O	|			|
- * |	A16	| PE 	2	|  O	|			|
- * |	A17	| PE 	3	|  O	|			|
- * |	A18	| PE 	4	|  O	|			|
- * |	D0	| PF 	0	|  I/O	|			|
- * |	D1	| PF 	1	|  I/O	|			|
- * |	D2	| PF 	2	|  I/O	|			|
- * |	D3	| PF 	3	|  I/O	|			|
- * |	D4	| PF 	4	|  I/O	|			|
- * |	D5	| PF 	5	|  I/O	|			|
- * |	D6	| PF 	6	|  I/O	|			|
- * |	D7	| PF 	7	|  I/O	|			|
- * |	RD	| PD 	3	|  O	|			|
- * |	WR	| PD 	2	|  O	|			|
- * |	MREQ	| PD 	4	|  O	|			|
- * |	RST	| PD 	5	|  O	|			|
- * |	BUSREQ	| PD 	7	|  O	|			|
- * |	BUSACK	| PD 	6	|  I	|			|
- * |	IOCS1	| PE 	5	|  I	|			|
- * |*	HALT	| P 		|	|			|
- * |*	NMI	| P 		|	|			|
- * |		| P 		|  	|			|
- * |		| P 		|  	|  af1	 USART1_TX	|
- * |		| P 		|  	|  af1	 USART1_RX	|
- * |		| P 		|JTDI	|  remap SPI1_NSS'	|
- * |		| P 		|JTDO	|  remap SPI1_SCK'	|
- * |		| P 		|JTRST	|  remap SPI1_MISO'	|
- * |		| P 		|	|  remap SPI1_MOSI'	|
- * |		| P 		|	|  af1	 OSC32		|
- * |		| P 		|	|  af1	 OSC32		|
-
+ * |    A0      | PA    0       |  O    |                       |
+ * |    A1      | PA    1       |  O    |                       |
+ * |    A2      | PA    2       |  O    |                       |
+ * |    A3      | PA    3       |  O    |                       |
+ * |    A4      | PA    4       |  O    |                       |
+ * |    A5      | PA    5       |  O    |                       |
+ * |    A6      | PA    6       |  O    |                       |
+ * |    A7      | PA    7       |  O    |                       |
+ * |    A8      | PC    0       |  O    |                       |
+ * |    A9      | PC    1       |  O    |                       |
+ * |    A10     | PC    2       |  O    |                       |
+ * |    A11     | PC    3       |  O    |                       |
+ * |    A12     | PC    4       |  O    |                       |
+ * |    A13     | PC    5       |  O    |                       |
+ * |    A14     | PC    6       |  O    |                       |
+ * |    A15     | PC    7       |  O    |                       |
+ * |    A16     | PE    2       |  O    |                       |
+ * |    A17     | PE    3       |  O    |                       |
+ * |    A18     | PE    4       |  O    |                       |
+ * |    D0      | PF    0       |  I/O  |                       |
+ * |    D1      | PF    1       |  I/O  |                       |
+ * |    D2      | PF    2       |  I/O  |                       |
+ * |    D3      | PF    3       |  I/O  |                       |
+ * |    D4      | PF    4       |  I/O  |                       |
+ * |    D5      | PF    5       |  I/O  |                       |
+ * |    D6      | PF    6       |  I/O  |                       |
+ * |    D7      | PF    7       |  I/O  |                       |
+ * |    RD      | PD    3       |  O    |                       |
+ * |    WR      | PD    2       |  O    |                       |
+ * |    MREQ    | PD    4       |  O    |                       |
+ * |    RST     | PD    5       |  O    |                       |
+ * |    BUSREQ  | PD    7       |  O    |                       |
+ * |    BUSACK  | PD    6       |  I    |                       |
+ * |    IOCS1   | PE    5       |  I    |                       |
+ * |*   HALT    | P             |       |                       |
+ * |*   NMI     | P             |       |                       |
+ * |            | P             |       |                       |
+ * |            | P             |       |  af1   USART1_TX      |
+ * |            | P             |       |  af1   USART1_RX      |
+ * |            | P             |JTDI   |  remap SPI1_NSS'      |
+ * |            | P             |JTDO   |  remap SPI1_SCK'      |
+ * |            | P             |JTRST  |  remap SPI1_MISO'     |
+ * |            | P             |       |  remap SPI1_MOSI'     |
+ * |            | P             |       |  af1   OSC32          |
+ * |            | P             |       |  af1   OSC32          |
 
  */
 
-#include <avr/io.h>
-#include <util/delay.h>
-#include <stdio.h>
+
+#include "common.h"
+#include <util/atomic.h>
 #include "debug.h"
 #include "z80-if.h"
 
 
-/* Number of array elements */
-#define NELEMS(x)  (sizeof x/sizeof *x)
-
-
-#define CONCAT(x,y) x ## y
-#define EVALUATOR(x,y)  CONCAT(x,y)
-
-#define GPIO_(X)	CONCAT(GPIO, X)
-
-struct bits {
-  uint8_t b0:1;
-  uint8_t b1:1;
-  uint8_t b2:1;
-  uint8_t b3:1;
-  uint8_t b4:1;
-  uint8_t b5:1;
-  uint8_t b6:1;
-  uint8_t b7:1;
-} __attribute__((__packed__));
-
-#define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin)
-
-
 
+//#define P_ZCLK		PORTB
+//#define ZCLK		5
+//#define DDR_ZCLK	DDRB
 #define P_MREQ		PORTD
 #define MREQ		4
 #define DDR_MREQ	DDRD
@@ -127,6 +112,7 @@ struct bits {
 //#define ADB_PORT	PORTE
 
 
+//#define Z80_O_ZCLK	SBIT(P_ZCLK, 5)
 #define	Z80_O_MREQ	SBIT(P_MREQ, 4)
 #define Z80_O_RD	SBIT(P_RD, 3)
 #define Z80_O_WR	SBIT(P_WR, 2)
@@ -137,48 +123,40 @@ struct bits {
 //#define Z80_I_HALT	SBIT(P_HALT, )
 
 
-void z80_busreq(level_t level)
-{
-	Z80_O_BUSREQ = level;
-}
-
-void z80_reset(level_t level)
-{
-	Z80_O_RST = level;
-}
-
-
-void z80_reset_pulse(void)
-{
-	Z80_O_RST = 0;
-	_delay_us(10);
-	Z80_O_RST = 1;
-}
-
-#if 0
-int z80_stat_halt(void)
-{
-	return Z80_I_HALT;
-}
-#endif
+#define BUS_TO 20
 
 
 #define MASK(n)	((1<<(n))-1)
 #define SMASK(w,s) (MASK(w) << (s))
 
 
-
 typedef union {
 	uint32_t l;
 	uint16_t w[2];
 	uint8_t b[4];
 } addr_t;
- 
+
+
+static zstate_t zstate;
+static volatile uint8_t timer;		/* used for bus timeout */
+
+/*---------------------------------------------------------*/
+/* 10Hz timer interrupt generated by OC4A                  */
+/*---------------------------------------------------------*/
+
+ISR(TIMER4_COMPA_vect)
+{
+
+	uint8_t i = timer;
+
+	if (i)
+		timer = i - 1;
+}
 
 /*--------------------------------------------------------------------------*/
 
 
-static void z80_setup_addrbus_tristate(void)
+static void z80_addrbus_set_tristate(void)
 {
 	/* /MREQ, /RD, /WR: Input, no pullup */
 	DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR));
@@ -194,8 +172,8 @@ static void z80_setup_addrbus_tristate(void)
 	DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT);
 }
 
-	
-static void z80_setup_addrbus_active(void)
+
+static void z80_addrbus_set_active(void)
 {
 	/* /MREQ, /RD, /WR: Output and high */
 	Z80_O_MREQ = 1;
@@ -209,18 +187,27 @@ static void z80_setup_addrbus_active(void)
 }
 
 
-
-static void z80_setup_dbus_in(void)
+static void z80_dbus_set_in(void)
 {
 	DDR_DB = 0;
 	P_DB = 0;
 }
 
-static void z80_setup_dbus_out(void)
+
+static void z80_dbus_set_out(void)
 {
 	DDR_DB = 0xff;
 }
 
+
+static void z80_reset_pulse(void)
+{
+	Z80_O_RST = 0;
+	_delay_us(10);
+	Z80_O_RST = 1;
+}
+
+
 void z80_setup_bus(void)
 {
 	/* /ZRESET: Output and low */
@@ -239,30 +226,189 @@ void z80_setup_bus(void)
 	DDR_IOCS1 &= ~_BV(IOCS1);
 	P_IOCS1 &= ~_BV(IOCS1);
 
-	z80_setup_addrbus_tristate();
-	z80_setup_dbus_in();
+	z80_addrbus_set_tristate();
+	z80_dbus_set_in();
+
+	zstate = RESET;
+
+	/* Timer 4 */
+	PRR1 &= ~_BV(PRTIM4);
+	OCR4A = F_CPU / 1024 / 10 - 1;		  /* Timer: 10Hz interval (OC4A) */
+	TCCR4B = (0b01<<WGM42)|(0b101<<CS30); /* CTC Mode, Prescaler 1024 */
+	TIMSK4 = _BV(OCIE4A);				  /* Enable oca interrupt */
+
 }
 
-/*--------------------------------------------------------------------------*/
 
-void z80_request_bus(void)
+zstate_t z80_bus_state(void)
 {
-	Z80_O_BUSREQ = 0;
-	while(Z80_I_BUSACK == 1);
-	z80_setup_addrbus_active();
+	return zstate;
 }
 
-void z80_release_bus(void)
+
+static void z80_busreq_hpulse(void)
 {
-	z80_setup_dbus_in();
-	z80_setup_addrbus_tristate();
-	Z80_O_BUSREQ = 1;
-	//while(Z80_I_BUSACK == 0);
+	z80_dbus_set_in();
+	z80_addrbus_set_tristate();
+
+	ATOMIC_BLOCK(ATOMIC_FORCEON) {
+		Z80_O_BUSREQ = 1;
+		Z80_O_BUSREQ = 1;	/* 2 AVR clock cycles */
+		Z80_O_BUSREQ = 0;	/* 2 AVR clock cycles */
+	}
+
+	if (zstate & ZST_ACQUIRED) {
+		timer = BUS_TO;
+		while (Z80_I_BUSACK == 1 && timer)
+			;
+		if (Z80_I_BUSACK == 0)
+			z80_addrbus_set_active();
+	}
+}
+
+
+/*
+
+ +              |               |               |               |               |
+    +   State   |     RESET     |  RESET_AQRD   |    RUNNING    | RUNNING_AQRD  |
+       +        |               |               |               |               |
+          +     |       0       |       1       |       2       |       3       |
+Event        +  |               |               |               |               |
+----------------+---------------+---------------+---------------+---------------+
+                |               |               |               |               |
+Reset           |       0       |       0       |       0       |       0       |
+                |               |               |               |               |
+                |               |               |               |               |
+Request         |       1       |               |       3       |               |
+                |               |               |               |               |
+                |               |               |               |               |
+Release         |               |       0       |               |       2       |
+                |               |               |               |               |
+                |               |               |               |               |
+Run             |       2       |       3       |               |               |
+                |               |               |               |               |
+                |               |               |               |               |
+Restart         |               |               |       2       |       3       |
+                |               |               |               |               |
+                |               |               |               |               |
+M_Cycle         |               |               |               |       3       |
+                |               |               |               |               |
+                |               |               |               |               |
+*/
+
+zstate_t z80_bus_cmd(bus_cmd_t cmd)
+{
+	switch (cmd) {
+
+	case Reset:
+		z80_dbus_set_in();
+		z80_addrbus_set_tristate();
+		Z80_O_RST = 0;
+		Z80_O_BUSREQ = 1;
+		zstate = RESET;
+		break;
+
+	case Request:
+		switch (zstate) {
+		case RESET:
+			Z80_O_BUSREQ = 0;
+			Z80_O_RST = 1;
+			timer = BUS_TO;
+			while (Z80_I_BUSACK == 1 && timer)
+				;
+			if (Z80_I_BUSACK == 0) {
+				z80_addrbus_set_active();
+				zstate = RESET_AQRD;
+			} else {
+				Z80_O_RST = 0;
+				Z80_O_BUSREQ = 1;
+			}
+			break;
+
+		case RUNNING:
+			Z80_O_BUSREQ = 0;
+			timer = BUS_TO;
+			while (Z80_I_BUSACK == 1 && timer)
+				;
+			if (Z80_I_BUSACK == 0) {
+				z80_addrbus_set_active();
+				zstate = RUNNING_AQRD;
+			} else {
+				Z80_O_BUSREQ = 1;
+			}
+			break;
+
+		default:
+			break;
+		}
+		break;
+
+	case Release:
+		switch (zstate) {
+		case RESET_AQRD:
+			z80_dbus_set_in();
+			z80_addrbus_set_tristate();
+			Z80_O_RST = 0;
+			Z80_O_BUSREQ = 1;
+			zstate = RESET;
+			break;
+		case RUNNING_AQRD:
+			z80_dbus_set_in();
+			z80_addrbus_set_tristate();
+			Z80_O_BUSREQ = 1;
+			zstate = RUNNING;
+			break;
+		default:
+			break;
+		}
+		break;
+
+	case Run:
+		switch (zstate) {
+		case RESET:
+			Z80_O_RST = 1;
+			zstate = RUNNING;
+			break;
+
+		case RESET_AQRD:
+			z80_dbus_set_in();
+			z80_addrbus_set_tristate();
+			z80_reset_pulse();
+			z80_addrbus_set_active();
+			zstate = RUNNING_AQRD;
+			break;
+		default:
+			break;
+		}
+		break;
+
+	case Restart:
+		switch (zstate) {
+		case RUNNING:
+		case RUNNING_AQRD:
+			z80_reset_pulse();
+			break;
+		default:
+			break;
+		}
+		break;
+
+	case M_Cycle:
+		switch (zstate) {
+		case RUNNING_AQRD:
+			z80_busreq_hpulse();	/* TODO: */
+			break;
+		default:
+			break;
+		}
+	}
+	return zstate;
 }
 
+
 /*--------------------------------------------------------------------------*/
 
-static 
+static
 //inline __attribute__ ((always_inline))
 void z80_setaddress(uint32_t addr)
 {
@@ -277,7 +423,7 @@ void z80_write(uint32_t addr, uint8_t data)
 {
 	z80_setaddress(addr);
 	Z80_O_MREQ = 0;
-	z80_setup_dbus_out();
+	z80_dbus_set_out();
 	P_DB = data;
 	P_DB = data;
 	Z80_O_WR = 0;
@@ -292,7 +438,7 @@ uint8_t z80_read(uint32_t addr)
 
 	z80_setaddress(addr);
 	Z80_O_MREQ = 0;
-	z80_setup_dbus_in();
+	z80_dbus_set_in();
 	Z80_O_RD = 0;
 	Z80_O_RD = 0;
 	Z80_O_RD = 0;
@@ -306,10 +452,27 @@ uint8_t z80_read(uint32_t addr)
 
 void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
 {
-	z80_setup_dbus_out();
+	z80_dbus_set_out();
 	Z80_O_MREQ = 0;
+	P_DB = data;
 	while(length--) {
 		z80_setaddress(addr++);
+		Z80_O_WR = 0;
+		Z80_O_WR = 0;
+		Z80_O_WR = 1;
+	}
+	Z80_O_MREQ = 1;
+}
+
+void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length)
+{
+	uint8_t data;
+
+	z80_dbus_set_out();
+	Z80_O_MREQ = 0;
+	while(length--) {
+		z80_setaddress(dest++);
+		data = *src++;
 		P_DB = data;
 		P_DB = data;
 		Z80_O_WR = 0;
@@ -319,11 +482,11 @@ void z80_memset(uint32_t addr, uint8_t data, uint32_t length)
 	Z80_O_MREQ = 1;
 }
 
-void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length)
+void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length)
 {
 	uint8_t data;
-	
-	z80_setup_dbus_out();
+
+	z80_dbus_set_out();
 	Z80_O_MREQ = 0;
 	while(length--) {
 		z80_setaddress(dest++);
@@ -337,13 +500,32 @@ void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length)
 	Z80_O_MREQ = 1;
 }
 
+void z80_read_block (uint8_t *dest, uint32_t src, size_t length)
+{
+	uint8_t data;
+
+	Z80_O_MREQ = 0;
+	z80_dbus_set_in();
+	while(length--) {
+		z80_setaddress(src++);
+		Z80_O_RD = 0;
+		Z80_O_RD = 0;
+		Z80_O_RD = 0;
+		data = PIN_DB;
+		Z80_O_RD = 1;
+		*dest++ = data;
+	}
+	Z80_O_MREQ = 1;
+}
+
+
 /*
   0179'                         rx.bs_mask:	ds	1		; (buf_len - 1)
   017A'                         rx.in_idx:	ds	1		;
   017B'                         rx.out_idx:	ds	1		;
   017C'                         rx.buf:		ds	rx.buf_len	;
   018B'                         rx.buf_end	equ	$-1		; last byte (start+len-1)
-                                
+
   018C'                         tx.bs_mask:	ds	1		; (buf_len - 1)
   018D'                         tx.in_idx:	ds	1		;
   018E'                         tx.out_idx:	ds	1		;
@@ -372,22 +554,21 @@ static struct {
 		idx_in,
 		mask;
 	} fifo_dsc[NUM_FIFOS];
-	
 
-void z80_memfifo_init(const fifo_t f, uint32_t adr)
-{
-
-DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, adr);
-
-	fifo_dsc[f].base = adr;
 
-	z80_request_bus();
+void z80_memfifo_init(const fifo_t f, uint32_t addr)
+{
+	fifo_dsc[f].base = addr;
 
-	fifo_dsc[f].mask = z80_read(adr + FIFO_BUFSIZE_MASK);
-	fifo_dsc[f].idx_in = z80_read(adr + FIFO_INDEX_IN);
-	fifo_dsc[f].idx_out = z80_read(adr + FIFO_INDEX_OUT);
+DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr);
 
-	z80_release_bus();
+	if (addr != 0) {
+		z80_bus_cmd(Request);
+		fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK);
+		fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
+		fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
+		z80_bus_cmd(Release);
+	}
 }
 
 
@@ -400,9 +581,9 @@ int z80_memfifo_is_empty(const fifo_t f)
 		uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN;
 		uint8_t idx;
 
-		z80_request_bus();
+		z80_bus_cmd(Request);
 		idx = z80_read(adr);
-		z80_release_bus();
+		z80_bus_cmd(Release);
 		rc = idx == fifo_dsc[f].idx_out;
 	}
 
@@ -411,31 +592,50 @@ int z80_memfifo_is_empty(const fifo_t f)
 
 int z80_memfifo_is_full(const fifo_t f)
 {
-	int rc = 1;
-	
+	int rc = 0;
+
 	if (fifo_dsc[f].base != 0) {
-		z80_request_bus();
+		z80_bus_cmd(Request);
 		rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
 			== z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT);
-		z80_release_bus();
+		z80_bus_cmd(Release);
 	}
 	return rc;
 }
 
-uint8_t z80_memfifo_getc(const fifo_t f)
+
+uint8_t z80_memfifo_getc_wait(const fifo_t f)
 {
 	uint8_t rc, idx;
-	
+
 	while (z80_memfifo_is_empty(f))
 		;
 
-	z80_request_bus();
+	z80_bus_cmd(Request);
 	idx = fifo_dsc[f].idx_out;
 	rc = z80_read(fifo_dsc[f].base+idx);
 	fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
 	z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
-	z80_release_bus();
-	
+	z80_bus_cmd(Release);
+
+	return rc;
+}
+
+int z80_memfifo_getc(const fifo_t f)
+{
+	int rc = -1;
+
+	if (fifo_dsc[f].base != 0) {
+		uint8_t idx = fifo_dsc[f].idx_out;
+		z80_bus_cmd(Request);
+		if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) {
+			rc = z80_read(fifo_dsc[f].base+idx);
+			fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
+			z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out);
+		}
+		z80_bus_cmd(Release);
+	}
+
 	return rc;
 }
 
@@ -443,102 +643,14 @@ uint8_t z80_memfifo_getc(const fifo_t f)
 void z80_memfifo_putc(fifo_t f, uint8_t val)
 {
 	int idx;
-	
+
 	while (z80_memfifo_is_full(f))
 		;
 
-	z80_request_bus();
+	z80_bus_cmd(Request);
 	idx = fifo_dsc[f].idx_in;
 	z80_write(fifo_dsc[f].base+idx, val);
 	fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
 	z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
-	z80_release_bus();
-}
-
-/*--------------------------------------------------------------------------*/
-
-static struct {
-	uint32_t base;
-	//uint8_t  idx_out, idx_in;
-	uint16_t count;
-	uint8_t  buf[256];
-	} msg_fifo;
-
-/*--------------------------------------------------------------------------*/
-
-#if 0
-
-static void tim1_setup(void)
-{
-	RCC_APB2RSTR |= RCC_APB2RSTR_TIM1RST;
-	RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM1RST;
-
-	TIM1_CR1 = 0;
-
-	TIM1_SMCR = 0
-	/*	| TIM_SMCR_ETP			*/
-	/*	| TIM_SMCR_ETF_CK_INT_N_2	*/
-		| TIM_SMCR_TS_ETRF
-		| TIM_SMCR_SMS_OFF
-		;
-
-	TIM1_DIER = TIM_DIER_TDE;
-
-
-	TIM1_CCMR1 = 0
-		| TIM_CCMR1_OC1M_FORCE_LOW
-		| TIM_CCMR1_CC1S_OUT;
-
-	TIM1_SMCR |= TIM_SMCR_SMS_TM;
-}
-
-#endif
-
-/*--------------------------------------------------------------------------*/
-
-void z80_setup_msg_fifo(void)
-{
-//	gpio_set_mode(P_BUSACK, GPIO_MODE_INPUT,
-//		GPIO_CNF_INPUT_FLOAT, GPIO_BUSACK | GPIO_IOCS1);
-
-//...
-
-//	msg_fifo.count = NELEMS(msg_fifo.buf);
-	msg_fifo.count = 0;
-	msg_fifo.base = 0;
-
-}
-
-
-void z80_init_msg_fifo(uint32_t addr)
-{
-
-DBG_P(1, "z80_init_msg_fifo: %lx\n", addr);
-
-	z80_request_bus();
-	z80_write(addr+FIFO_INDEX_OUT, z80_read(addr+FIFO_INDEX_IN));
-	z80_release_bus();
-	msg_fifo.base = addr;
-}
-
-
-int z80_msg_fifo_getc(void)
-{
-	int c = -1;
-	
-#if 0
-	if (msg_fifo.count != (NELEMS(msg_fifo.buf) /*- DMA1_CNDTR4 */ )) {
-		c = msg_fifo.buf[msg_fifo.count];
-		if (++msg_fifo.count == NELEMS(msg_fifo.buf))
-			msg_fifo.count = 0;
-
-		if (msg_fifo.base != 0) {
-			z80_request_bus();
-			z80_write(msg_fifo.base+FIFO_INDEX_OUT, msg_fifo.count);
-			z80_release_bus();
-		}
-	}
-#endif
-
-	return c;
+	z80_bus_cmd(Release);
 }