X-Git-Url: http://cloudbase.mooo.com/gitweb/z180-stamp.git/blobdiff_plain/a1595a8e7fe2148c818aef75d454e9f5e0696f78..b35fcb2f65a9c2dd17faae5b513eecca8032461b:/avr/z80-if.c

diff --git a/avr/z80-if.c b/avr/z80-if.c
index e0e230c..6183849 100644
--- a/avr/z80-if.c
+++ b/avr/z80-if.c
@@ -78,6 +78,7 @@
 #define BUSACK		6
 #define DDR_BUSACK	DDRD
 #define P_RST		PORTD
+#define PIN_RST		PIND
 #define DDR_RST		DDRD
 #define RST		5
 
@@ -106,6 +107,7 @@
 #define Z80_O_BUSREQ	SBIT(P_BUSREQ, 7)
 //#define Z80_O_NMI	SBIT(P_NMI, )
 #define Z80_O_RST	SBIT(P_RST, 5)
+#define Z80_I_RST	SBIT(PIN_RST, 5)
 #define Z80_I_BUSACK	SBIT(PIN_BUSACK, 6)
 //#define Z80_I_HALT	SBIT(P_HALT, )
 
@@ -134,9 +136,15 @@
 #define MASK(n)	((1<<(n))-1)
 #define SMASK(w,s) (MASK(w) << (s))
 
+void z80_bus_request_or_exit(void)
+{
+	if (!(z80_bus_cmd(Request) & ZST_ACQUIRED))
+		cmd_error(CMD_RET_FAILURE, EBUSTO, NULL);
+}
 
 static zstate_t zstate;
 static volatile uint8_t timer;		/* used for bus timeout */
+static bool reset_polarity;
 
 /*---------------------------------------------------------*/
 /* 10Hz timer interrupt generated by OC4A                  */
@@ -197,12 +205,27 @@ static void z80_dbus_set_out(void)
 	DDR_DB = 0xff;
 }
 
+static void z80_reset_active(void)
+{
+	if (reset_polarity)
+		Z80_O_RST = 1;
+	else
+		Z80_O_RST = 0;
+}
+
+static void z80_reset_inactive(void)
+{
+	if (reset_polarity)
+		Z80_O_RST = 0;
+	else
+		Z80_O_RST = 1;
+}
 
 static void z80_reset_pulse(void)
 {
-	Z80_O_RST = 0;
+	z80_reset_active();
 	_delay_us(10);
-	Z80_O_RST = 1;
+	z80_reset_inactive();
 }
 
 
@@ -210,9 +233,9 @@ void z80_setup_bus(void)
 {
 	ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
 
-		/* /ZRESET: Output and low */
+		/* /ZRESET: Input, no pullup */
+		DDR_RST &= ~_BV(RST);
 		Z80_O_RST = 0;
-		DDR_RST |= _BV(RST);
 
 		/* /BUSREQ: Output and high */
 		Z80_O_BUSREQ = 1;
@@ -232,6 +255,10 @@ void z80_setup_bus(void)
 			DDR_SS = (DDR_SS & ~_BV(WAIT)) | _BV(RUN) | _BV(STEP);
 		}
 
+		reset_polarity = Z80_I_RST;
+		z80_reset_active();
+		DDR_RST |= _BV(RST);
+
 		zstate = RESET;
 	}
 
@@ -263,6 +290,7 @@ static void z80_busreq_hpulse(void)
 	}
 #endif
 
+#if 1
 	ATOMIC_BLOCK(ATOMIC_FORCEON) {
 		Z80_O_BUSREQ = 1;
 
@@ -273,7 +301,7 @@ static void z80_busreq_hpulse(void)
 			}
 		} while (1);
 	}
-
+#endif
 
 	if (zstate & ZST_ACQUIRED) {
 		timer = BUS_TO;
@@ -321,7 +349,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
 	case Reset:
 		z80_dbus_set_in();
 		z80_addrbus_set_in();
-		Z80_O_RST = 0;
+		z80_reset_active();
 		Z80_O_BUSREQ = 1;
 		zstate = RESET;
 		break;
@@ -330,7 +358,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
 		switch (zstate) {
 		case RESET:
 			Z80_O_BUSREQ = 0;
-			Z80_O_RST = 1;
+			z80_reset_inactive();
 			timer = BUS_TO;
 			while (Z80_I_BUSACK == 1 && timer)
 				;
@@ -338,7 +366,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
 				z80_addrbus_set_out();
 				zstate = RESET_AQRD;
 			} else {
-				Z80_O_RST = 0;
+				z80_reset_active();
 				Z80_O_BUSREQ = 1;
 			}
 			break;
@@ -366,7 +394,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
 		case RESET_AQRD:
 			z80_dbus_set_in();
 			z80_addrbus_set_in();
-			Z80_O_RST = 0;
+			z80_reset_active();
 			Z80_O_BUSREQ = 1;
 			zstate = RESET;
 			break;
@@ -384,7 +412,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
 	case Run:
 		switch (zstate) {
 		case RESET:
-			Z80_O_RST = 1;
+			z80_reset_inactive();
 			zstate = RUNNING;
 			break;
 
@@ -576,7 +604,6 @@ void z80_memfifo_init(const fifo_t f, uint32_t addr)
 {
 	fifo_dsc[f].base = addr;
 
-DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr);
 
 	if (addr != 0) {
 		z80_bus_cmd(Request);
@@ -584,6 +611,11 @@ DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr);
 		fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN);
 		fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT);
 		z80_bus_cmd(Release);
+
+		if (fifo_dsc[f].idx_in != 0 || fifo_dsc[f].idx_out != 0) {
+			DBG_P(1, "## z80_memfifo_init: %i, %lx, in: %.2x, out: %.2x, mask: %.2x\n",
+					f, addr, fifo_dsc[f].idx_in, fifo_dsc[f].idx_out, fifo_dsc[f].mask);
+		}
 	}
 }