X-Git-Url: http://cloudbase.mooo.com/gitweb/z180-stamp.git/blobdiff_plain/eded7ec457ef999586c66b15ada5948bddcc735c..4b0604a43b1bd832797ec17fd8f849fc08ff3393:/avr/z80-if.c diff --git a/avr/z80-if.c b/avr/z80-if.c index 955a61a..ae3bd66 100644 --- a/avr/z80-if.c +++ b/avr/z80-if.c @@ -1,89 +1,68 @@ +/* + * (C) Copyright 2014 Leo C. + * + * SPDX-License-Identifier: GPL-2.0 + */ + /** * * Pin assignments * - * | Z180-Sig | AVR-Port | Dir | Special Function | - * +------------+---------------+-------+-----------------------+ - * | A0 | PA 0 | O | | - * | A1 | PA 1 | O | | - * | A2 | PA 2 | O | | - * | A3 | PA 3 | O | | - * | A4 | PA 4 | O | | - * | A5 | PA 5 | O | | - * | A6 | PA 6 | O | | - * | A7 | PA 7 | O | | - * | A8 | PC 0 | O | | - * | A9 | PC 1 | O | | - * | A10 | PC 2 | O | | - * | A11 | PC 3 | O | | - * | A12 | PC 4 | O | | - * | A13 | PC 5 | O | | - * | A14 | PC 6 | O | | - * | A15 | PC 7 | O | | - * | A16 | PE 2 | O | | - * | A17 | PE 3 | O | | - * | A18 | PE 4 | O | | - * | D0 | PF 0 | I/O | | - * | D1 | PF 1 | I/O | | - * | D2 | PF 2 | I/O | | - * | D3 | PF 3 | I/O | | - * | D4 | PF 4 | I/O | | - * | D5 | PF 5 | I/O | | - * | D6 | PF 6 | I/O | | - * | D7 | PF 7 | I/O | | - * | RD | PD 3 | O | | - * | WR | PD 2 | O | | - * | MREQ | PD 4 | O | | - * | RST | PD 5 | O | | - * | BUSREQ | PD 7 | O | | - * | BUSACK | PD 6 | I | | - * | IOCS1 | PE 5 | I | | - * |* HALT | P | | | - * |* NMI | P | | | - * | | P | | | - * | | P | | af1 USART1_TX | - * | | P | | af1 USART1_RX | - * | | P |JTDI | remap SPI1_NSS' | - * | | P |JTDO | remap SPI1_SCK' | - * | | P |JTRST | remap SPI1_MISO' | - * | | P | | remap SPI1_MOSI' | - * | | P | | af1 OSC32 | - * | | P | | af1 OSC32 | - + * | Z180-Sig | AVR-Port | Dir | + * +------------+---------------+-------+ + * | A0 | PA 0 | O | + * | A1 | PA 1 | O | + * | A2 | PA 2 | O | + * | A3 | PA 3 | O | + * | A4 | PA 4 | O | + * | A5 | PA 5 | O | + * | A6 | PA 6 | O | + * | A7 | PA 7 | O | + * | A8 | PC 0 | O | + * | A9 | PC 1 | O | + * | A10 | PC 2 | O | + * | A11 | PC 3 | O | + * | A12 | PC 4 | O | + * | A13 | PC 5 | O | + * | A14 | PC 6 | O | + * | A15 | PC 7 | O | + * | A16 | PE 2 | O | + * | A17 | PE 3 | O | + * | A18 | PE 4 | O | + * | D0 | PF 0 | I/O | + * | D1 | PF 1 | I/O | + * | D2 | PF 2 | I/O | + * | D3 | PF 3 | I/O | + * | D4 | PF 4 | I/O | + * | D5 | PF 5 | I/O | + * | D6 | PF 6 | I/O | + * | D7 | PF 7 | I/O | + * | RD | PD 3 | O | + * | WR | PD 2 | O | + * | MREQ | PD 4 | O | + * | RST | PD 5 | O | + * | BUSREQ | PD 7 | O | + * | BUSACK | PD 6 | I | + * | + * | Optional + * +------------------------------------+ + * | STEP | PG 0 | O | + * | RUN | PG 1 | O | + * | WAIT | PG 2 | I | */ -#include -#include -#include -#include "debug.h" -#include "z80-if.h" - - -/* Number of array elements */ -#define NELEMS(x) (sizeof x/sizeof *x) - - -#define CONCAT(x,y) x ## y -#define EVALUATOR(x,y) CONCAT(x,y) - -#define GPIO_(X) CONCAT(GPIO, X) - -struct bits { - uint8_t b0:1; - uint8_t b1:1; - uint8_t b2:1; - uint8_t b3:1; - uint8_t b4:1; - uint8_t b5:1; - uint8_t b6:1; - uint8_t b7:1; -} __attribute__((__packed__)); - -#define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin) +#include "z80-if.h" +#include +#include "debug.h" +#include "config.h" +#include "env.h" +//#define P_ZCLK PORTB +//#define ZCLK 5 +//#define DDR_ZCLK DDRB #define P_MREQ PORTD #define MREQ 4 #define DDR_MREQ DDRD @@ -95,15 +74,9 @@ struct bits { #define BUSREQ 7 #define DDR_BUSREQ DDRD #define P_BUSACK PORTD +#define PIN_BUSACK PIND #define BUSACK 6 #define DDR_BUSACK DDRD -//#define P_HALT PORTA -//#define HALT 12 -#define P_IOCS1 PORTE -#define IOCS1 5 -#define DDR_IOCS1 DDRE -//#define P_NMI PORTB -//#define NMI 7 #define P_RST PORTD #define DDR_RST DDRD #define RST 5 @@ -117,8 +90,8 @@ struct bits { #define P_ADH PORTC #define P_ADB PORTE #define PIN_ADB PINE -#define DDR_ADL DDRE -#define DDR_ADH DDRE +#define DDR_ADL DDRA +#define DDR_ADH DDRC #define DDR_ADB DDRE #define ADB_WIDTH 3 @@ -126,187 +99,351 @@ struct bits { //#define ADB_PORT PORTE - -#define ADp1_OFS 0 -#define ADp1_WIDTH 8 -#define ADp1_SHIFT 1 -#define ADp1_PORT GPIOA - -#define ADp2_OFS ADp1_WIDTH -#define ADp2_WIDTH 8 -#define ADp2_SHIFT 0 -#define ADp2_PORT GPIOC - -#define ADp3_OFS (ADp2_OFS+ADp2_WIDTH) -#define ADp3_WIDTH 3 -#define ADp3_SHIFT 10 -#define ADp3_PORT GPIOC - -#define ADunbuff1_WIDTH 1 -#define ADunbuff1_SHIFT 8 -#define ADunbuff1_PORT GPIOA - -#define ADunbuff2_WIDTH 2 -#define ADunbuff2_SHIFT 6 -#define ADunbuff2_PORT GPIOC - -#define ADunbuff3_WIDTH 3 -#define ADunbuff3_SHIFT 10 -#define ADunbuff3_PORT GPIOC - -#define DB_OFS 0 -#define DB_WIDTH 8 -#define DB_SHIFT 8 -#define DB_PORT GPIOB - - +//#define Z80_O_ZCLK SBIT(P_ZCLK, 5) #define Z80_O_MREQ SBIT(P_MREQ, 4) #define Z80_O_RD SBIT(P_RD, 3) #define Z80_O_WR SBIT(P_WR, 2) #define Z80_O_BUSREQ SBIT(P_BUSREQ, 7) //#define Z80_O_NMI SBIT(P_NMI, ) #define Z80_O_RST SBIT(P_RST, 5) -#define Z80_I_BUSACK SBIT(P_BUSACK, 6) +#define Z80_I_BUSACK SBIT(PIN_BUSACK, 6) //#define Z80_I_HALT SBIT(P_HALT, ) -void z80_busreq(level_t level) -{ - Z80_O_BUSREQ = level; -} - -void z80_reset(level_t level) -{ - Z80_O_RST = level; -} +/* Optional */ +#define P_RUN PORTG +#define RUN 1 +#define DDR_RUN DDRG +#define P_STEP PORTG +#define STEP 0 +#define DDR_STEP DDRG +#define P_WAIT PORTG +#define WAIT 2 +#define DDR_WAIT DDRG +/* All three signals are on the same Port (PortG) */ +#define PORT_SS PORTG +#define DDR_SS DDRG +#define PIN_SS PING +#define Z80_O_RUN SBIT(PORT_SS, RUN) +#define Z80_O_STEP SBIT(PORT_SS, STEP) +#define Z80_I_WAIT SBIT(PORT_SS, WAIT) -void z80_reset_pulse(void) -{ - Z80_O_RST = 0; - _delay_us(10); - Z80_O_RST = 1; -} - -#if 0 -int z80_stat_halt(void) -{ - return Z80_I_HALT; -} -#endif +#define BUS_TO 20 #define MASK(n) ((1<<(n))-1) #define SMASK(w,s) (MASK(w) << (s)) +static zstate_t zstate; +static volatile uint8_t timer; /* used for bus timeout */ -typedef union { - uint32_t l; - uint16_t w[2]; - uint8_t b[4]; -} addr_t; - +/*---------------------------------------------------------*/ +/* 10Hz timer interrupt generated by OC4A */ +/*---------------------------------------------------------*/ -/*--------------------------------------------------------------------------*/ +ISR(TIMER5_COMPA_vect) +{ + uint8_t i = timer; + if (i) + timer = i - 1; +} -/* - * A0..A6, A8..A13 are buffered. No need to disable. - * A7, A14..A18: set to input. - */ - -static void z80_setup_adrbus_tristate(void) +/*--------------------------------------------------------------------------*/ + + +static void z80_addrbus_set_in(void) { + /* /MREQ, /RD, /WR: Input, no pullup */ + DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR)); + Z80_O_MREQ = 0; + Z80_O_RD = 0; + Z80_O_WR = 0; + P_ADL = 0; DDR_ADL = 0; P_ADH = 0; DDR_ADH = 0; - PIN_ADB = P_ADB & MASK(ADB_WIDTH) << ADB_SHIFT; + PIN_ADB = P_ADB & (MASK(ADB_WIDTH) << ADB_SHIFT); DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT); } - -static void z80_setup_adrbus_active(void) + +static void z80_addrbus_set_out(void) { + /* /MREQ, /RD, /WR: Output and high */ + Z80_O_MREQ = 1; + Z80_O_RD = 1; + Z80_O_WR = 1; + DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR); + DDR_ADL = 0xff; DDR_ADH = 0xff; DDR_ADB = DDR_ADB | (MASK(ADB_WIDTH) << ADB_SHIFT); } - -static void z80_setup_dbus_in(void) +static void z80_dbus_set_in(void) { DDR_DB = 0; P_DB = 0; } -static void z80_setup_dbus_out(void) + +static void z80_dbus_set_out(void) { DDR_DB = 0xff; } -static -void z80_setaddress(uint32_t addr) -{ - addr_t x; x.l = addr; - P_ADL = x.b[0]; - P_ADH = x.b[1]; - PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ; +static void z80_reset_pulse(void) +{ + Z80_O_RST = 0; + _delay_us(10); + Z80_O_RST = 1; } + void z80_setup_bus(void) { - Z80_O_RST = 0; - DDR_RST |= _BV(RST); + ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { - Z80_O_BUSREQ = 1; - DDR_BUSREQ |= _BV(BUSREQ); + /* /ZRESET: Output and low */ + Z80_O_RST = 0; + DDR_RST |= _BV(RST); -// Z80_O_NMI = 1; -// DDR_NMI |= _BV(NMI); + /* /BUSREQ: Output and high */ + Z80_O_BUSREQ = 1; + DDR_BUSREQ |= _BV(BUSREQ); - Z80_O_MREQ = 1; - Z80_O_RD = 1; - Z80_O_WR = 1; - DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR); + /* /BUSACK: Input, no pullup */ + DDR_BUSACK &= ~_BV(BUSACK); + P_BUSACK &= ~_BV(BUSACK); - DDR_BUSACK &= ~_BV(BUSACK); - P_BUSACK &= ~_BV(BUSACK); + z80_addrbus_set_in(); + z80_dbus_set_in(); - DDR_IOCS1 &= ~_BV(IOCS1); - P_IOCS1 &= ~_BV(IOCS1); + if (getenv_yesno(PSTR(ENV_SINGLESTEP))) { + /* /RUN & /STEP: output, /WAIT: input */ - //Z80_O_BUSREQ = 0; - //while(Z80_I_BUSACK == 1); + PORT_SS = (PORT_SS & ~_BV(RUN)) | _BV(STEP); + DDR_SS = (DDR_SS & ~_BV(WAIT)) | _BV(RUN) | _BV(STEP); + } + + zstate = RESET; + } + + /* Timer 5 */ + PRR1 &= ~_BV(PRTIM5); + OCR5A = F_CPU / 1024 / 10 - 1; /* Timer: 10Hz interval (OC4A) */ + TCCR5B = (0b01<> 8; + PIN_ADB = (((addr >> 16) << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT; } void z80_write(uint32_t addr, uint8_t data) { z80_setaddress(addr); Z80_O_MREQ = 0; + z80_dbus_set_out(); P_DB = data; - z80_setup_dbus_out(); + P_DB = data; + Z80_O_WR = 0; Z80_O_WR = 0; Z80_O_WR = 1; Z80_O_MREQ = 1; @@ -318,7 +455,8 @@ uint8_t z80_read(uint32_t addr) z80_setaddress(addr); Z80_O_MREQ = 0; - z80_setup_dbus_in(); + z80_dbus_set_in(); + Z80_O_RD = 0; Z80_O_RD = 0; Z80_O_RD = 0; data = PIN_DB; @@ -331,40 +469,80 @@ uint8_t z80_read(uint32_t addr) void z80_memset(uint32_t addr, uint8_t data, uint32_t length) { - z80_setup_dbus_out(); + z80_dbus_set_out(); Z80_O_MREQ = 0; + P_DB = data; while(length--) { z80_setaddress(addr++); + Z80_O_WR = 0; + Z80_O_WR = 0; + Z80_O_WR = 1; + } + Z80_O_MREQ = 1; +} + +void z80_write_block_P(const FLASH uint8_t *src, uint32_t dest, uint32_t length) +{ + uint8_t data; + + z80_dbus_set_out(); + Z80_O_MREQ = 0; + while(length--) { + z80_setaddress(dest++); + data = *src++; + P_DB = data; P_DB = data; Z80_O_WR = 0; + Z80_O_WR = 0; Z80_O_WR = 1; } Z80_O_MREQ = 1; } -void z80_write_block(uint8_t *src, uint32_t dest, uint32_t length) +void z80_write_block(const uint8_t *src, uint32_t dest, uint32_t length) { uint8_t data; - - z80_setup_dbus_out(); + + z80_dbus_set_out(); Z80_O_MREQ = 0; while(length--) { z80_setaddress(dest++); data = *src++; P_DB = data; + P_DB = data; + Z80_O_WR = 0; Z80_O_WR = 0; Z80_O_WR = 1; } Z80_O_MREQ = 1; } +void z80_read_block (uint8_t *dest, uint32_t src, size_t length) +{ + uint8_t data; + + Z80_O_MREQ = 0; + z80_dbus_set_in(); + while(length--) { + z80_setaddress(src++); + Z80_O_RD = 0; + Z80_O_RD = 0; + Z80_O_RD = 0; + data = PIN_DB; + Z80_O_RD = 1; + *dest++ = data; + } + Z80_O_MREQ = 1; +} + + /* 0179' rx.bs_mask: ds 1 ; (buf_len - 1) 017A' rx.in_idx: ds 1 ; 017B' rx.out_idx: ds 1 ; 017C' rx.buf: ds rx.buf_len ; 018B' rx.buf_end equ $-1 ; last byte (start+len-1) - + 018C' tx.bs_mask: ds 1 ; (buf_len - 1) 018D' tx.in_idx: ds 1 ; 018E' tx.out_idx: ds 1 ; @@ -393,22 +571,21 @@ static struct { idx_in, mask; } fifo_dsc[NUM_FIFOS]; - - -void z80_memfifo_init(const fifo_t f, uint32_t adr) -{ -DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, adr); - fifo_dsc[f].base = adr; - - z80_request_bus(); +void z80_memfifo_init(const fifo_t f, uint32_t addr) +{ + fifo_dsc[f].base = addr; - fifo_dsc[f].mask = z80_read(adr + FIFO_BUFSIZE_MASK); - fifo_dsc[f].idx_in = z80_read(adr + FIFO_INDEX_IN); - fifo_dsc[f].idx_out = z80_read(adr + FIFO_INDEX_OUT); +DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, addr); - z80_release_bus(); + if (addr != 0) { + z80_bus_cmd(Request); + fifo_dsc[f].mask = z80_read(addr + FIFO_BUFSIZE_MASK); + fifo_dsc[f].idx_in = z80_read(addr + FIFO_INDEX_IN); + fifo_dsc[f].idx_out = z80_read(addr + FIFO_INDEX_OUT); + z80_bus_cmd(Release); + } } @@ -421,9 +598,9 @@ int z80_memfifo_is_empty(const fifo_t f) uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN; uint8_t idx; - z80_request_bus(); + z80_bus_cmd(Request); idx = z80_read(adr); - z80_release_bus(); + z80_bus_cmd(Release); rc = idx == fifo_dsc[f].idx_out; } @@ -432,31 +609,50 @@ int z80_memfifo_is_empty(const fifo_t f) int z80_memfifo_is_full(const fifo_t f) { - int rc = 1; - + int rc = 0; + if (fifo_dsc[f].base != 0) { - z80_request_bus(); + z80_bus_cmd(Request); rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask) == z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT); - z80_release_bus(); + z80_bus_cmd(Release); } return rc; } -uint8_t z80_memfifo_getc(const fifo_t f) + +uint8_t z80_memfifo_getc_wait(const fifo_t f) { uint8_t rc, idx; - + while (z80_memfifo_is_empty(f)) ; - z80_request_bus(); + z80_bus_cmd(Request); idx = fifo_dsc[f].idx_out; rc = z80_read(fifo_dsc[f].base+idx); fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask; z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out); - z80_release_bus(); - + z80_bus_cmd(Release); + + return rc; +} + +int z80_memfifo_getc(const fifo_t f) +{ + int rc = -1; + + if (fifo_dsc[f].base != 0) { + uint8_t idx = fifo_dsc[f].idx_out; + z80_bus_cmd(Request); + if (idx != z80_read(fifo_dsc[f].base + FIFO_INDEX_IN)) { + rc = z80_read(fifo_dsc[f].base+idx); + fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask; + z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out); + } + z80_bus_cmd(Release); + } + return rc; } @@ -464,100 +660,14 @@ uint8_t z80_memfifo_getc(const fifo_t f) void z80_memfifo_putc(fifo_t f, uint8_t val) { int idx; - + while (z80_memfifo_is_full(f)) ; - z80_request_bus(); + z80_bus_cmd(Request); idx = fifo_dsc[f].idx_in; z80_write(fifo_dsc[f].base+idx, val); fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask; z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in); - z80_release_bus(); -} - -/*--------------------------------------------------------------------------*/ - -static struct { - uint32_t base; - //uint8_t idx_out, idx_in; - uint16_t count; - uint8_t buf[256]; - } msg_fifo; - -/*--------------------------------------------------------------------------*/ - -#if 0 - -static void tim1_setup(void) -{ - RCC_APB2RSTR |= RCC_APB2RSTR_TIM1RST; - RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM1RST; - - TIM1_CR1 = 0; - - TIM1_SMCR = 0 - /* | TIM_SMCR_ETP */ - /* | TIM_SMCR_ETF_CK_INT_N_2 */ - | TIM_SMCR_TS_ETRF - | TIM_SMCR_SMS_OFF - ; - - TIM1_DIER = TIM_DIER_TDE; - - - TIM1_CCMR1 = 0 - | TIM_CCMR1_OC1M_FORCE_LOW - | TIM_CCMR1_CC1S_OUT; - - TIM1_SMCR |= TIM_SMCR_SMS_TM; -} - -#endif - -/*--------------------------------------------------------------------------*/ - -void z80_setup_msg_fifo(void) -{ -// gpio_set_mode(P_BUSACK, GPIO_MODE_INPUT, -// GPIO_CNF_INPUT_FLOAT, GPIO_BUSACK | GPIO_IOCS1); - -//... - -// msg_fifo.count = NELEMS(msg_fifo.buf); - msg_fifo.count = 0; - msg_fifo.base = 0; - -} - - -void z80_init_msg_fifo(uint32_t addr) -{ - -DBG_P(1, "z80_init_msg_fifo: %lx\n", addr); - - z80_request_bus(); - z80_write(addr+FIFO_INDEX_OUT, z80_read(addr+FIFO_INDEX_IN)); - z80_release_bus(); - msg_fifo.base = addr; -} - - -int z80_msg_fifo_getc(void) -{ - int c = -1; - - if (msg_fifo.count != (NELEMS(msg_fifo.buf) /*- DMA1_CNDTR4 */ )) { - c = msg_fifo.buf[msg_fifo.count]; - if (++msg_fifo.count == NELEMS(msg_fifo.buf)) - msg_fifo.count = 0; - - if (msg_fifo.base != 0) { - z80_request_bus(); - z80_write(msg_fifo.base+FIFO_INDEX_OUT, msg_fifo.count); - z80_release_bus(); - } - } - - return c; + z80_bus_cmd(Release); }