X-Git-Url: http://cloudbase.mooo.com/gitweb/z180-stamp.git/blobdiff_plain/eded7ec457ef999586c66b15ada5948bddcc735c..refs/tags/hexrel-2:/avr/z80-if.c diff --git a/avr/z80-if.c b/avr/z80-if.c index 955a61a..c0f128e 100644 --- a/avr/z80-if.c +++ b/avr/z80-if.c @@ -2,7 +2,7 @@ * * Pin assignments * - * | Z180-Sig | AVR-Port | Dir | Special Function | + * | Z180-Sig | AVR-Port | Dir | Special Function | * +------------+---------------+-------+-----------------------+ * | A0 | PA 0 | O | | * | A1 | PA 1 | O | | @@ -55,6 +55,7 @@ #include #include +#include #include #include "debug.h" #include "z80-if.h" @@ -83,7 +84,9 @@ struct bits { #define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin) - +#define P_ZCLK PORTB +#define ZCLK 7 +#define DDR_ZCLK DDRB #define P_MREQ PORTD #define MREQ 4 #define DDR_MREQ DDRD @@ -95,6 +98,7 @@ struct bits { #define BUSREQ 7 #define DDR_BUSREQ DDRD #define P_BUSACK PORTD +#define PIN_BUSACK PIND #define BUSACK 6 #define DDR_BUSACK DDRD //#define P_HALT PORTA @@ -117,8 +121,8 @@ struct bits { #define P_ADH PORTC #define P_ADB PORTE #define PIN_ADB PINE -#define DDR_ADL DDRE -#define DDR_ADH DDRE +#define DDR_ADL DDRA +#define DDR_ADH DDRC #define DDR_ADB DDRE #define ADB_WIDTH 3 @@ -126,187 +130,366 @@ struct bits { //#define ADB_PORT PORTE +#define Z80_O_ZCLK SBIT(P_ZCLK, 7) +#define Z80_O_MREQ SBIT(P_MREQ, 4) +#define Z80_O_RD SBIT(P_RD, 3) +#define Z80_O_WR SBIT(P_WR, 2) +#define Z80_O_BUSREQ SBIT(P_BUSREQ, 7) +//#define Z80_O_NMI SBIT(P_NMI, ) +#define Z80_O_RST SBIT(P_RST, 5) +#define Z80_I_BUSACK SBIT(PIN_BUSACK, 6) +//#define Z80_I_HALT SBIT(P_HALT, ) -#define ADp1_OFS 0 -#define ADp1_WIDTH 8 -#define ADp1_SHIFT 1 -#define ADp1_PORT GPIOA - -#define ADp2_OFS ADp1_WIDTH -#define ADp2_WIDTH 8 -#define ADp2_SHIFT 0 -#define ADp2_PORT GPIOC -#define ADp3_OFS (ADp2_OFS+ADp2_WIDTH) -#define ADp3_WIDTH 3 -#define ADp3_SHIFT 10 -#define ADp3_PORT GPIOC +#define MASK(n) ((1<<(n))-1) +#define SMASK(w,s) (MASK(w) << (s)) -#define ADunbuff1_WIDTH 1 -#define ADunbuff1_SHIFT 8 -#define ADunbuff1_PORT GPIOA -#define ADunbuff2_WIDTH 2 -#define ADunbuff2_SHIFT 6 -#define ADunbuff2_PORT GPIOC -#define ADunbuff3_WIDTH 3 -#define ADunbuff3_SHIFT 10 -#define ADunbuff3_PORT GPIOC +typedef union { + uint32_t l; + uint16_t w[2]; + uint8_t b[4]; +} addr_t; -#define DB_OFS 0 -#define DB_WIDTH 8 -#define DB_SHIFT 8 -#define DB_PORT GPIOB +static zstate_t zstate; -#define Z80_O_MREQ SBIT(P_MREQ, 4) -#define Z80_O_RD SBIT(P_RD, 3) -#define Z80_O_WR SBIT(P_WR, 2) -#define Z80_O_BUSREQ SBIT(P_BUSREQ, 7) -//#define Z80_O_NMI SBIT(P_NMI, ) -#define Z80_O_RST SBIT(P_RST, 5) -#define Z80_I_BUSACK SBIT(P_BUSACK, 6) -//#define Z80_I_HALT SBIT(P_HALT, ) +/*--------------------------------------------------------------------------*/ -void z80_busreq(level_t level) +static +void z80_setup_clock(void) { - Z80_O_BUSREQ = level; -} + /* ZCLK: Output and low */ + DDR_ZCLK |= _BV(ZCLK); + Z80_O_ZCLK = 0; -void z80_reset(level_t level) -{ - Z80_O_RST = level; -} + DDRB |= _BV(6); /* Debug */ + PORTB |= _BV(6); /* Debug */ + PRR0 &= ~_BV(PRTIM1); -void z80_reset_pulse(void) -{ - Z80_O_RST = 0; - _delay_us(10); - Z80_O_RST = 1; + /* Timer1: CTC: Toggle OC1C on compare match */ + OCR1A = 0; + OCR1C = 0; + TCCR1A = (0b01 << COM1C0) | (0b00 << WGM10); + TCCR1B = (0b01 << WGM12) | (0b001 << CS10); } -#if 0 -int z80_stat_halt(void) + +int z80_clock_set(unsigned long freq) { - return Z80_I_HALT; -} -#endif + unsigned long ocrval = F_CPU / freq / 2; + uint8_t prescale = 0; + + while (ocrval > (1L<<16)) { + prescale++; + if (prescale < 3) + ocrval = ocrval / 8; + else + ocrval = ocrval / 4; + } + if ((ocrval == 0) || (prescale > 4)) + return -1; -#define MASK(n) ((1<<(n))-1) -#define SMASK(w,s) (MASK(w) << (s)) + ocrval -= 1; + PINB |= _BV(6); /* Debug */ + /* Stop Timer */ + TCCR1B = (0b01 << WGM12) | (0b000 << CS10); + TCNT1 = 0; -typedef union { - uint32_t l; - uint16_t w[2]; - uint8_t b[4]; -} addr_t; - + OCR1A = ocrval; + OCR1CL = ocrval; + TCCR1A = (0b01 << COM1C0) | (0b00 << WGM10); + TCCR1B = (0b01 << WGM12) | ((prescale+1) << CS10); -/*--------------------------------------------------------------------------*/ + if (ocrval == 0) { +// TCCR1C |= _BV(FOC1C); + ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { + TCNT1 = 0xFFFF; + } + } + PINB |= _BV(6); /* Debug */ + return 0; +} -/* - * A0..A6, A8..A13 are buffered. No need to disable. - * A7, A14..A18: set to input. - */ - -static void z80_setup_adrbus_tristate(void) +uint32_t z80_clock_get(void) { + uint32_t count = (OCR1A + 1L) * 2; + uint8_t pre = (TCCR1B & 7) - 1; + + while (pre) { + if (pre > 2) + count *= 4; + else + count *= 8; + pre--; + + } + + return F_CPU/count; +} + + + +static void z80_addrbus_set_tristate(void) +{ + /* /MREQ, /RD, /WR: Input, no pullup */ + DDR_MREQ &= ~(_BV(MREQ) | _BV(RD) | _BV(WR)); + Z80_O_MREQ = 0; + Z80_O_RD = 0; + Z80_O_WR = 0; + P_ADL = 0; DDR_ADL = 0; P_ADH = 0; DDR_ADH = 0; - PIN_ADB = P_ADB & MASK(ADB_WIDTH) << ADB_SHIFT; + PIN_ADB = P_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT); DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT); } - -static void z80_setup_adrbus_active(void) + +static void z80_addrbus_set_active(void) { + /* /MREQ, /RD, /WR: Output and high */ + Z80_O_MREQ = 1; + Z80_O_RD = 1; + Z80_O_WR = 1; + DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR); + DDR_ADL = 0xff; DDR_ADH = 0xff; DDR_ADB = DDR_ADB | (MASK(ADB_WIDTH) << ADB_SHIFT); } - -static void z80_setup_dbus_in(void) +static void z80_dbus_set_in(void) { DDR_DB = 0; P_DB = 0; } -static void z80_setup_dbus_out(void) + +static void z80_dbus_set_out(void) { DDR_DB = 0xff; } -static -void z80_setaddress(uint32_t addr) -{ - addr_t x; x.l = addr; - P_ADL = x.b[0]; - P_ADH = x.b[1]; - PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ; +static void z80_reset_pulse(void) +{ + Z80_O_RST = 0; + _delay_us(10); + Z80_O_RST = 1; } + void z80_setup_bus(void) { + z80_setup_clock(); + + /* /ZRESET: Output and low */ Z80_O_RST = 0; DDR_RST |= _BV(RST); + /* /BUSREQ: Output and high */ Z80_O_BUSREQ = 1; DDR_BUSREQ |= _BV(BUSREQ); -// Z80_O_NMI = 1; -// DDR_NMI |= _BV(NMI); - - Z80_O_MREQ = 1; - Z80_O_RD = 1; - Z80_O_WR = 1; - DDR_MREQ |= _BV(MREQ) | _BV(RD) | _BV(WR); - + /* /BUSACK: Input, no pullup */ DDR_BUSACK &= ~_BV(BUSACK); P_BUSACK &= ~_BV(BUSACK); + /* /IOCS1: Input, no pullup */ DDR_IOCS1 &= ~_BV(IOCS1); P_IOCS1 &= ~_BV(IOCS1); - //Z80_O_BUSREQ = 0; - //while(Z80_I_BUSACK == 1); + z80_addrbus_set_tristate(); + z80_dbus_set_in(); - z80_setup_adrbus_tristate(); - z80_setup_dbus_in(); + zstate = RESET; } -void z80_request_bus(void) + +zstate_t z80_bus_state(void) { - Z80_O_BUSREQ = 0; - while(Z80_I_BUSACK == 1); - z80_setup_adrbus_active(); + return zstate; } -void z80_release_bus(void) + +static void z80_busreq_hpulse(void) { - z80_setup_dbus_in(); - z80_setup_adrbus_tristate(); - Z80_O_BUSREQ = 1; - while(Z80_I_BUSACK == 0); + z80_dbus_set_in(); + z80_addrbus_set_tristate(); + + ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { + Z80_O_BUSREQ = 1; + Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */ + Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */ + } + + if (zstate & ZST_ACQUIRED) { + while(Z80_I_BUSACK == 1) + ; + z80_addrbus_set_active(); + } +} + + +/* + + + | | | | | + + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD | + + | | | | | + + | 0 | 1 | 2 | 3 | +Event + | | | | | +----------------+---------------+---------------+---------------+---------------+ + | | | | | +Reset | 0 | 0 | 0 | 0 | + | | | | | + | | | | | +Request | 1 | | 3 | | + | | | | | + | | | | | +Release | | 0 | | 2 | + | | | | | + | | | | | +Run | 2 | 3 | | | + | | | | | + | | | | | +Restart | | | 2 | 3 | + | | | | | + | | | | | +M_Cycle | | | | 3 | + | | | | | + | | | | | +*/ + +zstate_t z80_bus_cmd(bus_cmd_t cmd) +{ + switch (cmd) { + + case Reset: + z80_dbus_set_in(); + z80_addrbus_set_tristate(); + Z80_O_RST = 0; + Z80_O_BUSREQ = 1; + zstate = RESET; + break; + + case Request: + switch (zstate) { + case RESET: + Z80_O_BUSREQ = 0; + Z80_O_RST = 1; + while(Z80_I_BUSACK == 1) + ; + z80_addrbus_set_active(); + zstate = RESET_AQRD; + break; + + case RUNNING: + Z80_O_BUSREQ = 0; + while(Z80_I_BUSACK == 1) + ; + z80_addrbus_set_active(); + zstate = RUNNING_AQRD; + break; + + default: + break; + } + break; + + case Release: + switch (zstate) { + case RESET_AQRD: + z80_dbus_set_in(); + z80_addrbus_set_tristate(); + Z80_O_RST = 0; + Z80_O_BUSREQ = 1; + zstate = RESET; + break; + case RUNNING_AQRD: + z80_dbus_set_in(); + z80_addrbus_set_tristate(); + Z80_O_BUSREQ = 1; + zstate = RUNNING; + break; + default: + break; + } + break; + + case Run: + switch (zstate) { + case RESET: + Z80_O_RST = 1; + zstate = RUNNING; + break; + + case RESET_AQRD: + z80_dbus_set_in(); + z80_addrbus_set_tristate(); + z80_reset_pulse(); + z80_addrbus_set_active(); + zstate = RUNNING_AQRD; + break; + default: + break; + } + break; + + case Restart: + switch (zstate) { + case RUNNING: + case RUNNING_AQRD: + z80_reset_pulse(); + break; + default: + break; + } + break; + + case M_Cycle: + switch (zstate) { + case RUNNING_AQRD: + z80_busreq_hpulse(); + break; + default: + break; + } + } + return zstate; +} + + +/*--------------------------------------------------------------------------*/ + +static +//inline __attribute__ ((always_inline)) +void z80_setaddress(uint32_t addr) +{ + addr_t x; x.l = addr; + + P_ADL = x.b[0]; + P_ADH = x.b[1]; + PIN_ADB = ((x.b[2] << ADB_SHIFT) ^ P_ADB) & MASK(ADB_WIDTH) << ADB_SHIFT ; } void z80_write(uint32_t addr, uint8_t data) { z80_setaddress(addr); Z80_O_MREQ = 0; + z80_dbus_set_out(); P_DB = data; - z80_setup_dbus_out(); + P_DB = data; + Z80_O_WR = 0; Z80_O_WR = 0; Z80_O_WR = 1; Z80_O_MREQ = 1; @@ -318,7 +501,8 @@ uint8_t z80_read(uint32_t addr) z80_setaddress(addr); Z80_O_MREQ = 0; - z80_setup_dbus_in(); + z80_dbus_set_in(); + Z80_O_RD = 0; Z80_O_RD = 0; Z80_O_RD = 0; data = PIN_DB; @@ -331,27 +515,31 @@ uint8_t z80_read(uint32_t addr) void z80_memset(uint32_t addr, uint8_t data, uint32_t length) { - z80_setup_dbus_out(); + z80_dbus_set_out(); Z80_O_MREQ = 0; while(length--) { z80_setaddress(addr++); P_DB = data; + P_DB = data; + Z80_O_WR = 0; Z80_O_WR = 0; Z80_O_WR = 1; } Z80_O_MREQ = 1; } -void z80_write_block(uint8_t *src, uint32_t dest, uint32_t length) +void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length) { uint8_t data; - - z80_setup_dbus_out(); + + z80_dbus_set_out(); Z80_O_MREQ = 0; while(length--) { z80_setaddress(dest++); data = *src++; P_DB = data; + P_DB = data; + Z80_O_WR = 0; Z80_O_WR = 0; Z80_O_WR = 1; } @@ -364,7 +552,7 @@ void z80_write_block(uint8_t *src, uint32_t dest, uint32_t length) 017B' rx.out_idx: ds 1 ; 017C' rx.buf: ds rx.buf_len ; 018B' rx.buf_end equ $-1 ; last byte (start+len-1) - + 018C' tx.bs_mask: ds 1 ; (buf_len - 1) 018D' tx.in_idx: ds 1 ; 018E' tx.out_idx: ds 1 ; @@ -393,7 +581,7 @@ static struct { idx_in, mask; } fifo_dsc[NUM_FIFOS]; - + void z80_memfifo_init(const fifo_t f, uint32_t adr) { @@ -402,13 +590,13 @@ DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, adr); fifo_dsc[f].base = adr; - z80_request_bus(); + z80_bus_cmd(Request); fifo_dsc[f].mask = z80_read(adr + FIFO_BUFSIZE_MASK); fifo_dsc[f].idx_in = z80_read(adr + FIFO_INDEX_IN); fifo_dsc[f].idx_out = z80_read(adr + FIFO_INDEX_OUT); - z80_release_bus(); + z80_bus_cmd(Release); } @@ -421,9 +609,9 @@ int z80_memfifo_is_empty(const fifo_t f) uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN; uint8_t idx; - z80_request_bus(); + z80_bus_cmd(Request); idx = z80_read(adr); - z80_release_bus(); + z80_bus_cmd(Release); rc = idx == fifo_dsc[f].idx_out; } @@ -433,12 +621,12 @@ int z80_memfifo_is_empty(const fifo_t f) int z80_memfifo_is_full(const fifo_t f) { int rc = 1; - + if (fifo_dsc[f].base != 0) { - z80_request_bus(); + z80_bus_cmd(Request); rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask) == z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT); - z80_release_bus(); + z80_bus_cmd(Release); } return rc; } @@ -446,17 +634,17 @@ int z80_memfifo_is_full(const fifo_t f) uint8_t z80_memfifo_getc(const fifo_t f) { uint8_t rc, idx; - + while (z80_memfifo_is_empty(f)) ; - z80_request_bus(); + z80_bus_cmd(Request); idx = fifo_dsc[f].idx_out; rc = z80_read(fifo_dsc[f].base+idx); fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask; z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out); - z80_release_bus(); - + z80_bus_cmd(Release); + return rc; } @@ -464,19 +652,22 @@ uint8_t z80_memfifo_getc(const fifo_t f) void z80_memfifo_putc(fifo_t f, uint8_t val) { int idx; - + while (z80_memfifo_is_full(f)) ; - z80_request_bus(); + z80_bus_cmd(Request); idx = fifo_dsc[f].idx_in; z80_write(fifo_dsc[f].base+idx, val); fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask; z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in); - z80_release_bus(); + z80_bus_cmd(Release); } /*--------------------------------------------------------------------------*/ +/* + TODO: Rewrite msg_fifo routines for AVR +*/ static struct { uint32_t base; @@ -536,9 +727,9 @@ void z80_init_msg_fifo(uint32_t addr) DBG_P(1, "z80_init_msg_fifo: %lx\n", addr); - z80_request_bus(); + z80_bus_cmd(Request); z80_write(addr+FIFO_INDEX_OUT, z80_read(addr+FIFO_INDEX_IN)); - z80_release_bus(); + z80_bus_cmd(Release); msg_fifo.base = addr; } @@ -546,18 +737,20 @@ DBG_P(1, "z80_init_msg_fifo: %lx\n", addr); int z80_msg_fifo_getc(void) { int c = -1; - + +#if 0 if (msg_fifo.count != (NELEMS(msg_fifo.buf) /*- DMA1_CNDTR4 */ )) { c = msg_fifo.buf[msg_fifo.count]; if (++msg_fifo.count == NELEMS(msg_fifo.buf)) msg_fifo.count = 0; if (msg_fifo.base != 0) { - z80_request_bus(); + z80_bus_cmd(Request); z80_write(msg_fifo.base+FIFO_INDEX_OUT, msg_fifo.count); - z80_release_bus(); + z80_bus_cmd(Release); } } +#endif return c; }