X-Git-Url: http://cloudbase.mooo.com/gitweb/z180-stamp.git/blobdiff_plain/f338df2abc35f85961aa6266458f94ea2a102b81..9e689a832629fd09ad60161ddacfe7b05bb00dc5:/avr/z80-if.c diff --git a/avr/z80-if.c b/avr/z80-if.c index ab8e293..726e50b 100644 --- a/avr/z80-if.c +++ b/avr/z80-if.c @@ -84,7 +84,9 @@ struct bits { #define SBIT(port,pin) ((*(volatile struct bits*)&port).b##pin) - +#define P_ZCLK PORTB +#define ZCLK 7 +#define DDR_ZCLK DDRB #define P_MREQ PORTD #define MREQ 4 #define DDR_MREQ DDRD @@ -128,6 +130,7 @@ struct bits { //#define ADB_PORT PORTE +#define Z80_O_ZCLK SBIT(P_ZCLK, 7) #define Z80_O_MREQ SBIT(P_MREQ, 4) #define Z80_O_RD SBIT(P_RD, 3) #define Z80_O_WR SBIT(P_WR, 2) @@ -171,7 +174,7 @@ static void z80_setup_addrbus_tristate(void) DDR_ADB = DDR_ADB & ~(MASK(ADB_WIDTH) << ADB_SHIFT); } - + static void z80_setup_addrbus_active(void) { /* /MREQ, /RD, /WR: Output and high */ @@ -186,20 +189,45 @@ static void z80_setup_addrbus_active(void) } - static void z80_setup_dbus_in(void) { DDR_DB = 0; P_DB = 0; } + static void z80_setup_dbus_out(void) { DDR_DB = 0xff; } + +static void z80_reset_pulse(void) +{ + Z80_O_RST = 0; + _delay_us(10); + Z80_O_RST = 1; +} + +static +void z80_setup_clock(void) +{ + /* ZCLK: Output and low */ + DDR_ZCLK |= _BV(ZCLK); + Z80_O_ZCLK = 0; + + /* Timer1: CTC: Toggle OC1C on compare match */ + PRR0 &= ~_BV(PRTIM1); + OCR1A = 0; + OCR1C = 0; + TCCR1A = (0b01 << COM1C0) | (0b00 << WGM10); + TCCR1B = (0b01 << WGM12) | (0b001 << CS10); +} + void z80_setup_bus(void) { + z80_setup_clock(); + /* /ZRESET: Output and low */ Z80_O_RST = 0; DDR_RST |= _BV(RST); @@ -220,218 +248,165 @@ void z80_setup_bus(void) z80_setup_dbus_in(); zstate = RESET; -// Stat &= ~S_Z180_RUNNING; -} - -/*--------------------------------------------------------------------------*/ -#if 0 - switch (zstate) { - case RESET: - break; - case RESET_AQRD: - break; - case RUN: - break; - case RUN_AQRD: - break; - } -#endif -/*--------------------------------------------------------------------------*/ - -#if 0 -void z80_busreq(level_t level) -{ - Z80_O_BUSREQ = level; -} - -int z80_stat_reset(void) -{ -// return Z80_O_RESET; -} - -int z80_stat_halt(void) -{ - return Z80_I_HALT; } -#endif -zstate_t z80_runstate(void) +zstate_t z80_bus_state(void) { return zstate; } -void z80_reset(void) + +static void z80_busreq_hpulse(void) { -#if DEBUG - zstate_t old = zstate; -#endif z80_setup_dbus_in(); z80_setup_addrbus_tristate(); - Z80_O_RST = 0; - Z80_O_BUSREQ = 1; - zstate = RESET; - - debug("z80_reset: state: %02x --> %02x\n", old, zstate); -} - -void z80_reset_pulse(void) -{ -#if DEBUG - zstate_t old = zstate; -#endif - switch (zstate) { - case RESET: - case RESET_AQRD: - break; - case RUN: - case RUN_AQRD: - Z80_O_RST = 0; - _delay_us(10); - Z80_O_RST = 1; - break; + ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { + Z80_O_BUSREQ = 1; + Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */ + Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */ } - debug("z80_reset_pulse: state: %02x --> %02x\n", old, zstate); -} - -void z80_request_bus(void) -{ -#if DEBUG - zstate_t old = zstate; -#endif - - switch (zstate) { - case RESET: - Z80_O_BUSREQ = 0; - Z80_O_RST = 1; + if (zstate & ZST_ACQUIRED) { while(Z80_I_BUSACK == 1) ; z80_setup_addrbus_active(); - zstate = RESET_AQRD; - break; - - case RESET_AQRD: - break; - - case RUN: - Z80_O_BUSREQ = 0; - while(Z80_I_BUSACK == 1); - z80_setup_addrbus_active(); - zstate = RUN_AQRD; - break; - - case RUN_AQRD: - break; } - debug("z80_request_bus: state: %02x --> %02x\n", old, zstate); } -void z80_release_bus(void) -{ -#if DEBUG - zstate_t old = zstate; -#endif - switch (zstate) { - case RESET: - break; - case RESET_AQRD: - z80_setup_dbus_in(); - z80_setup_addrbus_tristate(); - Z80_O_RST = 0; - Z80_O_BUSREQ = 1; - zstate = RESET; - break; - case RUN: - break; - case RUN_AQRD: - z80_setup_dbus_in(); - z80_setup_addrbus_tristate(); - Z80_O_BUSREQ = 1; - zstate = RUN; - break; - } - - debug("z80_release_bus: state: %02x --> %02x\n", old, zstate); -} /* - * Do nothing, if we have the bus allready - * - * return previous state - */ -zstate_t z80_request_bus_save(void) -{ - zstate_t state; - - state = z80_runstate(); - if (!(state & ZST_ACQUIRED)) - z80_request_bus(); - - return state; -} -/* - * Do nothing, if we had the bus before - */ -void z80_release_bus_save(zstate_t prev) -{ - if (!(prev & ZST_ACQUIRED)) - z80_release_bus(); -} + + | | | | | + + State | RESET | RESET_AQRD | RUNNING | RUNNING_AQRD | + + | | | | | + + | 0 | 1 | 2 | 3 | +Event + | | | | | +----------------+---------------+---------------+---------------+---------------+ + | | | | | +Reset | 0 | 0 | 0 | 0 | + | | | | | + | | | | | +Request | 1 | | 3 | | + | | | | | + | | | | | +Release | | 0 | | 2 | + | | | | | + | | | | | +Run | 2 | 3 | | | + | | | | | + | | | | | +Restart | | | 2 | 3 | + | | | | | + | | | | | +M_Cycle | | | | 3 | + | | | | | + | | | | | +*/ -void z80_run(void) +zstate_t z80_bus_cmd(bus_cmd_t cmd) { -#if DEBUG - zstate_t old = zstate; -#endif - switch (zstate) { - case RESET: - Z80_O_RST = 1; - zstate = RUN; - break; + switch (cmd) { - case RESET_AQRD: + case Reset: z80_setup_dbus_in(); z80_setup_addrbus_tristate(); Z80_O_RST = 0; - _delay_us(10); - Z80_O_RST = 1; - z80_setup_addrbus_active(); - zstate = RUN_AQRD; + Z80_O_BUSREQ = 1; + zstate = RESET; break; - case RUN: - break; - case RUN_AQRD: + case Request: + switch (zstate) { + case RESET: + Z80_O_BUSREQ = 0; + Z80_O_RST = 1; + while(Z80_I_BUSACK == 1) + ; + z80_setup_addrbus_active(); + zstate = RESET_AQRD; + break; + + case RUNNING: + Z80_O_BUSREQ = 0; + while(Z80_I_BUSACK == 1) + ; + z80_setup_addrbus_active(); + zstate = RUNNING_AQRD; + break; + + default: + break; + } break; - } - debug("z80_run: state: %02x --> %02x\n", old, zstate); -} + case Release: + switch (zstate) { + case RESET_AQRD: + z80_setup_dbus_in(); + z80_setup_addrbus_tristate(); + Z80_O_RST = 0; + Z80_O_BUSREQ = 1; + zstate = RESET; + break; + case RUNNING_AQRD: + z80_setup_dbus_in(); + z80_setup_addrbus_tristate(); + Z80_O_BUSREQ = 1; + zstate = RUNNING; + break; + default: + break; + } + break; -void z80_busreq_hpulse(void) -{ - z80_setup_dbus_in(); - z80_setup_addrbus_tristate(); + case Run: + switch (zstate) { + case RESET: + Z80_O_RST = 1; + zstate = RUNNING; + break; + + case RESET_AQRD: + z80_setup_dbus_in(); + z80_setup_addrbus_tristate(); + z80_reset_pulse(); + z80_setup_addrbus_active(); + zstate = RUNNING_AQRD; + break; + default: + break; + } + break; - ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { - Z80_O_BUSREQ = 1; - Z80_O_BUSREQ = 1; /* 2 AVR clock cycles */ - Z80_O_BUSREQ = 0; /* 2 AVR clock cycles */ - } + case Restart: + switch (zstate) { + case RUNNING: + case RUNNING_AQRD: + z80_reset_pulse(); + break; + default: + break; + } + break; - if (zstate & ZST_ACQUIRED) { - while(Z80_I_BUSACK == 1) - ; - z80_setup_addrbus_active(); + case M_Cycle: + switch (zstate) { + case RUNNING_AQRD: + z80_busreq_hpulse(); + break; + default: + break; + } } + return zstate; } + /*--------------------------------------------------------------------------*/ -static +static //inline __attribute__ ((always_inline)) void z80_setaddress(uint32_t addr) { @@ -491,7 +466,7 @@ void z80_memset(uint32_t addr, uint8_t data, uint32_t length) void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length) { uint8_t data; - + z80_setup_dbus_out(); Z80_O_MREQ = 0; while(length--) { @@ -512,7 +487,7 @@ void z80_write_block(const __flash uint8_t *src, uint32_t dest, uint32_t length) 017B' rx.out_idx: ds 1 ; 017C' rx.buf: ds rx.buf_len ; 018B' rx.buf_end equ $-1 ; last byte (start+len-1) - + 018C' tx.bs_mask: ds 1 ; (buf_len - 1) 018D' tx.in_idx: ds 1 ; 018E' tx.out_idx: ds 1 ; @@ -541,7 +516,7 @@ static struct { idx_in, mask; } fifo_dsc[NUM_FIFOS]; - + void z80_memfifo_init(const fifo_t f, uint32_t adr) { @@ -550,13 +525,13 @@ DBG_P(2, "z80_memfifo_init: %i, %lx\n", f, adr); fifo_dsc[f].base = adr; - z80_request_bus(); + z80_bus_cmd(Request); fifo_dsc[f].mask = z80_read(adr + FIFO_BUFSIZE_MASK); fifo_dsc[f].idx_in = z80_read(adr + FIFO_INDEX_IN); fifo_dsc[f].idx_out = z80_read(adr + FIFO_INDEX_OUT); - z80_release_bus(); + z80_bus_cmd(Release); } @@ -569,9 +544,9 @@ int z80_memfifo_is_empty(const fifo_t f) uint32_t adr = fifo_dsc[f].base + FIFO_INDEX_IN; uint8_t idx; - z80_request_bus(); + z80_bus_cmd(Request); idx = z80_read(adr); - z80_release_bus(); + z80_bus_cmd(Release); rc = idx == fifo_dsc[f].idx_out; } @@ -581,12 +556,12 @@ int z80_memfifo_is_empty(const fifo_t f) int z80_memfifo_is_full(const fifo_t f) { int rc = 1; - + if (fifo_dsc[f].base != 0) { - z80_request_bus(); + z80_bus_cmd(Request); rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask) == z80_read(fifo_dsc[f].base+FIFO_INDEX_OUT); - z80_release_bus(); + z80_bus_cmd(Release); } return rc; } @@ -594,17 +569,17 @@ int z80_memfifo_is_full(const fifo_t f) uint8_t z80_memfifo_getc(const fifo_t f) { uint8_t rc, idx; - + while (z80_memfifo_is_empty(f)) ; - z80_request_bus(); + z80_bus_cmd(Request); idx = fifo_dsc[f].idx_out; rc = z80_read(fifo_dsc[f].base+idx); fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask; z80_write(fifo_dsc[f].base+FIFO_INDEX_OUT, fifo_dsc[f].idx_out); - z80_release_bus(); - + z80_bus_cmd(Release); + return rc; } @@ -612,16 +587,16 @@ uint8_t z80_memfifo_getc(const fifo_t f) void z80_memfifo_putc(fifo_t f, uint8_t val) { int idx; - + while (z80_memfifo_is_full(f)) ; - z80_request_bus(); + z80_bus_cmd(Request); idx = fifo_dsc[f].idx_in; z80_write(fifo_dsc[f].base+idx, val); fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask; z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in); - z80_release_bus(); + z80_bus_cmd(Release); } /*--------------------------------------------------------------------------*/ @@ -687,9 +662,9 @@ void z80_init_msg_fifo(uint32_t addr) DBG_P(1, "z80_init_msg_fifo: %lx\n", addr); - z80_request_bus(); + z80_bus_cmd(Request); z80_write(addr+FIFO_INDEX_OUT, z80_read(addr+FIFO_INDEX_IN)); - z80_release_bus(); + z80_bus_cmd(Release); msg_fifo.base = addr; } @@ -697,7 +672,7 @@ DBG_P(1, "z80_init_msg_fifo: %lx\n", addr); int z80_msg_fifo_getc(void) { int c = -1; - + #if 0 if (msg_fifo.count != (NELEMS(msg_fifo.buf) /*- DMA1_CNDTR4 */ )) { c = msg_fifo.buf[msg_fifo.count]; @@ -705,9 +680,9 @@ int z80_msg_fifo_getc(void) msg_fifo.count = 0; if (msg_fifo.base != 0) { - z80_request_bus(); + z80_bus_cmd(Request); z80_write(msg_fifo.base+FIFO_INDEX_OUT, msg_fifo.count); - z80_release_bus(); + z80_bus_cmd(Release); } } #endif