X-Git-Url: http://cloudbase.mooo.com/gitweb/z180-stamp.git/blobdiff_plain/f4d5b4febbffab80cb06bd18564d4c326756fad7..447a805f04115a0e32a1b9ad6be7c0177c3f8977:/z180/z180reg.inc

diff --git a/z180/z180reg.inc b/z180/z180reg.inc
index 616138c..a1a90c2 100644
--- a/z180/z180reg.inc
+++ b/z180/z180reg.inc
@@ -24,7 +24,7 @@ cntla1	equ	IOBASE+01h	;ASCI Control Register A Channel 1
 	b2m MPBR, 3		;Multiprocessor Bit Receive (Read)
 	b2m EFR, 3		;Error Flag Reset (Write)
 	b2m MOD2, 2		;Data Format Mode 1 = 8-Bit data
-	b2m NOD1, 1		;1 = Parity enabled
+	b2m MOD1, 1		;1 = Parity enabled
 	b2m MOD0, 0		;1 = 2 stop bits
 
 cntlb0	equ	IOBASE+02h	;ASCI Control Register B Channel 0
@@ -47,14 +47,14 @@ stat1	equ	IOBASE+05h	;ASCI Status Channel 1
 	b2m FE,4		;Framing Error
 	b2m RIE,3		;Receive Interrupt Enable
 	b2m DCD0,2		;Data Carrier Detect (Ch 0)
-	b2m CTS1E,2		;Clear To Send (Ch 1)
+	b2m CTS1E,2		;Clear To Send Enable (Ch 1)
 	b2m TDRE,1		;Transmit Data Register Empty
 	b2m TIE,0		;Transmit Interrupt Enable
 
-tdr0	equ	IOBASE+06h	;ASCI Transmit Data 
-tdr1	equ	IOBASE+07h	;ASCI Transmit Data 
-rdr0	equ	IOBASE+08h	;ASCI Receive Data 
-rdr1	equ	IOBASE+09h	;ASCI Receive Data 
+tdr0	equ	IOBASE+06h	;ASCI Transmit Data
+tdr1	equ	IOBASE+07h	;ASCI Transmit Data
+rdr0	equ	IOBASE+08h	;ASCI Receive Data
+rdr1	equ	IOBASE+09h	;ASCI Receive Data
 
 cntr	equ	IOBASE+0Ah	;CSI/O Control Register
 trdr	equ	IOBASE+0Bh	;CSI/O Transmit/Receive Data Register
@@ -76,6 +76,13 @@ tcr	equ	IOBASE+10h	;Timer Control Register
 
 asext0	equ	IOBASE+12h	;ASCI Extension Control Register
 asext1	equ	IOBASE+13h	;ASCI Extension Control Register
+	b2m DCD0DIS,6		;DCD0 Disable
+	b2m CTS0DIS,5		;CTS0 Disable
+	b2m X1,4		;CKA * 1 Clock/Samle Rate Divider
+	b2m BRGMOD,3		;BRG Mode (Baud rate generator)
+	b2m BREAKEN,2		;Break Enable
+	b2m BREAK,1		;Break detected
+	b2m SENDBREAK,0		;Send Break
 
 tmdr1l	equ	IOBASE+14h	;Timer Data Register Channel 1
 tmdr1h	equ	IOBASE+15h	;
@@ -94,6 +101,7 @@ cmr	equ	IOBASE+1Eh	;Clock Mutiplier Register
 	b2m LNC,6		;Low Noise Crystal
 
 ccr	equ	IOBASE+1Fh	;CPU Control Register
+	b2m NCD	7		;No Clock Divide
 
 sar0l	equ	IOBASE+20h	;DMA Src Adr Register Channel 0
 sar0h	equ	IOBASE+21h	;
@@ -122,8 +130,8 @@ bcr1h	equ	IOBASE+2Fh	;
 dstat	equ	IOBASE+30h	;DMA Status Register
 	b2m DE1,7		;DMA enable ch 1,0
 	b2m DE0,6		;
-	b2m DWE1,5		;DMA Enable Bit Write Enable 1,0
-	b2m DWE0,4		;
+	b2m NDWE1,5		;DMA Enable Bit Write Enable 1,0
+	b2m NDWE0,4		;
 	b2m DIE1,3		;DMA Interrupt Enable 1,0
 	b2m DIE0,2		;
 	b2m DME,0		;DMA Master enable
@@ -187,4 +195,3 @@ IV$ASCI0 equ	14		;ASCI channel 0
 IV$ASCI1 equ	16		;ASCI channel 1 (lowest priority)
 
 	.list
-