X-Git-Url: http://cloudbase.mooo.com/gitweb/z180-stamp.git/blobdiff_plain/f66d9570ec64ecaa1f879619a0e4fed8d5fa7803..aea51b6c4c93c56715f50e64d424e1181c6d0242:/avr/z80-if.c

diff --git a/avr/z80-if.c b/avr/z80-if.c
index 180a27f..5a4104d 100644
--- a/avr/z80-if.c
+++ b/avr/z80-if.c
@@ -72,6 +72,7 @@
 #define WR		2
 #define P_BUSREQ	PORTD
 #define BUSREQ		7
+#define PIN_BUSREQ	PIND
 #define DDR_BUSREQ	DDRD
 #define P_BUSACK	PORTD
 #define PIN_BUSACK	PIND
@@ -105,6 +106,7 @@
 #define Z80_O_RD	SBIT(P_RD, 3)
 #define Z80_O_WR	SBIT(P_WR, 2)
 #define Z80_O_BUSREQ	SBIT(P_BUSREQ, 7)
+#define Z80_I_BUSREQ	SBIT(PIN_BUSREQ, 7)
 //#define Z80_O_NMI	SBIT(P_NMI, )
 #define Z80_O_RST	SBIT(P_RST, 5)
 #define Z80_I_RST	SBIT(PIN_RST, 5)
@@ -144,7 +146,16 @@ void z80_bus_request_or_exit(void)
 
 static zstate_t zstate;
 static volatile uint8_t timer;		/* used for bus timeout */
-static bool reset_polarity;
+
+
+static volatile uint16_t busack_cycles_ovl;
+
+static uint32_t busack_cycles;
+
+ISR(TIMER4_COMPB_vect)
+{
+	busack_cycles_ovl++;
+}
 
 /*---------------------------------------------------------*/
 /* 10Hz timer interrupt generated by OC5A                  */
@@ -207,7 +218,7 @@ static void z80_dbus_set_out(void)
 
 static void z80_reset_active(void)
 {
-	if (reset_polarity)
+	if (Stat & S_RESET_POLARITY)
 		Z80_O_RST = 1;
 	else
 		Z80_O_RST = 0;
@@ -215,7 +226,7 @@ static void z80_reset_active(void)
 
 static void z80_reset_inactive(void)
 {
-	if (reset_polarity)
+	if (Stat & S_RESET_POLARITY)
 		Z80_O_RST = 0;
 	else
 		Z80_O_RST = 1;
@@ -255,7 +266,10 @@ void z80_setup_bus(void)
 			DDR_SS = (DDR_SS & ~_BV(WAIT)) | _BV(RUN) | _BV(STEP);
 		}
 
-		reset_polarity = Z80_I_RST;
+		if (Z80_I_RST)
+			Stat |= S_RESET_POLARITY;
+		else
+			Stat &= ~S_RESET_POLARITY;
 		z80_reset_active();
 		DDR_RST |= _BV(RST);
 
@@ -271,11 +285,26 @@ void z80_setup_bus(void)
 }
 
 
+uint32_t z80_get_busreq_cycles(void)
+{
+	return busack_cycles;
+}
+
 zstate_t z80_bus_state(void)
 {
 	return zstate;
 }
 
+void z80_toggle_reset(void)
+{
+	Z80_I_RST = 1;
+}
+
+void z80_toggle_busreq(void)
+{
+	Z80_I_BUSREQ = 1;
+}
+
 
 static void z80_busreq_hpulse(void)
 {
@@ -350,6 +379,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
 		z80_dbus_set_in();
 		z80_addrbus_set_in();
 		z80_reset_active();
+		_delay_us(10);
 		Z80_O_BUSREQ = 1;
 		timer = BUS_TO;
 		while (Z80_I_BUSACK == 0 && timer)
@@ -361,13 +391,39 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
 		switch (zstate) {
 		case RESET:
 			Z80_O_BUSREQ = 0;
-			z80_reset_inactive();
-			timer = BUS_TO;
+			timer = 255; //BUS_TO;
+
+			uint16_t tcnt;
+			uint16_t ovl_cnt;
+			uint8_t ifr;
+			busack_cycles = 0;
+			busack_cycles_ovl = 0;
+			ATOMIC_BLOCK(ATOMIC_FORCEON) {
+				Z80_I_RST = 1;					/* Toggle RESET  --> inactive */
+				OCR4B = TCNT4;
+				TIFR4 = _BV(OCF4B);				/* Clear compare match flag */
+//				TIMSK4 &= ~_BV(OCIE4A);		/* Disable Output Compare A interrupt */
+			}
+			TIMSK4 |= _BV(OCIE4B);				/* Enable compare match interrupt */
+
 			while (Z80_I_BUSACK == 1 && timer)
 				;
+
+			ATOMIC_BLOCK(ATOMIC_FORCEON) {
+				tcnt = TCNT4 - OCR4B;
+				ovl_cnt = busack_cycles_ovl;
+				ifr = TIFR4;
+				TIMSK4 &= ~_BV(OCIE4B);			/* Disable compare match interrupt */
+//				TIMSK4 |= _BV(OCIE4A);		/* Enable Output Compare A interrupt */
+			}
 			if (Z80_I_BUSACK == 0) {
+				if ((ifr & _BV(OCF4B)) && !(tcnt & (1<<15)))
+					ovl_cnt++;
+				busack_cycles = tcnt + ((uint32_t) ovl_cnt << 16);
 				z80_addrbus_set_out();
 				zstate = RESET_AQRD;
+//				debug("### ovl: %u, ifr: %u, beg: %u, end: %u\n", ovl_cnt,
+//								(ifr & _BV(OCF4B)) != 0,	OCR4B, tcnt);
 			} else {
 				z80_reset_active();
 				Z80_O_BUSREQ = 1;
@@ -398,6 +454,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
 			z80_dbus_set_in();
 			z80_addrbus_set_in();
 			z80_reset_active();
+			_delay_us(10);
 			Z80_O_BUSREQ = 1;
 			timer = BUS_TO;
 			while (Z80_I_BUSACK == 0 && timer)
@@ -506,6 +563,8 @@ int32_t z80_memsize_detect(void)
 	return addr;
 }
 
+/*--------------------------------------------------------------------------*/
+
 void z80_write(uint32_t addr, uint8_t data)
 {
 	z80_setaddress(addr);
@@ -605,6 +664,7 @@ void z80_read_block (uint8_t *dest, uint32_t src, size_t length)
 	Z80_O_MREQ = 1;
 }
 
+/*--------------------------------------------------------------------------*/
 
 /*
   0179'                         rx.bs_mask:	ds	1		; (buf_len - 1)
@@ -745,3 +805,31 @@ void z80_memfifo_putc(fifo_t f, uint8_t val)
 	z80_write(fifo_dsc[f].base+FIFO_INDEX_IN, fifo_dsc[f].idx_in);
 	z80_bus_cmd(Release);
 }
+
+/*--------------------------------------------------------------------------*/
+
+void z80_load_mem(int_fast8_t verbosity,
+				const FLASH unsigned char data[],
+				const FLASH unsigned long *sections,
+				const FLASH unsigned long address[],
+				const FLASH unsigned long length_of_sections[])
+{
+	uint32_t sec_base = 0;
+
+	if (verbosity > 1)
+		printf_P(PSTR("Loading Z180 memory... \n"));
+
+	for (unsigned sec = 0; sec < *sections; sec++) {
+		if (verbosity > 0) {
+			printf_P(PSTR("   From: 0x%.5lX to: 0x%.5lX    (%5li bytes)\n"),
+					address[sec],
+					address[sec]+length_of_sections[sec] - 1,
+					length_of_sections[sec]);
+		}
+
+		z80_write_block_P((const FLASH unsigned char *) &data[sec_base],  /* src */
+				address[sec],                  /* dest */
+				length_of_sections[sec]);      /* len */
+		sec_base += length_of_sections[sec];
+	}
+}