blob: 154ef8586d3832fc72e46ee7996d2d98ae2b9794 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
|
.xlist
;;
;; TMPZ84C015 Register Definitions
;;
CTC_CH0 equ 010h ;
CTC_CH1 equ 011h ;
CTC_CH2 equ 012h ;
CTC_CH3 equ 013h ;
SIOAData equ 018h ;
SIOACtrl equ 019h ;
SIOBData equ 01Ah ;
SIOBCtrl equ 01Bh ;
PIOAData equ 01Ch ;
PIOACtrl equ 01Dh ;
PIOBData equ 01Eh ;
PIOBCtrl equ 01Fh ;
WDTMR equ 0F0h ;Watch Dog Timer Master Register */
WDTCR equ 0F1h ;Watch Dog Timer Command Register */
INTPR equ 0F4h ;Interrupt Priority Register */
;SIO WR0
R0 equ 00h ;SIO register pointer
R1 equ 01h ;
R2 equ 02h ;
R3 equ 03h ;
R4 equ 04h ;
R5 equ 05h ;
R6 equ 06h ;
R7 equ 07h ;
SA equ 08h ;Send Abort (SDLC)
RESI equ 10h ;Reset Ext/Stat Int
CHRST equ 18h ;Channel Reset
EIRXNXT equ 20h ;Enable Int On Next Rx Char
RTXIP equ 28h ;Reset Tx Int Pending
ER equ 30h ;Error Reset
RFI equ 38h ;Return From Int
RRXCC equ 40h ;Reset Rx CRC Checker
RTXCG equ 80h ;Reset Tx CRC Generator
RTXUEL equ 0c0h ;Reset Tx Under/EOM Latch
;SIO WR1
WAIT equ 00h ;
EXTIE equ 01h ;Ext Int Enable
TXIE equ 02h ;Tx Int Enable
SAVECT equ 04h ;Status Affects Vector (Ch B only)
RXIDIS equ 00h ;Rx Int Disable
RXIFRST equ 08h ;Rx Int on First Character
RXIAPA equ 10h ;Rx Int on All Characters (Parity Affects Vector)
RXIAPN equ 18h ;Rx Int on All Characters (Parity Does Not Affect Vector)
WRONRX equ 20h ;Wait/Ready On Receive
RDY equ 40h ;Ready Function
WRDYEN equ 80h ;Wait/Ready enable
;SIO WR3
RXEN equ 01h ;Rx Enable
AUTOEN equ 20h ;Auto Enable
RXB7 equ 40h ;RX 7 bits/character
RXB6 equ 80h ;RX 6 bits/character
RXB8 equ 0c0h ;RX 8 bits/character
;SIO WR4
PAREN equ 01h ;Parity Enable
PAREVEN equ 02h ;Parity Even
STOP1 equ 04h ;1 Stop Bit
STOP1H equ 08h ;1 and a Half Stop Bits
STOP2 equ 0ch ;2 Stop Bits
CLK1 equ 00h ;Clock Mode X1
CLK16 equ 40h ;Clock Mode X16
CLK32 equ 80h ;Clock Mode X32
CLK64 equ 0c0h ;Clock Mode X64
;SIO WR5
RTS equ 02h ;Request To Send
TXEN equ 08h ;Tx Enable
TXBREAK equ 10h ;Send Break
TX7B equ 20h ;Tx 7 bits/character
TX6B equ 40h ;Tx 6 bits/character
TX8B equ 60h ;Tx 8 bits/character
DTR equ 80h ;Data Terminal Ready
;SIO RR0 - Status of Rx and Tx Buffers
BREAK equ 7 ;Break/Abort
TXUEOM equ 6 ;TX Underrun EOM
CTS equ 5 ;
SHBE equ 4 ;Sync/Hunt Buffer Empty
DCD equ 3 ;
TXE equ 2 ;TX Buffer Empty
INTPEND equ 1 ;Interrupt Pending
RXCA equ 0 ;RX Char available
;SIO RR1 - Special Receive Condition Status
EOF equ 7 ;End Of Frame
CRCFE equ 6 ;CRC/Framing Error
RXOE equ 5 ;Rx Overrun Error
PE equ 4 ;Parity Error
TXALL equ 0 ;All Sent
;SIO RR2 - Interrupt Vector (Channel B only)
.list
|