libopencm3: Set PWM duty cycle to 33%. Improve timer handling.

1 files changed, 15 insertions, 24 deletions

diff --git a/irsnd.c b/irsnd.c
index f421731..fab3d47 100644
--- a/irsnd.c
+++ b/irsnd.c
@@ -557,8 +557,6 @@ irsnd_on (void)
 

 #  elif defined (LIBOPENCM3)                             // STM32 whit libopencm3

         timer_set_oc_mode(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCM_PWM1);

-        timer_generate_event(IRSND_TIMER, TIM_EGR_UG);

-        timer_enable_counter(IRSND_TIMER);

 

 #  elif defined (TEENSY_ARM_CORTEX_M4)                  // TEENSY

         analogWrite(IRSND_PIN, 33 * 255 / 100);         // pwm 33%

@@ -636,9 +634,7 @@ irsnd_off (void)
         TIM_SetCounter(IRSND_TIMER, 0);                                                 // reset counter value

 

 #  elif defined (LIBOPENCM3)                                                             // STM32

-        timer_set_oc_mode(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCM_FORCE_LOW);

-        timer_disable_counter(IRSND_TIMER);

-        timer_set_counter(IRSND_TIMER, 0);

+        timer_set_oc_mode(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCM_INACTIVE);

 

 #  elif defined (TEENSY_ARM_CORTEX_M4)                                                  // TEENSY

         analogWrite(IRSND_PIN, 0);                                                      // pwm off, LOW level

@@ -782,8 +778,10 @@ irsnd_set_freq (IRSND_FREQ_TYPE freq)
 

         /* Set frequency */

         timer_set_period(IRSND_TIMER, freq - 1);

-        /* Set duty cycle */

-        timer_set_oc_value(IRSND_TIMER, IRSND_TIMER_CHANNEL, (freq + 1) / 2);

+        /* Set duty cycle to 33% */

+        timer_set_oc_value(IRSND_TIMER, IRSND_TIMER_CHANNEL, (freq + 2) / 3);

+        timer_set_counter(IRSND_TIMER, 0);

+        timer_enable_counter(IRSND_TIMER);

 

 #  elif defined (TEENSY_ARM_CORTEX_M4)

         analogWriteResolution(8);                                                           // 8 bit

@@ -896,34 +894,27 @@ irsnd_init (void)
 #  elif defined (LIBOPENCM3)

        /* GPIOx clock enable */

         rcc_periph_clock_enable(IRSND_PORT_RCC);

-

-        /* GPIO Configuration */

-#    if 0

-        gpio_set_mode(IRSND_PORT, GPIO_MODE_OUTPUT_2_MHZ,

-                  GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, IRSND_BIT);

-#    else

-        gpio_set_mode(IRSND_PORT, GPIO_MODE_OUTPUT_2_MHZ,

-                  GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, IRSND_BIT);

-#    endif

         /* TIMx clock enable */

         rcc_periph_clock_enable(IRSND_TIMER_RCC);

 

         /* Time base configuration */

+        /* Stop timer and set it to its default mode (edge-aligned upcounting) */

         timer_reset(IRSND_TIMER);

-        timer_set_mode(IRSND_TIMER, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE,

-                        TIM_CR1_DIR_UP);

-        timer_set_period(IRSND_TIMER, -1);

-        timer_enable_preload(IRSND_TIMER);

 

-        /* PWM1 Mode configuration */

-        timer_set_oc_mode(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCM_FORCE_LOW);

+        /* PWM Mode configuration */

+        timer_set_oc_mode(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCM_INACTIVE);

         timer_enable_oc_output(IRSND_TIMER, IRSND_TIMER_CHANNEL);

-        timer_enable_oc_preload(IRSND_TIMER, IRSND_TIMER_CHANNEL);

         timer_enable_break_main_output(IRSND_TIMER);

+

+        /* Output polarity and GPIO Configuration */

 #    if 0

-        timer_set_oc_polarity_high(IRSND_TIMER, IRSND_TIMER_CHANNEL);

+        /* (active) high is the default output polarity */

+        gpio_set_mode(IRSND_PORT, GPIO_MODE_OUTPUT_2_MHZ,

+                  GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, IRSND_BIT);

 #    else

         timer_set_oc_polarity_low(IRSND_TIMER, IRSND_TIMER_CHANNEL);

+        gpio_set_mode(IRSND_PORT, GPIO_MODE_OUTPUT_2_MHZ,

+                  GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, IRSND_BIT);

 #    endif

 

 #  elif defined (TEENSY_ARM_CORTEX_M4)