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authorLeo C2016-08-30 23:11:32 +0200
committerLeo C2016-08-30 23:11:32 +0200
commit61bd408cda6cc14d11bd9815828df2e8dec39bec (patch)
tree197499c394dd586bbb66736f1e5fcf81aea190df /avr
parent66e23a9dc242ecc830902867c63c37745a4d5c07 (diff)
downloadz180-stamp-61bd408cda6cc14d11bd9815828df2e8dec39bec.zip
Detect ZRESET polarity
Diffstat (limited to 'avr')
-rw-r--r--avr/z80-if.c40
1 files changed, 31 insertions, 9 deletions
diff --git a/avr/z80-if.c b/avr/z80-if.c
index 08d417b..e36b369 100644
--- a/avr/z80-if.c
+++ b/avr/z80-if.c
@@ -78,6 +78,7 @@
#define BUSACK 6
#define DDR_BUSACK DDRD
#define P_RST PORTD
+#define PIN_RST PIND
#define DDR_RST DDRD
#define RST 5
@@ -106,6 +107,7 @@
#define Z80_O_BUSREQ SBIT(P_BUSREQ, 7)
//#define Z80_O_NMI SBIT(P_NMI, )
#define Z80_O_RST SBIT(P_RST, 5)
+#define Z80_I_RST SBIT(PIN_RST, 5)
#define Z80_I_BUSACK SBIT(PIN_BUSACK, 6)
//#define Z80_I_HALT SBIT(P_HALT, )
@@ -137,6 +139,7 @@
static zstate_t zstate;
static volatile uint8_t timer; /* used for bus timeout */
+static bool reset_polarity;
/*---------------------------------------------------------*/
/* 10Hz timer interrupt generated by OC4A */
@@ -197,12 +200,27 @@ static void z80_dbus_set_out(void)
DDR_DB = 0xff;
}
+static void z80_reset_active(void)
+{
+ if (reset_polarity)
+ Z80_O_RST = 1;
+ else
+ Z80_O_RST = 0;
+}
+
+static void z80_reset_inactive(void)
+{
+ if (reset_polarity)
+ Z80_O_RST = 0;
+ else
+ Z80_O_RST = 1;
+}
static void z80_reset_pulse(void)
{
- Z80_O_RST = 0;
+ z80_reset_active();
_delay_us(10);
- Z80_O_RST = 1;
+ z80_reset_inactive();
}
@@ -210,9 +228,9 @@ void z80_setup_bus(void)
{
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
- /* /ZRESET: Output and low */
+ /* /ZRESET: Input, no pullup */
+ DDR_RST &= ~_BV(RST);
Z80_O_RST = 0;
- DDR_RST |= _BV(RST);
/* /BUSREQ: Output and high */
Z80_O_BUSREQ = 1;
@@ -232,6 +250,10 @@ void z80_setup_bus(void)
DDR_SS = (DDR_SS & ~_BV(WAIT)) | _BV(RUN) | _BV(STEP);
}
+ reset_polarity = Z80_I_RST;
+ z80_reset_active();
+ DDR_RST |= _BV(RST);
+
zstate = RESET;
}
@@ -322,7 +344,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
case Reset:
z80_dbus_set_in();
z80_addrbus_set_in();
- Z80_O_RST = 0;
+ z80_reset_active();
Z80_O_BUSREQ = 1;
zstate = RESET;
break;
@@ -331,7 +353,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
switch (zstate) {
case RESET:
Z80_O_BUSREQ = 0;
- Z80_O_RST = 1;
+ z80_reset_inactive();
timer = BUS_TO;
while (Z80_I_BUSACK == 1 && timer)
;
@@ -339,7 +361,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
z80_addrbus_set_out();
zstate = RESET_AQRD;
} else {
- Z80_O_RST = 0;
+ z80_reset_active();
Z80_O_BUSREQ = 1;
}
break;
@@ -367,7 +389,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
case RESET_AQRD:
z80_dbus_set_in();
z80_addrbus_set_in();
- Z80_O_RST = 0;
+ z80_reset_active();
Z80_O_BUSREQ = 1;
zstate = RESET;
break;
@@ -385,7 +407,7 @@ zstate_t z80_bus_cmd(bus_cmd_t cmd)
case Run:
switch (zstate) {
case RESET:
- Z80_O_RST = 1;
+ z80_reset_inactive();
zstate = RUNNING;
break;