Swap pins for IOSEL1 and /BUSACK. IOSEL --> TIM3_CH4 (DMA-REQ)

3 files changed, 206 insertions, 182 deletions

diff --git a/stm32/Rules.mk b/stm32/Rules.mk
index 4751496..764851b 100644
--- a/stm32/Rules.mk
+++ b/stm32/Rules.mk
@@ -137,8 +137,10 @@ flash: $(P_BINARY).flash
 %.flash: %.elf
 	$(call echo_cmd,GDB $< (flash)) $(GDB) --batch \
 		   -ex 'target extended-remote $(STLINK_PORT)' \
-		   -x $(SCRIPT_DIR)/stlink_flash.scr \
+		   -ex 'monitor reset halt' \
+		   -ex 'load' \
 		   $<
 
+
 .PHONY: images elf bin hex srec list flash
 
diff --git a/stm32/z80-if.c b/stm32/z80-if.c
index a8083c8..a9ce884 100644
--- a/stm32/z80-if.c
+++ b/stm32/z80-if.c
@@ -1,21 +1,62 @@
-/*
-
-PC14	af1	OSC32
-PC15	"	"
-PA9	af1	USART1_TX
-PA10	af1	USART1_RX
-
+/**
+ *
+ * Pin assignments
+ *
+ * | Z180-Sig | STM32-Port | Buffer | Dir |Special Function |
+ * | -------- | ---------- | ------ | --- | --------------- |
+ * |	A0	|A	1	|P	|O | |
+ * |	A1	|A	2	|P	|O | |
+ * |	A2	|A	3	|P	|O | |
+ * |	A3	|A	4	|P	|O | |
+ * |	A4	|A	5	|P	|O | |
+ * |	A5	|A	6	|P	|O | |
+ * |	A6	|A	7	|P	|O | |
+ * |	A7	|A	8	|	|O | |
+ * |	A8	|C	0	|P	|O | |
+ * |	A9	|C	1	|P	|O | |
+ * |	A10	|C	2	|P	|O | |
+ * |	A11	|C	3	|P	|O | |
+ * |	A12	|C	4	|P	|O | |
+ * |	A13	|C	5	|P	|O | |
+ * |	A14	|C	6	|	|O | |
+ * |	A15	|C	7	|	|O | |
+ * |	A16	|C	10	|	|O | |
+ * |	A17	|C	11	|	|O | |
+ * |	A18	|C	12	|	|O | |
+ * |	D0	|B	8	|	|I/O | |
+ * |	D1	|B	9	|	|I/O | |
+ * |	D2	|B	10	|	|I/O | |
+ * |	D3	|B	11	|	|I/O | |
+ * |	D4	|B	12	|	|I/O | |
+ * |	D5	|B	13	|	|I/O | |
+ * |	D6	|B	14	|	|I/O | |
+ * |	D7	|B	15	|	|I/O | |
+ * |	ME	|C	13	|P	|O | |
+ * |	RD	|B	0	|P	|O | |
+ * |	WR	|B	1	|P	|O | |
+ * |	BUSREQ	|D	2	|	|O | |
+ * |	IOCS1	|A	11	|	|I	|TIM1_CH4 |
+ * |	BUSACK	|A	12	|	|I | |
+ * |	HALT	|A	12	|	|I | |
+ * |	NMI	|B	7	|	|O | |
+ * |	RST	|B	6	|	|O	|TIM16_CH1N |
+ * |		|		|	|  	| |
+ * |		|A 9		|	|  	|af1	USART1_TX |
+ * |		|A 10		|	|  	|af1	USART1_RX |
+ * |		|A 15		|	|JTDI	|	remap	SPI1_NSS' |
+ * |		|B 3		|	|JTDO	|remap	 SPI1_SCK' |
+ * |		|B 4		|	|NJTRST	|remap	SPI1_MISO' |
+ * |		|B 5		|	|	|remap	SPI1_MOSI' |
+ * |		|C 14		|	|	|af1	OSC32 |
+ * |		|C 15		|	|	|af1	OSC32 |
 
-JTDO	remap	PB3, SPI1_SCK'
-NJTRST	remap	PB4, SPI1_MISO'
-PB5	remap	SPI1_MOSI'
-JTDI	remap	PA15, SPI1_NSS'
 
 AFIO_MAPR2 =
 AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON  (frees 
 AFIO_MAPR_SPI1_REMAP 
 
-*/
+ */
+
 
 #include <libopencm3/stm32/gpio.h>
 #include <libopencm3/stm32/rcc.h>
@@ -34,49 +75,8 @@ AFIO_MAPR_SPI1_REMAP
 
 #define GPIO_(X)	CONCAT(GPIO, X)
 
-/*
 
-	A0	A	1	P	O
-	A1	A	2	P	O
-	A2	A	3	P	O
-	A3	A	4	P	O
-	A4	A	5	P	O
-	A5	A	6	P	O
-	A6	A	7	P	O
-	A7	A	8		O
-	A8	C	0	P	O
-	A9	C	1	P	O
-	A10	C	2	P	O
-	A11	C	3	P	O
-	A12	C	4	P	O
-	A13	C	5	P	O
-	A14	C	6		O
-	A15	C	7		O
-	A16	C	10		O
-	A17	C	11		O
-	A18	C	12		O
-
-	D0	B	8		I/O
-	D1	B	9		I/O
-	D2	B	10		I/O
-	D3	B	11		I/O
-	D4	B	12		I/O
-	D5	B	13		I/O
-	D6	B	14		I/O
-	D7	B	15		I/O
-
-	ME	C	13	P	O
-	RD	B	0	P	O
-	WR	B	1	P	O
-
-	BUSREQ	D	2		O
-	BUSACK	A	11		I
-//	HALT	A	12		I
-	IOE	A	12		I	TIM1_ETR
-	NMI	B	7		O
-	RST	B	6		O	TIM16_CH1N
 
-*/
 
 #define P_ME		GPIOC
 #define ME		13
@@ -87,11 +87,11 @@ AFIO_MAPR_SPI1_REMAP
 #define P_BUSREQ	GPIOD
 #define BUSREQ		2
 #define P_BUSACK	GPIOA
-#define BUSACK		11
+#define BUSACK		12
 //#define P_HALT		GPIOA
 //#define HALT		12
-#define P_IOE		GPIOA
-#define IOE		12
+#define P_IOCS1		GPIOA
+#define IOCS1		11
 #define P_NMI		GPIOB
 #define NMI		7
 #define P_RST		GPIOB
@@ -135,7 +135,7 @@ AFIO_MAPR_SPI1_REMAP
 #define GPIO_BUSREQ	GPIO_(BUSREQ)
 #define GPIO_BUSACK	GPIO_(BUSACK)
 //#define GPIO_HALT	GPIO_(HALT)
-#define GPIO_IOE	GPIO_(IOE)
+#define GPIO_IOCS1	GPIO_(IOCS1)
 #define GPIO_NMI	GPIO_(NMI)
 #define GPIO_RST	GPIO_(RST)
 
@@ -182,27 +182,15 @@ AFIO_MAPR_SPI1_REMAP
 
 /*--------------------------------------------------------------------------*/
 
-volatile uint8_t z80_inbuf[256];
-static uint32_t inbuf_ndt;
-
-/*--------------------------------------------------------------------------*/
-
-#define TIM16_BDTR			TIM_BDTR(TIM16)
-
 static void tim16_setup(void)
 {
-	RCC_APB2RSTR |= (1<<17);
-	RCC_APB2RSTR &= ~(1<<17);
+	RCC_APB2RSTR |= RCC_APB2RSTR_TIM16RST;
+	RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM16RST;
 	
 	TIM16_BDTR = TIM_BDTR_MOE;
 		
 	TIM16_CCMR1 = 0
 		| TIM_CCMR1_OC1M_FORCE_LOW	
-	/*	| TIM_CCMR1_OC1M_FORCE_HIGH	*/
-	/*	| TIM_CCMR1_OC1M_PWM2		*/
-		
-	/*	| TIM_CCMR1_OC1PE		*/
-	/*	| TIM_CCMR1_OC1FE		*/
 		| TIM_CCMR1_CC1S_OUT;
 		
 	TIM16_CCER = TIM_CCER_CC1NE
@@ -214,63 +202,7 @@ static void tim16_setup(void)
 
 /*--------------------------------------------------------------------------*/
 
-static void tim1_setup(void)
-{
-	RCC_APB2RSTR |= RCC_APB2RSTR_TIM1RST;
-	RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM1RST;
-	
-	TIM1_CR1 = 0;
-	
-	TIM1_SMCR = 0
-	/*	| TIM_SMCR_ETP			*/
-	/*	| TIM_SMCR_ETF_CK_INT_N_2	*/
-		| TIM_SMCR_TS_ETRF
-		| TIM_SMCR_SMS_OFF		
-		;
-		
-	TIM1_DIER = TIM_DIER_TDE;
-
-			
-	TIM1_CCMR1 = 0
-		| TIM_CCMR1_OC1M_FORCE_LOW	
-	/*	| TIM_CCMR1_OC1M_FORCE_HIGH	*/
-	/*	| TIM_CCMR1_OC1M_PWM2		*/
-		
-	/*	| TIM_CCMR1_OC1PE		*/
-	/*	| TIM_CCMR1_OC1FE		*/
-		| TIM_CCMR1_CC1S_OUT;
-		
-	TIM1_SMCR |= TIM_SMCR_SMS_TM;
-	/*	| TIM_SMCR_SMS_ECM1		*/
-}
-
-/*--------------------------------------------------------------------------*/
-
-static void dma4_setup(void)
-{
-	DMA1_CCR4 =
-		DMA_CCR_PL_VERY_HIGH
-		| DMA_CCR_MSIZE_8BIT
-		| DMA_CCR_PSIZE_8BIT
-		| DMA_CCR_MINC
-		| DMA_CCR_CIRC;
-
-	DMA1_CMAR4 = (uint32_t) &z80_inbuf[0];
-
-#if (DB_SHIFT == 0) || (DB_SHIFT == 8)
-	DMA1_CPAR4 = DB_PORT + IDR + DB_SHIFT/8;
-#else
-	#error "Databus not byte aligned!"
-#endif
-
-	DMA1_CNDTR4 = inbuf_ndt = NELEMS(z80_inbuf);
-	
-	DMA1_CCR4 |= DMA_CCR_EN;
-}
-
-/*--------------------------------------------------------------------------*/
-
-void tim16_set(int mode)
+static void tim16_set(int mode)
 {
 	uint16_t cc_mode;
 	
@@ -359,9 +291,7 @@ static void z80_setaddress(uint32_t addr)
 void z80_setup_bus(void)
 {
 	tim16_setup();
-	tim1_setup();
-	dma4_setup();
-	
+
 	gpio_set_mode(P_RST, GPIO_MODE_OUTPUT_10_MHZ,
 		GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_RST);
 	Z80_O_BUSREQ = 1;
@@ -378,9 +308,6 @@ void z80_setup_bus(void)
 	gpio_set_mode(P_RD, GPIO_MODE_OUTPUT_10_MHZ,
 		GPIO_CNF_OUTPUT_PUSHPULL, GPIO_RD | GPIO_WR);
 
-	gpio_set_mode(P_BUSACK, GPIO_MODE_INPUT,
-		GPIO_CNF_INPUT_FLOAT, GPIO_BUSACK | GPIO_IOE);
-
 	//Z80_O_BUSREQ = 0;
 	//while(Z80_I_BUSACK == 1);
 
@@ -394,7 +321,7 @@ void z80_setup_bus(void)
 	z80_setup_dbus_in();
 }
 
-void z80_get_bus(void)
+void z80_request_bus(void)
 {
 	Z80_O_BUSREQ = 0;
 	while(Z80_I_BUSACK == 1);
@@ -517,89 +444,183 @@ static struct {
 	uint8_t idx_out,
 		idx_in,
 		mask;
-	} fifos[2];
+	} fifo_dsc[2];
 	
-void z80_fifo_init(void)
+void z80_memfifo_init(void)
 {
-	z80_get_bus();
-	fifos[fifo_in].base = tx_fifo;
-	fifos[fifo_in].idx_out = z80_read(tx_fifo+fifo_index_out);
-	fifos[fifo_in].idx_in = z80_read(tx_fifo+fifo_index_in);
-	fifos[fifo_in].mask = z80_read(tx_fifo+fifo_bufsize_mask);
-
-	fifos[fifo_out].base = rx_fifo;
-	fifos[fifo_out].idx_out = z80_read(rx_fifo+fifo_index_out);
-	fifos[fifo_out].idx_in = z80_read(rx_fifo+fifo_index_in);
-	fifos[fifo_out].mask = z80_read(rx_fifo+fifo_bufsize_mask);
+	z80_request_bus();
+	fifo_dsc[fifo_in].base = tx_fifo;
+	fifo_dsc[fifo_in].idx_out = z80_read(tx_fifo+fifo_index_out);
+	fifo_dsc[fifo_in].idx_in = z80_read(tx_fifo+fifo_index_in);
+	fifo_dsc[fifo_in].mask = z80_read(tx_fifo+fifo_bufsize_mask);
+
+	fifo_dsc[fifo_out].base = rx_fifo;
+	fifo_dsc[fifo_out].idx_out = z80_read(rx_fifo+fifo_index_out);
+	fifo_dsc[fifo_out].idx_in = z80_read(rx_fifo+fifo_index_in);
+	fifo_dsc[fifo_out].mask = z80_read(rx_fifo+fifo_bufsize_mask);
 	z80_release_bus();
 }
 #endif
 
-int z80_fifo_is_not_empty(fifo_t f)
+int z80_memfifo_is_empty(fifo_t f)
 {
-	uint32_t adr = fifos[f].base+fifo_index_in;
+	uint32_t adr = fifo_dsc[f].base+fifo_index_in;
 	uint8_t idx;
 	
-	z80_get_bus();
+	z80_request_bus();
 	idx = z80_read(adr);
 	z80_release_bus();
 
-	return idx != fifos[f].idx_out;
+	return idx == fifo_dsc[f].idx_out;
 }
 
-int z80_fifo_is_not_full(fifo_t f)
+int z80_memfifo_is_full(fifo_t f)
 {
 	int rc;
 	
-	z80_get_bus();
-	rc = ((fifos[f].idx_in + 1) & fifos[f].mask)
-		!= z80_read(fifos[f].base+fifo_index_out);
+	z80_request_bus();
+	rc = ((fifo_dsc[f].idx_in + 1) & fifo_dsc[f].mask)
+		== z80_read(fifo_dsc[f].base+fifo_index_out);
 	z80_release_bus();
 	
 	return rc;
 }
 
-uint8_t z80_fifo_getc(fifo_t f)
+uint8_t z80_memfifo_getc(fifo_t f)
 {
 	uint8_t rc, idx;
 	
-	while (!z80_fifo_is_not_empty(f)) 
+	while (z80_memfifo_is_empty(f))
 		;
 
-	z80_get_bus();
-	idx = fifos[f].idx_out;
-	rc = z80_read(fifos[f].base+idx);
-	fifos[f].idx_out = ++idx & fifos[f].mask;
-	z80_write(fifos[f].base+fifo_index_out, fifos[f].idx_out);
+	z80_request_bus();
+	idx = fifo_dsc[f].idx_out;
+	rc = z80_read(fifo_dsc[f].base+idx);
+	fifo_dsc[f].idx_out = ++idx & fifo_dsc[f].mask;
+	z80_write(fifo_dsc[f].base+fifo_index_out, fifo_dsc[f].idx_out);
 	z80_release_bus();
 	
 	return rc;
 }
 
 
-void z80_fifo_putc(fifo_t f, uint8_t val)
+void z80_memfifo_putc(fifo_t f, uint8_t val)
 {
 	int idx;
 	
-	while (!z80_fifo_is_not_full(f)) 
+	while (z80_memfifo_is_full(f))
 		;
 
-	z80_get_bus();
-	idx = fifos[f].idx_in;
-	z80_write(fifos[f].base+idx, val);
-	fifos[f].idx_in = ++idx & fifos[f].mask;
-	z80_write(fifos[f].base+fifo_index_in, fifos[f].idx_in);
+	z80_request_bus();
+	idx = fifo_dsc[f].idx_in;
+	z80_write(fifo_dsc[f].base+idx, val);
+	fifo_dsc[f].idx_in = ++idx & fifo_dsc[f].mask;
+	z80_write(fifo_dsc[f].base+fifo_index_in, fifo_dsc[f].idx_in);
 	z80_release_bus();
 }
 
-int z80_inbuf_getc(void)
+/*--------------------------------------------------------------------------*/
+
+//volatile uint8_t io_infifo[256];
+
+static struct {
+	uint8_t  idx_out,
+		 idx_in;
+	uint16_t count;
+	uint8_t  buf[256];
+	} io_infifo;
+
+/*--------------------------------------------------------------------------*/
+
+static void tim1_setup(void)
+{
+	RCC_APB2RSTR |= RCC_APB2RSTR_TIM1RST;
+	RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM1RST;
+
+	TIM1_CR1 = 0;
+
+	TIM1_SMCR = 0
+	/*	| TIM_SMCR_ETP			*/
+	/*	| TIM_SMCR_ETF_CK_INT_N_2	*/
+		| TIM_SMCR_TS_ETRF
+		| TIM_SMCR_SMS_OFF
+		;
+
+	TIM1_DIER = TIM_DIER_TDE;
+
+
+	TIM1_CCMR1 = 0
+		| TIM_CCMR1_OC1M_FORCE_LOW
+		| TIM_CCMR1_CC1S_OUT;
+
+	TIM1_SMCR |= TIM_SMCR_SMS_TM;
+}
+
+/*--------------------------------------------------------------------------*/
+
+static void tim1_ch4_setup(void)
+{
+	/* Reset Timer 1 */
+	RCC_APB2RSTR |= RCC_APB2RSTR_TIM1RST;
+	RCC_APB2RSTR &= ~RCC_APB2RSTR_TIM1RST;
+
+	TIM1_CCMR2 = 0
+		| TIM_CCMR2_CC4S_IN_TI2
+		| TIM_CCMR2_IC4F_OFF
+		| TIM_CCMR2_IC4PSC_OFF;
+
+	TIM1_CCER = 0
+	/*	| TIM_CCER_CC4P */
+		| TIM_CCER_CC4E;
+
+	/* Enable DMA for channel 4 */
+	TIM1_DIER = TIM_DIER_CC4DE;
+}
+
+/*--------------------------------------------------------------------------*/
+
+static void dma1_ch4_setup(void)
+{
+	DMA1_CCR4 =
+		DMA_CCR_PL_VERY_HIGH
+		| DMA_CCR_MSIZE_8BIT
+		| DMA_CCR_PSIZE_8BIT
+		| DMA_CCR_MINC
+		| DMA_CCR_CIRC;
+
+	DMA1_CMAR4 = (uint32_t) io_infifo.buf;
+
+#if (DB_SHIFT == 0) || (DB_SHIFT == 8)
+	DMA1_CPAR4 = DB_PORT + IDR + DB_SHIFT/8;
+#else
+	#error "Databus not byte aligned!"
+#endif
+
+	DMA1_CNDTR4 = io_infifo.count = NELEMS(io_infifo.buf);
+
+	DMA1_CCR4 |= DMA_CCR_EN;
+}
+
+/*--------------------------------------------------------------------------*/
+
+void z80_setup_io_infifo(void)
+{
+	gpio_set_mode(P_BUSACK, GPIO_MODE_INPUT,
+		GPIO_CNF_INPUT_FLOAT, GPIO_BUSACK | GPIO_IOCS1);
+
+	tim1_ch4_setup();
+	dma1_ch4_setup();
+}
+
+
+int z80_io_infifo_getc(void)
 {
 	int c = -1;
 	
-	if (inbuf_ndt != DMA1_CNDTR4) {
-		c = z80_inbuf[NELEMS(z80_inbuf) - inbuf_ndt--];
-		if (inbuf_ndt == 0)
-			inbuf_ndt = NELEMS(z80_inbuf);
+	if (io_infifo.count != DMA1_CNDTR4) {
+		c = io_infifo.buf[NELEMS(io_infifo.buf) - io_infifo.count--];
+		if (io_infifo.count == 0)
+			io_infifo.count = NELEMS(io_infifo.buf);
 	}
 
 	return c;
diff --git a/stm32/z80-if.h b/stm32/z80-if.h
index 914ead5..09ef901 100644
--- a/stm32/z80-if.h
+++ b/stm32/z80-if.h
@@ -9,7 +9,7 @@ typedef enum {LOW, HIGH} level_t;
 void z80_setup_bus(void);
 void z80_write(uint32_t addr, uint8_t data);
 uint8_t z80_read(uint32_t addr);
-void z80_get_bus(void);
+void z80_request_bus(void);
 void z80_release_bus(void);
 void z80_memset(uint32_t addr, uint8_t data, int length);
 void z80_reset(level_t level);
@@ -23,10 +23,11 @@ int z80_stat_halt(void);
 
 typedef enum {fifo_in, fifo_out} fifo_t;
 
-void z80_fifo_init(void);
-int z80_fifo_is_not_empty(fifo_t f);
-int z80_fifo_is_not_full(fifo_t f);
-uint8_t z80_fifo_getc(fifo_t f);
-void z80_fifo_putc(fifo_t f, uint8_t val);
+void z80_memfifo_init(void);
+int z80_memfifo_is_empty(fifo_t f);
+int z80_memfifo_is_full(fifo_t f);
+uint8_t z80_memfifo_getc(fifo_t f);
+void z80_memfifo_putc(fifo_t f, uint8_t val);
 
-int z80_inbuf_getc(void);
+void z80_setup_io_infifo(void);
+int z80_io_infifo_getc(void);