Add polling driver for ASCI0/1

6 files changed, 217 insertions, 24 deletions

diff --git a/z180/Tupfile b/z180/Tupfile
index 46aae4e..23855f8 100644
--- a/z180/Tupfile
+++ b/z180/Tupfile
@@ -4,8 +4,8 @@ PROG	= hdrom
 
 SRC 	= init.180
 SRC	+= ddtz.180
-#SRC	+= fifoio.180 msgbuf.180 asci1-i.180 console.180
-SRC	+= msgbuf-a.180 conbuf-a.180 asci1-i.180 bioscio.180 chario.180
+#SRC	+= fifoio.180 msgbuf.180 asci-p.180 console.180
+SRC	+= msgbuf-a.180 conbuf-a.180 asci-p.180 bioscio.180 chario.180
 # serial (asci1) console only:
 #SRC	+= asci1-i.180 console.180
 SRC	+= romend.180
diff --git a/z180/asci-p.180 b/z180/asci-p.180
new file mode 100644
index 0000000..956faf1
--- /dev/null
+++ b/z180/asci-p.180
@@ -0,0 +1,133 @@
+	page	200

+

+	extrn	ioiniml

+

+	global	as0init

+	global	as0ista,as0inp

+	global	as0osta,as0out

+	global	as1init

+	global	as1ista,as1inp

+	global	as1osta,as1out

+

+	include config.inc

+	include	z180reg.inc

+

+

+;-----------------------------------------------------

+;

+;

+; TC = (f PHI /(2*baudrate*Clock_mode)) - 2

+;

+; TC = (f PHI / (32 * baudrate)) - 2

+;

+

+	cseg

+;

+; Init Serial I/O for console input and output (ASCI1)

+;

+	

+

+

+as0init:

+	ld	hl,initab0

+	jp	ioiniml

+

+as1init:

+	ld	hl,initab1

+	jp	ioiniml

+

+		

+	ld	a,M_MPBT 

+	out0	(cntlb1),a

+	ld	a,M_RE + M_TE + M_MOD2	;Rx/Tx enable 

+	out0	(cntla1),a

+	ld	a,M_RIE

+	out0	(stat1),a	;Enable rx interrupts

+

+	ret			;

+

+

+initab0:

+	db	1,stat0,0		;Disable rx/tx interrupts

+					;Enable baud rate generator

+	db	1,asext0,M_BRGMOD+M_DCD0DIS+M_CTS0DIS

+	db	2,astc0l,low 28, high 28

+	db	1,cntlb0,M_MPBT		;No MP Mode, X16

+	db	1,cntla0,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1

+	db	0

+

+initab1:

+	db	1,stat1,0		;Disable rx/tx ints, disable CTS1

+	db	1,asext1,M_BRGMOD	;Enable baud rate generator

+	db	2,astc1l,low 3, high 3

+	db	1,cntlb1,M_MPBT		;No MP Mode, X16

+	db	1,cntla1,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1

+	db	0

+

+

+

+as0ista:

+	in0	a,(stat0)

+	and	M_RDRF

+	ret	z

+	or	0ffh

+	ret

+	

+as1ista:

+	in0	a,(stat1)

+	and	M_RDRF

+	ret	z

+	or	0ffh

+	ret

+	

+

+as0inp:

+	in0	a,(stat0)

+	rlca

+	jr	nc,as0inp

+	in0	a,rdr0

+	ret

+

+as1inp:

+	in0	a,(stat1)

+	rlca

+	jr	nc,as1inp

+	in0	a,rdr1

+	ret

+

+

+

+as0osta:

+	in0	a,(stat0)

+	and	M_TDRE

+	ret	z

+	or	0ffh

+	ret

+

+as1osta:

+	in0	a,(stat1)

+	and	M_TDRE

+	ret	z

+	or	0ffh

+	ret

+

+

+as0out:

+	in0	a,(stat0)

+	and	M_TDRE

+	jr	z,as0out

+	out0	(tdr0),c

+	ld	a,c

+	ret

+

+as1out:

+	in0	a,(stat1)

+	and	M_TDRE

+	jr	z,as1out

+	out0	(tdr1),c

+	ld	a,c

+	ret

+

+	end

+

+

diff --git a/z180/bioscio.180 b/z180/bioscio.180
index b0fd4da..2d8e5e0 100644
--- a/z180/bioscio.180
+++ b/z180/bioscio.180
@@ -66,7 +66,7 @@ c$init$loop:
 	jp	p,c$init$loop

 

 ;	ld	hl,1000000000000000b	; assign console to HOST

-	ld	hl,0100000000000000b	; assign console to ASCI1

+	ld	hl,0010000000000000b	; assign console to ASCI1

 	ld	(@civec),hl

 	ld	(@covec),hl

 	ld	hl,0000000000000000b	; assign auxiliary to nothing

diff --git a/z180/chario.180 b/z180/chario.180
index 6632690..8313658 100644
--- a/z180/chario.180
+++ b/z180/chario.180
@@ -8,14 +8,15 @@
 	public	@ctbl

 

 	extrn	ff.init,ff.i.st,ff.in,ff.o.st,ff.out

-	extrn	ser.init,ser.ist,ser.in,ser.ost,ser.out

+	extrn	as0init,as0ista,as0inp,as0osta,as0out

+	extrn	as1init,as1ista,as1inp,as1osta,as1out

 	

 	include config.inc

 	include	z180reg.inc

 	include modebaud.inc	; define mode bits and baud eqautes

 

 

-max$device	equ 2

+max$device	equ 3

 

 	cseg

 

@@ -25,7 +26,8 @@ max$device	equ 2
 	ld	b,c

 	call	vector$io

 	dw	ff.init

-	dw	ser.init

+	dw	as0init

+	dw	as1init

 	dw	rret

 

 ; b = device, c = output char, a = input char

@@ -33,25 +35,29 @@ max$device	equ 2
 ?ci:				; character input

 	call	vector$io

 	dw	ff.in

-	dw	ser.in

+	dw	as0inp

+	dw	as1inp

 	dw	null$input

 

 ?cist:				; character input status

 	call	vector$io

 	dw	ff.i.st

-	dw	ser.ist

+	dw	as0ista

+	dw	as1ista

 	dw	null$status

 

 ?co:				; character output

 	call	vector$io

 	dw	ff.out

-	dw	ser.out

+	dw	as0out

+	dw	as1out

 	dw	rret

 

 ?cost:				; character output status

 	call	vector$io

 	dw	ff.o.st

-	dw	ser.ost

+	dw	as0osta

+	dw	as1osta

 	dw	ret$true

 

 vector$io:

@@ -89,10 +95,15 @@ null$status:
 

 @ctbl:

 	db	'HOST  '	; device 0

-	db	mb$output

+	db	mb$in$out

 	db	baud$none

 

-	db	'ASCI1 '	; device 0

+	db	'ASCI1 '	; device 1

+	db	mb$in$out+mb$serial+mb$soft$baud

+ser0$baud:

+	db	baud$19200

+

+	db	'ASCI1 '	; device 2

 	db	mb$in$out+mb$serial+mb$soft$baud

 ser1$baud:

 	db	baud$19200

diff --git a/z180/init.180 b/z180/init.180
index 0bd37c1..39b03fc 100644
--- a/z180/init.180
+++ b/z180/init.180
@@ -5,7 +5,6 @@
 	extrn $stack

 	extrn charini,?const,?conin

 	extrn ?cono,?conos

-

 	extrn romend

 

 

@@ -75,14 +74,12 @@ start:
 

 hwini0:

     if CPU_Z180

-

 	db	3		;count

 	db	rcr,CREFSH	;configure DRAM refresh

 	db	dcntl,INIWAITS	;wait states

 	db	cbar,SYS$CBAR

-    else

-	db     0

     endif

+	db     0

 

     if CPU_Z180

 dmclrt:				;clear ram per dma

@@ -95,6 +92,7 @@ nullbyte:
 	db	00h		;dst

 	dw 	0-romend	;count (64k)

 dmct_e:

+	db	0

     endif

 

 

@@ -165,7 +163,7 @@ kstart:
      if 0

 	

 	ld	hl,dmclrt	;load DMA registers

-	call	io.ini.m

+	call	ioiniml

 	ld	a,0cbh		;01ef	dst +1, src fixed, burst

 	out0	(dmode),a	;01f1

 

@@ -434,7 +432,7 @@ prt0_init:
 	inc	hl

 	ld	(hl),high iprt0

 	ld	hl,prt0itab

-	call	io.ini.m

+	call	ioiniml

 	ret

 

 prt0itab:

@@ -444,6 +442,7 @@ prt0itab:
 	dw	PRT_TC10MS

 	db	M_TIE0+M_TDE0	;enable timer 0 interrupt and down count.

 prt0it_e:

+	db	0

     endif

 

 

@@ -451,24 +450,55 @@ prt0it_e:
 ;----------------------------------------------------------------------

 ;

 

+    if CPU_Z180

 io.ini:

+     if 0

 	push	bc

-    if CPU_Z180

-

 	ld	b,0		;high byte port adress

+ioi_nxt:

 	ld	a,(hl)		;count

 	inc	hl

 	or	a

 	jr	z,ioi_e

-ioi_1:

+

 	ld	c,(hl)		;port address

 	inc	hl

+ioi_r:

 	outi

 	inc	b		;outi decrements b

 	dec	a

-	jr	nz,ioi_1

+	jr	nz,ioi_r

+	jr	ioi_nxt

 ioi_e:	

+	pop	bc

+	ret

+	

+     else ;(if 1/0)

+     

+	push	bc

+	jr	ioi_nxt

+ioi_l:

+	ld	c,(hl)		;port address

+	inc	hl

+	inc	c

+ioi_r:

+	dec	c		;otim increments c

+	otim

+	jr	z,ioi_r

+ioi_nxt:

+	ld	b,(hl)		;count

+	inc	hl

+	inc	b		;stop if count == 0

+	djnz	ioi_l

+	pop	bc

+	ret

+	

+     endif ;(1/0)

+

     else

+

+io.ini:

+	push	bc

 	jr	ioi_nxt

 ioi_l:

 	ld	c,(hl)		;port address

@@ -483,16 +513,28 @@ ioi_nxt:
 	pop	bc

 	ret

 

+;----------------------------------------------------------------------

+

     if CPU_Z180

-io.ini.m:

+

+	global ioiniml

+

+ioiniml:

 	push	bc

+	xor	a

+ioml_lp:

 	ld	b,(hl)

 	inc	hl

+	cp	b

+	jr	z,ioml_e

+	

 	ld	c,(hl)

 	inc	hl

 	otimr

+	jr	ioml_lp

+ioml_e:

 	pop	bc

-	ret

+	ret	z

     endif

 

 io.ini.l:

diff --git a/z180/z180reg.inc b/z180/z180reg.inc
index 5bbd088..271a446 100644
--- a/z180/z180reg.inc
+++ b/z180/z180reg.inc
@@ -76,6 +76,13 @@ tcr	equ	IOBASE+10h	;Timer Control Register
 

 asext0	equ	IOBASE+12h	;ASCI Extension Control Register

 asext1	equ	IOBASE+13h	;ASCI Extension Control Register

+	b2m DCD0DIS,6		;DCD0 Disable

+	b2m CTS0DIS,5		;CTS0 Disable

+	b2m X1,4		;CKA * 1 Clock/Samle Rate Divider

+	b2m BRGMOD,3		;BRG Mode (Baud rate generator)

+	b2m BREAKEN,2		;Break Enable

+	b2m BREAK,1		;Break detected

+	b2m SENDBREAK,0		;Send Break

 

 tmdr1l	equ	IOBASE+14h	;Timer Data Register Channel 1

 tmdr1h	equ	IOBASE+15h	;