diff options
Diffstat (limited to 'z180/z180reg.inc')
| -rw-r--r-- | z180/z180reg.inc | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/z180/z180reg.inc b/z180/z180reg.inc index 5bbd088..2666867 100644 --- a/z180/z180reg.inc +++ b/z180/z180reg.inc @@ -24,7 +24,7 @@ cntla1 equ IOBASE+01h ;ASCI Control Register A Channel 1 b2m MPBR, 3 ;Multiprocessor Bit Receive (Read)
b2m EFR, 3 ;Error Flag Reset (Write)
b2m MOD2, 2 ;Data Format Mode 1 = 8-Bit data
- b2m NOD1, 1 ;1 = Parity enabled
+ b2m MOD1, 1 ;1 = Parity enabled
b2m MOD0, 0 ;1 = 2 stop bits
cntlb0 equ IOBASE+02h ;ASCI Control Register B Channel 0
@@ -76,6 +76,13 @@ tcr equ IOBASE+10h ;Timer Control Register asext0 equ IOBASE+12h ;ASCI Extension Control Register
asext1 equ IOBASE+13h ;ASCI Extension Control Register
+ b2m DCD0DIS,6 ;DCD0 Disable
+ b2m CTS0DIS,5 ;CTS0 Disable
+ b2m X1,4 ;CKA * 1 Clock/Samle Rate Divider
+ b2m BRGMOD,3 ;BRG Mode (Baud rate generator)
+ b2m BREAKEN,2 ;Break Enable
+ b2m BREAK,1 ;Break detected
+ b2m SENDBREAK,0 ;Send Break
tmdr1l equ IOBASE+14h ;Timer Data Register Channel 1
tmdr1h equ IOBASE+15h ;
@@ -123,8 +130,8 @@ bcr1h equ IOBASE+2Fh ; dstat equ IOBASE+30h ;DMA Status Register
b2m DE1,7 ;DMA enable ch 1,0
b2m DE0,6 ;
- b2m DWE1,5 ;DMA Enable Bit Write Enable 1,0
- b2m DWE0,4 ;
+ b2m NDWE1,5 ;DMA Enable Bit Write Enable 1,0
+ b2m NDWE0,4 ;
b2m DIE1,3 ;DMA Interrupt Enable 1,0
b2m DIE0,2 ;
b2m DME,0 ;DMA Master enable
@@ -188,4 +195,3 @@ IV$ASCI0 equ 14 ;ASCI channel 0 IV$ASCI1 equ 16 ;ASCI channel 1 (lowest priority)
.list
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