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|
FALSE equ 0
TRUE equ NOT FALSE
DEBUG equ true
banked equ true
;-----------------------------------------------------
; CPU and BANKING types
CPU_Z180 equ TRUE
CPU_Z80 equ FALSE
ROMSYS equ FALSE
AVRCLK equ 18432 ;[KHz]
if CPU_Z180
;-----------------------------------------------------
;FOSC equ AVRCLK/2 ;Oscillator frequency [KHz]
;PHI equ FOSC*2 ;CPU frequency (clock doubler enabled)
;----------------------------------------------------------------------
; Baudrate Generator for x16 clock mode:
; TC = (f PHI / (32 * baudrate)) - 2
;
; PHI [MHz]: 9.216 18.432
; baudrate TC TC
; ----------------------
; 115200 - 3
; 57600 3 8
; 38400 - 13
; 19200 13 28
; 9600 28 58
;-----------------------------------------------------
; Programmable Reload Timer (PRT)
PRT_PRE equ 20 ;PRT prescaler
;-----------------------------------------------------
; MMU
COMMON_SIZE equ 16*1024 ;Common Area size in bytes
;must be multiple of 4K
if (COMMON_SIZE mod 1000h)
.printx COMMON_SIZE not multiple of 4K!
end ;stop assembly
endif
CSK equ COMMON_SIZE/1000h ;
CA equ 10h - CSK ;common area start
BA equ 0 ;banked area start
SYS$CBR equ 0
SYS$CBAR equ CA*16 + CA ;CBAR in system mode
USR$CBAR equ CA*16 + BA ;CBAR in user mode (CP/M)
BANKS equ 18 ;max nr. of banks
;-----------------------------------------------------
CREFSH equ 0 ;Refresh rate register (disable refresh)
CWAITIO equ 3 shl IWI0 ;Max I/O Wait States, 0 Memory Wait States
PHI_X2 equ 0 ;set to M_X2CM to enable the clock doubler
endif ;CPU_Z180
if CPU_Z80
PHI equ AVRCLK/5 ;CPU frequency [KHz]
BAUDCLCK equ AVRCLK/10 ;Baudrate clock [KHz]
;BDCLK16 equ
SIOAD EQU 0bch
SIOAC EQU 0bdh
SIOBD EQU 0beh
SIOBC EQU 0bfh
CTC0 EQU 0f4h
CTC1 EQU 0f5h
CTC2 EQU 0f6h
CTC3 EQU 0f7h
;
; Init Serial I/O for console input and output (SIO-A)
;
; Baudrate clock: 1843200 Hz (Bus connector pin A17)
;
; Baudrate Divider SIO CTC
; ---------------------------------
; 115200 16 16 1
; 57600 32 16 2
; 38400 48 16 3
; 19200 96 16 6
; 9600 192 16 12
; 4800 384 16 24
; 2400 768 16 48
; 1200 1536 16 96
; 600 3072 16 192
; 300 6144 64 92
endif ; CPU_Z80
if ROMSYS
c$rom equ 0a5h
ROM_EN equ 0C0h
ROM_DIS equ ROMEN+1
if CPU_Z180
CWAITROM equ 2 shl MWI0
endif
endif
DDTZRSTVEC equ 030h ;DDTZ Restart vector (breakpoints)
INIDONE equ 03Fh ;CP/M skip hw init, if this address
INIDONEVAL equ 080h ; is set to this value.
mtx.fifo_len equ 64 ;Message transfer fifos
mtx.fifo_id equ 0 ; This *must* have #0
mrx.fifo_len equ 64
mrx.fifo_id equ 1
ci.fifo_len equ 32 ;AVRCON Character I/O via AVR
ci.fifo_id equ 2
co.fifo_len equ 32
co.fifo_id equ 3
s1.rx_len equ 128 ;Serial 1 (ASCI1) buffers
s1.rx_id equ 4 ;
s1.tx_len equ 128 ;
s1.tx_id equ 5 ;
AVRINT5 equ 4Fh
AVRINT6 equ 5Fh
;PMSG equ 80h
;-----------------------------------------------------
; Definition of (logical) top 2 memory pages
sysram_start equ 0FE00h
bs$stack$size equ 80
isvsw_loc equ 0FEE0h
ivtab equ 0ffc0h ;int vector table
iv2tab equ ivtab + 2*9
;-----------------------------------------------------
o.id equ -4
o.mask equ -3
o.in_idx equ -2
o.out_idx equ -1
.lall
mkbuf macro id,name,size
if ((size AND (size-1)) NE 0) OR (size GT 256)
.printx Error: buffer ^size must be power of 2 and in range 0..256!
name&.mask equ ;wrong size error
else
db id
db size-1
ds 2
name:: ds size
name&.mask equ low (size-1)
if size ne 0
name&.end equ $-1
name&.len equ size
name&.id equ id
endif
endif
endm
;-----------------------------------------------------
inidat macro
cseg
??ps.a defl $
endm
inidate macro
??ps.len defl $ - ??ps.a
dseg
ds ??ps.len
endm
;-----------------------------------------------------
b0call macro address
call _b0call
dw address
endm
|
