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.z80 ; for M80, ignored by SLR assembler
include z180reg.inc
RUN_TPA equ 0
UUNKNOWN equ 0 ;Unknown CPU
U8080 equ 1 ;8080
U8085 equ 2 ;8085
UZ80 equ 3 ;Z80
UX180 equ 4 ;HD64180 or higher
UHD64180 equ 5 ;HD64180
UZ80180 equ 6 ;Z80180
UZ8S180 equ 7 ;Z8S180, Z8L180
;-------------------------------------------------------------------------------
if RUN_TPA
base equ 0100h
else
base equ 0
endif
aseg
org base
jp start
done: db 0
result: db 0
cycls: db 0
wstates:db 0
;-------------------------------------------------------------------------------
cyctab:
db 0 ;Unknown CPU
db 20 ;8080
db 20 ;8085
db 21 ;Z80
db 19 ;HD64180 or higher
db 19 ;HD64180
db 19 ;Z80180
db 19 ;Z8S180, Z8L180
;-------------------------------------------------------------------------------
; Check if register C exists. D holds mask of bit to test.
; return z, if register exists
chk_reg:
in a,(c)
ld l,a
; check, if register is changeable
xor d ;
out (c),a
in a,(c) ; get it back
xor d
out (c),l ; set register to original state
cp l
ret
;-------------------------------------------------------------------------------
; Check CPU
;
;
; return:
; E = 0 Unknown
; E = 1 8080
; E = 2 8085
; E = 3 Z80
; E = 4 HD64180 or higher
; E = 5 HD64180
; E = 6 Z80180
; E = 7 Z8S180, Z8L180
;
;-------------------------------------------------------------------------------
; Registers only in Z180+, not in HD64180
; 3E OMCR
;
; Registers only in Z8S180/Z8L180
; 12 ASEXT0
; 13 ASEXT1
; 1A ASTC0L
; 1B ASTC0H
; 1C ASTC1L
; 1D ASTC1H
; 1E CMR
; 1F CCR
; 2D IAR1B
;
; Reserved registers
; 11
; 19
; 35
; 37
; 3B - 3D
check:
ld e,U8080 ; Init return val, assume 8080
xor a
dec a ; 00 --> 0FFH 8080/8085: even parity; Z80+: No overflow
jp po,chk_z80 ; Z80+ if P/V flag reset
; The 8085 logical AND instructions always set the auxiliary flag ON.
; The 8080 logical AND instructions set the flag to reflect the
; logical OR of bit 3 of the values involved in the AND operation.
; (8080/8085 ASSEMBLY LANGUAGE PROGRAMMING MANUAL, 1977, 1978)
xor a
and a ; 8085 sets, 8080 resets half carry.
daa ; A=06 (8085) or A=00 (8080)
ret z
inc e
ret
chk_z80:
ld e,UZ80 ; Assume Z80
daa ; Z80: 099H, x180+: 0F9H
cp 99h ; Result on 180 type cpus is F9 here. Thanks Hitachi
ret z
inc e ; x180
; At least Hitachi HD64180
; Test differences in certain internal registers
; to determine the 180 variant.
ld a,(wstates)
out0 (DCNTL),a
out0 (RCR),b ;
in0 a,(icr)
cp 01FH
jr z,icr_ok
;TODO: additional plausibility checks
ret ; I/O registers not found
; Register (base) found.
icr_ok:
inc e ; HD64180
ld c,omcr ; Check, if CPU has OMCR register
ld d,M_IOC ;
call chk_reg ;
ret nz ; Register does not exist. It's a HD64180
inc e ; Z80180
ld c,cmr ; Check, if CPU has CMR register
ld d,M_LNC ;
call chk_reg ;
ret nz ; register does not exist. It's a Z80180
inc e ; S180/L180 (class) detected.
ret
;-------------------------------------------------------------------------------
start:
ld sp,stack
ld hl,done
ld b,h
ld (hl),b
inc hl
ld (hl),b
call check
ld hl,cyctab
ld d,h
add hl,de
ld a,(hl)
ld hl,cycls
ld (hl),a
dec hl
ld (hl),e
dec hl
ld (hl),0ffH
out (040H),a
;808x Z80 Z180(0W) Z180(MaxW)
loop: ;---------------------------------
in a,(050h) ;10 11 10 +3*3 19
jp loop ;10 10 9 +3*3 18
;---------------------------------
;20 21 19 37
; jr loop ;-- 12 8 +2*3 14
rept 4
dw 0
endm
stack:
end
; vim:set ts=8 noet nowrap
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