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page 255
.z80
extrn ddtz,bpent
extrn $stack
extrn charini,?const,?conin
extrn ?cono,?conos
extrn romend
global iobyte
global isv_sw
include config.inc
;----------------------------------------------------------------------
cseg
romstart equ $
org romstart+0
jp start
iobyte: db 0
; restart vectors
rsti defl 1
rept 7
org 8*rsti + romstart
jp bpent
rsti defl rsti+1
endm
;----------------------------------------------------------------------
org romstart+40h
dw 0
db 0
cseg
if ROMSYS
$crom: defb c$rom ;
else
db 0 ;
endif
hwini0:
db 0 ;count
; db rcr,CREFSH ;configure DRAM refresh
; db dcntl,INIWAITS ;wait states
; db cbar,SYS$CBAR
;----------------------------------------------------------------------
org romstart+50h
start:
jp cstart
jp wstart
jp ?const
jp ?conin
jp ?cono
jp ?conos
jp charini
cstart:
di
xor a
ld (@cbnk),a
; search warm start mark
ld ix,mark_55AA ; top of common area
ld a,0aah ;
cp (ix+000h) ;
jr nz,kstart ;
cp (ix+002h) ;
jr nz,kstart ;
cpl ;
cp (ix+001h) ;
jr nz,kstart ;
cp (ix+003h) ;
jr nz,kstart ;
ld sp,$stack ; mark found, check
; call checkcrc_alv ;
jp z,wstart ; check ok,
;
; ram not ok, initialize -- kstart --
kstart:
ld sp,$stack ;01e1
; Clear RAM
; Init bank manager
;----------------------------------------------------------------------
;
ld hl,055AAh ;set warm start mark
ld (mark_55AA),hl ;
ld (mark_55AA+2),hl;
;
; -- wstart --
;
wstart:
call sysram_init ;027f
call ivtab_init
call charini
call bufferinit
ld c,0
call selbnk
im 2 ;?030e
ei ;0282
call ?const ;0284
call ?const ;0287
or a ;028a
call nz,?conin ;028d
;;; ld a,(banktab) ;
;;; ld e,a ;
jp ddtz ;0290
;----------------------------------------------------------------------
;
;TODO: Make a ringbuffer module.
global buf.init
buf.init:
ld (ix+o.in_idx),0
ld (ix+o.out_idx),0
ld (ix+o.mask),a
ret
;----------------------------------------------------------------------
extrn msginit,msg.sout
extrn mtx.fifo,mrx.fifo
extrn co.fifo,ci.fifo
bufferinit:
call msginit
ld hl,buffers
ld b,buftablen
bfi_1:
ld a,(hl)
inc hl
ld (bufdat+0),a
ld e,(hl)
inc hl
ld d,(hl)
inc hl
ex de,hl
or a
jr nz,bfi_2
ld a,(@cbnk)
call bnk2phys
ld (40h+0),hl
ld (40h+2),a
out (AVRINT5),a
jr bfi_3
bfi_2:
ld a,(@cbnk)
call bnk2phys
ld (bufdat+1),hl
ld (bufdat+3),a
ld hl,inimsg
call msg.sout
bfi_3:
ex de,hl
djnz bfi_1
ret
buffers:
db 0
dw mtx.fifo
db 1
dw mrx.fifo
db 2
dw co.fifo
db 3
dw ci.fifo
buftablen equ ($ - buffers)/3
inimsg:
db inimsg_e - $ -1
db 0AEh
db inimsg_e - $ -1
db 0
bufdat:
db 0
dw 0
db 0
inimsg_e:
;
;----------------------------------------------------------------------
;
bnk2phys:
sla h
jr nc,b2p_1 ;A15=1 --> common
ld a,3
b2p_1:
srl a
rr h
ret
;
;----------------------------------------------------------------------
;
sysram_init:
ld hl,sysramw
ld de,topcodsys
ld bc,sysrame-sysramw
ldir
ret
;----------------------------------------------------------------------
ivtab_init:
ld hl,ivtab ;
ld a,h ;
ld i,a ;
; out0 (il),l ;
; Let all vectors point to spurious int routines.
ld d,high sp.int0
ld a,low sp.int0
ld b,9
ivt_i1:
ld (hl),a
inc l
ld (hl),d
inc l
add a,sp.int.len
djnz ivt_i1
ret
;----------------------------------------------------------------------
;
global io.ini
io.ini:
push bc
if CPU_Z180
ld b,0 ;high byte port adress
ld a,(hl) ;count
inc hl
or a
jr z,ioi_e
ioi_1:
ld c,(hl) ;port address
inc hl
outi
inc b ;outi decrements b
dec a
jr nz,ioi_1
else
jr ioi_nxt
ioi_l:
ld c,(hl) ;port address
inc hl
otir
ioi_nxt:
ld b,(hl) ;count
inc hl
inc b
djnz ioi_l
endif
ioi_e:
pop bc
ret
if CPU_Z180
io.ini.m:
push bc
ld b,(hl)
inc hl
ld c,(hl)
inc hl
otimr
pop bc
ret
endif
io.ini.l:
;
;----------------------------------------------------------------------
;
;return:
; hl = hl + a
; Flags undefined
;
add_hl_a:
add a,l
ld l,a
ret nc
inc h
ret
; ---------------------------------------------------------
sysramw:
.phase isvsw_loc
topcodsys:
; Trampoline for interrupt routines in banked ram.
; Switch stack pointer to "system" stack in top ram
; todo: z80 bank switch
isv_sw: ;
ex (sp),hl ; save hl, return adr in hl
push de ;
push af ;
ex de,hl ;
ld hl,0 ;
add hl,sp ;
ld a,h ;
cp 0f8h ;
jr nc,isw_1 ;
ld sp,$stack ;
isw_1:
push hl ;
; save current bank
; in0 h,(cbar) ;
push hl ;
; switch to system bank
; ld a,SYS$CBAR ;
; out0 (cbar),a ;
ex de,hl ;
ld e,(hl) ;
inc hl ;
ld d,(hl) ;
ex de,hl ;
push bc ;
call jphl ;
pop bc ;
pop hl ; restore bank
; out0 (cbar),h ;
pop hl ;
ld sp,hl ;
pop af ;
pop de ;
pop hl ;
ei ;
ret ;
jphl:
jp (hl) ;
; ---------------------------------------------------------
sp.int0:
ld a,0d0h
jr sp.i.1
sp.int.len equ $-sp.int0
ld a,0d1h
jr sp.i.1
ld a,0d2h
jr sp.i.1
ld a,0d3h
jr sp.i.1
ld a,0d4h
jr sp.i.1
ld a,0d5h
jr sp.i.1
ld a,0d6h
jr sp.i.1
ld a,0d7h
jr sp.i.1
ld a,0d8h
sp.i.1:
; out (80h),a
halt
; ---------------------------------------------------------
; Get IFF2
; This routine may not be loaded in page zero
;
; return Carry clear, if INTs are enabled.
;
global getiff
getiff:
xor a ;clear accu and carry
push af ;stack bottom := 00xxh
pop af
ld a,i ;P flag := IFF2
ret pe ;exit carry clear, if enabled
dec sp
dec sp ;has stack bottom been overwritten?
pop af
and a ;if not 00xxh, INTs were
ret nz ;actually enabled
scf ;Otherwise, they really are disabled
ret
;----------------------------------------------------------------------
global selbnk
; a: bank (0..2)
selbnk:
push bc
ld c,a
call getiff
push af
ld a,c
di
ld (@cbnk),a
ld a,5
out (SIOAC),a
ld a,(mm_sio0)
rla
srl c
rra
out (SIOAC),a
ld (mm_sio0),a
ld a,5
out (SIOBC),a
ld a,(mm_sio1)
rla
srl c
rra
out (SIOBC),a
ld (mm_sio1),a
pop af
pop bc
ret c ;INTs were disabled
ei
ret
;----------------------------------------------------------------------
; c: bank (0..2)
if 0
selbnk:
ld a,(@cbnk)
xor c
and 3
ret z ;no change
call getiff
push af
ld a,c
di
ld (@cbnk),a
ld a,5
out (SIOAC),a
ld a,(mm_sio0)
rla
srl c
rra
out (SIOAC),a
ld (mm_sio0),a
ld a,5
out (SIOBC),a
ld a,(mm_sio1)
rla
srl c
rra
out (SIOBC),a
ld (mm_sio1),a
pop af
ret nc ;INTs were disabled
ei
ret
endif
;----------------------------------------------------------------------
if 0
ex af,af'
push af
ex af,af'
rra
jr nc,stbk1
ex af,af'
ld a,5
out (SIOAC),a
ld a,(mm_sio0)
rla
srl c
rra
out (SIOAC),a
ld (mm_sio1),a
ex af,af'
stbk1:
rra
jr nc,stbk2
ex af,af'
ld a,5
out (SIOBC),a
ld a,(mm_sio1)
rla
srl c
rra
out (SIOBC),a
ld (mm_sio1),a
ex af,af'
stbk2:
endif
global @cbnk
global mm_sio0, mm_sio1
@cbnk: db 0 ; current bank (0..2)
mm_sio0:
ds 1
mm_sio1:
ds 1
;----------------------------------------------------------------------
curph defl $
.dephase
sysrame:
.phase curph
tim_ms: db 0
tim_s: dw 0
.dephase
;-----------------------------------------------------
cseg
;.phase 0ffc0h
;ivtab equ 0ffc0h ; 0ffc0h ;int vector table
;.dephase
;.phase 0fffch
mark_55AA equ 0fffch
;ds 4 ; 0fffch
;.dephase
end
|