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9c15f366 L |
1 | ; Configuration, hardware definition, ... |
2 | ; | |
3 | ; Copyright (C) 2010 Sprite_tm | |
4 | ; Copyright (C) 2010 Leo C. | |
5 | ; | |
6 | ; This file is part of avrcpm. | |
7 | ; | |
8 | ; avrcpm is free software: you can redistribute it and/or modify it | |
9 | ; under the terms of the GNU General Public License as published by | |
10 | ; the Free Software Foundation, either version 3 of the License, or | |
11 | ; (at your option) any later version. | |
12 | ; | |
13 | ; avrcpm is distributed in the hope that it will be useful, | |
14 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ; GNU General Public License for more details. | |
17 | ; | |
18 | ; You should have received a copy of the GNU General Public License | |
19 | ; along with avrcpm. If not, see <http://www.gnu.org/licenses/>. | |
20 | ; | |
21 | ; $Id$ | |
22 | ; | |
23 | ||
24 | ||
25 | #define VMAJOR 2 /* Version number */ | |
80e1fa71 | 26 | #define VMINOR 3 |
9c15f366 L |
27 | |
28 | #ifndef DRAM_8BIT | |
678fc0b0 | 29 | #define DRAM_8BIT 1 /* 1 = 8bit wide DRAM */ |
9c15f366 L |
30 | #endif |
31 | #ifndef F_CPU | |
32 | #define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */ | |
33 | #endif | |
34 | #ifndef BAUD | |
35 | #define BAUD 38400 /* console baud rate */ | |
36 | #endif | |
37 | ||
9c15f366 | 38 | #define K 1024 |
637689de | 39 | #define M 1024*K |
9c15f366 L |
40 | |
41 | ;#define RAMSIZE 256*K*4 /* 1 chip 256Kx4 */ | |
42 | #define RAMSIZE 4*M*4 * 2 /* 2 chips 4Mx4 */ | |
43 | ||
80e1fa71 L |
44 | #define EM_Z80 0 /* Emulate Z80 if true */ |
45 | ||
3f75a0d3 L |
46 | #ifndef FAT16_SUPPORT |
47 | #define FAT16_SUPPORT 1 /* Include Support for FAT16 Partitions */ | |
48 | #endif /* which may contain CP/M image files. */ | |
b741422e L |
49 | #define RAMDISKCNT 0 /* Number of RAM disks */ |
50 | #define RAMDISKNR 'I'-'A' /* Drive "letter" for first RAM disk */ | |
9c15f366 L |
51 | |
52 | #define PARTID 0x52 /* Partition table id */ | |
53 | /* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */ | |
54 | #define IPLADDR 0x2000 /* Bootloader load address */ | |
55 | ||
56 | #define DRAM_WAITSTATES 1 /* Number of additional clock cycles for dram read access */ | |
57 | #define REFR_RATE 64000 /* dram refresh rate in cycles/s. */ | |
58 | /* Most drams need 1/15.6µs. */ | |
59 | #define RXBUFSIZE 128 /* USART recieve buffer size. Must be power of 2 */ | |
60 | #define TXBUFSIZE 128 /* USART transmit buffer size. Must be power of 2 */ | |
61 | ||
62 | ||
80e1fa71 L |
63 | #if EM_Z80 |
64 | #define CPUSTR "Z80" | |
65 | #else | |
66 | #define CPUSTR "8080" | |
67 | #endif | |
9c15f366 | 68 | |
dd7aea8c L |
69 | .equ BOOTWAIT = 1 |
70 | .equ MEMTEST = 1 | |
71 | .equ MEMFILL = 1 | |
e832c81a L |
72 | .equ MMC_DEBUG = 0 /* Increase for more debugging */ |
73 | .equ FAT16_DEBUG = 0 | |
a5b2e36e | 74 | .equ FAT16_RWDEBUG = 0 |
b2017655 | 75 | .equ FAT16_DBG_FAT = 0 |
e832c81a L |
76 | .equ DISK_DEBUG = 0 /* Increase for more debugging */ |
77 | .equ HOSTRW_DEBUG = 0 | |
dd7aea8c L |
78 | .equ HEAP_DEBUG = 0 |
79 | .equ PORT_DEBUG = 0 | |
80 | .equ INS_DEBUG = 0 | |
e832c81a L |
81 | .equ STACK_DBG = 0 |
82 | .equ PRINT_PC = 0 | |
9c15f366 L |
83 | |
84 | #define MMC_SPI2X 1 /* 0 = SPI CLK/4, 1 = SPI CLK/2 */ | |
85 | ||
80e1fa71 | 86 | #define MEMFILL_VAL 0x76 /* Fill ram with HALT opcode. */ |
9c15f366 L |
87 | #define DBG_TRACE_BOTTOM 0x01 /* Page boundaries for INS_DEBUG and PRINT_PC */ |
88 | #define DBG_TRACE_TOP 0xdc /* Trace is off, below bottom page and above top page. */ | |
89 | ||
90 | ;----------------------------------------------------------------------- | |
91 | ; Port declarations | |
92 | ||
93 | #if DRAM_8BIT /* Implies software uart */ | |
94 | ||
95 | ;Port D | |
96 | .equ RAM_D0 = 0 | |
97 | .equ RAM_D1 = 1 | |
98 | .equ RAM_D2 = 2 | |
99 | .equ RAM_D3 = 3 | |
100 | .equ RAM_D4 = 4 | |
101 | .equ RAM_D5 = 5 | |
102 | .equ RAM_D6 = 6 | |
103 | .equ RAM_D7 = 7 | |
104 | .equ RAM_A0 = 0 | |
105 | .equ RAM_A1 = 1 | |
106 | .equ RAM_A2 = 2 | |
107 | .equ RAM_A3 = 3 | |
108 | .equ RAM_A4 = 4 | |
109 | .equ RAM_A5 = 5 | |
110 | .equ RAM_A6 = 6 | |
111 | .equ RAM_A7 = 7 | |
112 | ||
113 | ;Port B | |
114 | .equ MMC_MOSI = 3 | |
115 | .equ MMC_MISO = 4 | |
116 | .equ MMC_SCK = 5 | |
117 | .equ RAM_A8 = 3 | |
118 | .equ RAM_A9 = 4 | |
119 | .equ RAM_A10 = 5 | |
120 | ||
121 | .equ RXD = 0 | |
122 | .equ TXD = 1 | |
123 | .equ MMC_CS = 2 | |
124 | ||
125 | .equ P_MMC_CS = PORTB | |
126 | .equ P_A8 = PORTB | |
127 | .equ P_RXD = PORTB | |
128 | ||
129 | ;Port C | |
130 | .equ RAM_RAS = 0 | |
131 | .equ RAM_CAS = 1 | |
132 | .equ RAM_OE = 2 | |
133 | .equ RAM_W = 3 | |
134 | ||
135 | .equ P_RAS = PORTC | |
136 | .equ P_CAS = PORTC | |
137 | .equ P_OE = PORTC | |
138 | .equ P_W = PORTC | |
139 | ||
140 | ||
141 | #else /* 4 bit RAM, hardware uart */ | |
142 | ||
143 | ; Port D | |
144 | .equ RXD = 0 | |
145 | .equ TXD = 1 | |
146 | .equ RAM_OE = 2 | |
147 | .equ RAM_A8 = 3 | |
148 | .equ MMC_CS = 4 | |
149 | .equ RAM_A5 = 5 | |
150 | .equ RAM_A6 = 6 | |
151 | .equ RAM_A7 = 7 | |
152 | ||
153 | .equ P_RXD = PORTD | |
154 | .equ P_OE = PORTD | |
155 | .equ P_A8 = PORTD | |
156 | .equ P_MMC_CS = PORTD | |
157 | .equ P_AH = PORTD | |
158 | ; RAM_A[7..5] | |
159 | .equ RAM_AH_MASK = (1<<RAM_A8)|(1<<RAM_A7)|(1<<RAM_A6)|(1<<RAM_A5) | |
160 | .equ PD_OUTPUT_MASK = (1<<MMC_CS) | (1<<RAM_OE) | RAM_AH_MASK | |
161 | ||
162 | ||
163 | ;Port B | |
164 | .equ RAM_A4 = 0 | |
165 | .equ RAM_A3 = 1 | |
166 | .equ RAM_A2 = 2 | |
167 | .equ RAM_A1 = 3 | |
168 | .equ MMC_MOSI = 3 | |
169 | .equ RAM_A0 = 4 | |
170 | .equ MMC_MISO = 4 | |
171 | .equ RAM_RAS = 5 | |
172 | .equ MMC_SCK = 5 | |
173 | ||
174 | .equ P_RAS = PORTB | |
175 | .equ P_AL = PORTB | |
176 | ; RAM_A[4..0] | |
177 | .equ RAM_AL_MASK = (1<<RAM_A4)|(1<<RAM_A3)|(1<<RAM_A2)|(1<<RAM_A1)|(1<<RAM_A0) | |
178 | .equ PB_OUTPUT_MASK = (1<<RAM_ras) | RAM_AL_MASK | |
179 | ||
180 | ;Port C | |
181 | .equ RAM_D0 = 0 | |
182 | .equ RAM_D1 = 1 | |
183 | .equ RAM_D2 = 2 | |
184 | .equ RAM_D3 = 3 | |
185 | .equ RAM_W = 4 | |
186 | .equ RAM_CAS = 5 | |
187 | ||
188 | .equ P_DQ = PORTC | |
189 | .equ P_W = PORTC | |
190 | .equ P_CAS = PORTC | |
191 | ||
192 | .equ RAM_DQ_MASK = (1<<RAM_D3)|(1<<RAM_D2)|(1<<RAM_D1)|(1<<RAM_D0) | |
193 | .equ PC_OUTPUT_MASK = (1<<RAM_CAS)|(1<<RAM_W) | |
194 | ||
195 | #endif /* DRAM_8BIT */ | |
196 | ||
197 | ||
198 | ;----------------------------------------------------------------------- | |
199 | ;Register definitions | |
200 | ||
201 | .def _tmp0 = r0 | |
202 | .def _tmp1 = r1 | |
203 | ||
204 | .def _RAS0 = r2 | |
205 | .def _CAS0 = r3 | |
206 | .def _OE = r4 | |
207 | .def _WE = r5 | |
208 | .def _255 = r6 | |
209 | .def _0 = r7 | |
210 | .def z_a = r9 | |
211 | ;.def stx_bitcount = r9 | |
212 | ;.def stx_dr = r10 | |
fa9059af | 213 | |
9c15f366 L |
214 | .def srx_lastedgel = r10 |
215 | .def srx_lastedgeh = r11 | |
fa9059af | 216 | ;.def insstore= r8 ; |
9c15f366 | 217 | ;.def insop = r13 ; |
fa9059af | 218 | |
9c15f366 L |
219 | .def insdecl = r12 ; |
220 | .def insdech = r13 ; | |
221 | .def z_spl = r14 | |
222 | .def z_sph = r15 ; | |
223 | .def temp = r16 ; | |
224 | .def temp2 = r17 ; | |
225 | .def temp3 = r18 | |
226 | .def temp4 = r19 | |
227 | .def z_flags = r20 ; | |
fa9059af | 228 | .def intstat = r21 ; interpreter status / interrupt status |
9c15f366 L |
229 | .def opl = r22 ; |
230 | .def oph = r23 ; | |
231 | .def z_pcl = r24 ; | |
232 | .def z_pch = r25 ; | |
233 | ; xl ;r26 | |
234 | ; xh ;r27 | |
235 | ; yl ;r28 | |
236 | ; yh ;r29 | |
237 | ; zl ;r30 ; | |
238 | ; zh ;r31 ; | |
239 | ||
240 | ||
fa9059af | 241 | .equ i_break = 0 ;break detected flag |
80e1fa71 L |
242 | .equ i_trace = 1 ;cpu interpreter trace flag |
243 | .equ i_halt = 2 ;executing halt instruction | |
9c15f366 L |
244 | |
245 | #if defined __ATmega8__ | |
246 | .equ flags = TWBR | |
247 | .equ P_PUD = SFIOR | |
248 | #else | |
249 | .equ flags = GPIOR0 | |
250 | .equ P_PUD = MCUCR | |
251 | #endif | |
252 | ||
253 | ; Flags: | |
254 | .equ hostact = 7 ;host active flag | |
255 | .equ hostwrt = 6 ;host written flag | |
256 | .equ rsflag = 5 ;read sector flag | |
257 | .equ readop = 4 ;1 if read operation | |
80e1fa71 L |
258 | |
259 | .equ prefixfd = 1 ;Opcode prefix DD=0, FD=1 | |
260 | .equ trace = 0 | |
9c15f366 L |
261 | |
262 | ; This is the base z80 port address for clock access | |
263 | #define TIMERPORT 0x40 | |
264 | #define TIMER_CTL TIMERPORT | |
265 | #define TIMER_MSECS TIMERPORT+1 | |
266 | #define TIMER_SECS TIMER_MSECS+2 | |
267 | ||
268 | #define starttimercmd 1 | |
269 | #define quitTimerCmd 2 | |
270 | #define printTimerCmd 15 | |
271 | #define uptimeCmd 16 | |
272 | ||
80e1fa71 L |
273 | #define DEBUGPORT 0x4F |
274 | ||
275 | #define startTraceCmd 1 | |
276 | #define stopTraceCmd 0 | |
277 | ||
278 | ||
9c15f366 L |
279 | #if defined __ATmega8__ |
280 | .equ RXTXDR0 = UDR | |
281 | .equ UCSR0A = UCSRA | |
282 | .equ UDRE0 = UDRE | |
283 | .equ UCSR0B = UCSRB | |
284 | .equ RXCIE0 = RXCIE | |
285 | .equ UDRIE0 = UDRIE | |
286 | .equ RXEN0 = RXEN | |
287 | .equ TXEN0 = TXEN | |
288 | .equ UCSR0C = UCSRC | |
289 | .equ UCSZ00 = UCSZ0 | |
290 | .equ UCSZ01 = UCSZ1 | |
291 | .equ UBRR0H = UBRRH | |
292 | .equ UBRR0L = UBRRL | |
293 | .equ OCR2A = OCR2 | |
294 | .equ OC2Aaddr= OC2addr | |
295 | .equ TCCR2A = TCCR2 | |
296 | .equ TCCR2B = TCCR2 | |
297 | .equ TIMSK1 = TIMSK | |
298 | .equ TIMSK2 = TIMSK | |
299 | .equ OCIE2A = OCIE2 | |
300 | .equ TIFR1 = TIFR | |
301 | .equ ICIE1 = TICIE1 | |
302 | #else | |
303 | .equ RXTXDR0 = UDR0 | |
304 | #endif | |
305 | ||
306 | ; vim:set ts=8 noet nowrap | |
307 | ||
308 |