]>
Commit | Line | Data |
---|---|---|
9c15f366 L |
1 | ; Configuration, hardware definition, ... |
2 | ; | |
3 | ; Copyright (C) 2010 Sprite_tm | |
2ccaac16 | 4 | ; Copyright (C) 2010,2012,2013 Leo C. |
9c15f366 L |
5 | ; |
6 | ; This file is part of avrcpm. | |
7 | ; | |
8 | ; avrcpm is free software: you can redistribute it and/or modify it | |
9 | ; under the terms of the GNU General Public License as published by | |
10 | ; the Free Software Foundation, either version 3 of the License, or | |
11 | ; (at your option) any later version. | |
12 | ; | |
13 | ; avrcpm is distributed in the hope that it will be useful, | |
14 | ; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ; GNU General Public License for more details. | |
17 | ; | |
18 | ; You should have received a copy of the GNU General Public License | |
19 | ; along with avrcpm. If not, see <http://www.gnu.org/licenses/>. | |
20 | ; | |
21 | ; $Id$ | |
9c15f366 L |
22 | |
23 | ||
db81b524 | 24 | #define VMAJOR 3 /* Version number */ |
825ecc9d | 25 | #define VMINOR 2 |
9c15f366 | 26 | |
5c8bb361 L |
27 | ;----------------------------------------------------------------------- |
28 | ; | |
29 | ; Hardware and feature configuration | |
30 | ; | |
9c15f366 | 31 | |
5c8bb361 L |
32 | ; Supported MCUs are: atmega328P atmega168 atmega88 atmega8 |
33 | ; Z80 emulation currently needs atmega328P, so this is the default. | |
2ccaac16 | 34 | ;#define atmega328p |
80e1fa71 | 35 | |
5c8bb361 L |
36 | ; MCU frequency in Hz. |
37 | ;#define F_CPU 20000000 | |
9c15f366 | 38 | |
5c8bb361 L |
39 | ; Set this to 0, if you have a (one) DRAM chip whith 4 Bit data bus. |
40 | ;#define DRAM_8BIT 1 | |
9c15f366 | 41 | |
5c8bb361 L |
42 | ; Baudrate of serial port (console). |
43 | ;#define BAUD 115200 | |
9c15f366 | 44 | |
825ecc9d | 45 | ; I2C_SUPPORT defaults to 1 on 8-bit-ram systems and must be 0 on 4-bit-ram systems. |
5c8bb361 L |
46 | ; Set this do 0, if you don't have I2C peripherals and want to save some flash |
47 | ; or use the I2C pins for other purposes. | |
825ecc9d | 48 | ;#define I2C_SUPPORT |
5c8bb361 L |
49 | |
50 | ; Emulate Z80 cpu if 1, 8080 otherwise. | |
51 | ; | |
52 | ;#define EM_Z80 1 | |
53 | ||
54 | ; Uncomment and set RAMDISKCOUNT to 1-4 if you want to test the experimental and | |
55 | ; unsupported ramdisk feature . Number depends on actual ram size (256kx4 - 4Mx8) | |
56 | ; and bios dpb/dph definitions. | |
57 | ;#define RAMDISKCNT 0 | |
58 | ||
59 | ; Uncomment and set to 0, if you need to save flash (ie. ATmega88). | |
60 | ;#define FAT16_SUPPORT 1 | |
61 | ||
ce520bff L |
62 | ; Uncomment and set to 0, if you don't want to use CP/M partitions. |
63 | ; (Saves some bytes.) | |
64 | ;#define CPMDSK_SUPPORT 1 | |
65 | ||
5c8bb361 L |
66 | ; Uncomment and set to 0, if you need to save flash. |
67 | ;#define MMCBOOTLOADER 1 | |
9c15f366 | 68 | |
2ccaac16 L |
69 | ; Uncomment to disable ADC support |
70 | ;#define ADC_SUPPORT 0 | |
9c15f366 | 71 | |
5c8bb361 L |
72 | ;----------------------------------------------------------------------- |
73 | ;Debugging aids | |
74 | ||
dd7aea8c L |
75 | .equ BOOTWAIT = 1 |
76 | .equ MEMTEST = 1 | |
98979541 L |
77 | .equ MEMFILL = 1 /* Fill DRAM */ |
78 | .equ SRAM_FILL = 1 /* Fill unused SRAM */ | |
e832c81a | 79 | .equ MMC_DEBUG = 0 /* Increase for more debugging */ |
02d57479 | 80 | .equ MMC_DEBUG_RDW = 0 |
2ccaac16 L |
81 | .equ DSKSEL_DEBUG = 0 |
82 | .equ DISK_DEBUG = 0 /* 1 = BOOT/HOME debug, 2 = +R/W debug */ | |
83 | .equ HOSTRW_DEBUG = 0 | |
e832c81a | 84 | .equ FAT16_DEBUG = 0 |
b2017655 | 85 | .equ FAT16_DBG_FAT = 0 |
dd7aea8c L |
86 | .equ HEAP_DEBUG = 0 |
87 | .equ PORT_DEBUG = 0 | |
88 | .equ INS_DEBUG = 0 | |
e832c81a L |
89 | .equ STACK_DBG = 0 |
90 | .equ PRINT_PC = 0 | |
de15c768 | 91 | .equ TIMER_DEBUG = 0 |
9c15f366 | 92 | |
5c8bb361 L |
93 | ;----------------------------------------------------------------------- |
94 | ; Z80/8080 Virtual Ports | |
95 | ||
2ccaac16 L |
96 | #define READ_FUNC 7 |
97 | #define WRITE_FUNC 6 | |
98 | #define BOOT_FUNC 5 | |
99 | #define HOME_FUNC 4 | |
100 | ||
5c8bb361 L |
101 | #define TIMERPORT 0x40 /* Base z80 port address for clock access */ |
102 | #define TIMER_CTL TIMERPORT | |
103 | #define TIMER_MSECS TIMERPORT+1 | |
104 | #define TIMER_SECS TIMER_MSECS+2 | |
105 | #define CLOCKPORT TIMERPORT+7 /* Real time clock BCD (ss,mm,hh,DD,MM,YYYY) */ | |
106 | ||
107 | #define starttimercmd 1 | |
108 | #define quitTimerCmd 2 | |
109 | #define printTimerCmd 15 | |
110 | #define uptimeCmd 16 | |
111 | ||
112 | #define DEBUGPORT 0x4F | |
113 | ||
98979541 L |
114 | #define startTraceCmd 0x01 /* 'OUT (DEBUGPORT),startTraceCmd' starts tracing */ |
115 | #define stopTraceCmd 0x00 | |
116 | #define PrintStackCmd 0x02 | |
5c8bb361 L |
117 | |
118 | ; Virtual I2C Interface | |
119 | #define I2CSTAT 0x05 | |
120 | #define I2CCTRL 0x05 | |
121 | #define I2CBLEN 0x06 | |
122 | #define I2CADR 0x07 | |
123 | #define I2CADRL 0x07 | |
124 | #define I2CADRH 0x08 | |
125 | ||
825ecc9d | 126 | ; Simple ADC Interface |
2ccaac16 L |
127 | #define ADC80 0x17 /* Read Value from ADC6 Pin, 8 bit */ |
128 | #define ADC81 0x18 /* Read Value from ADC7 Pin, 8 bit */ | |
129 | #define ADCTEMP 0x19 /* Read Value from Temp Sensor, 8 bit */ | |
130 | #define ADCBGL 0x20 /* Read 1.1V Bandgap, 10 bit */ | |
131 | #define ADCBGH 0x21 /* Read 1.1V Bandgap, 10 bit */ | |
132 | ||
825ecc9d | 133 | |
5c8bb361 L |
134 | ; Port-Expander PCF8574 |
135 | #define PORT 0x80 | |
136 | #define PORT0 0x80 | |
137 | #define PORT1 0x81 | |
138 | #define PORT2 0x82 | |
139 | #define PORT3 0x83 | |
140 | #define PORT4 0x84 | |
141 | #define PORT5 0x85 | |
142 | #define PORT6 0x86 | |
143 | #define PORT7 0x87 | |
144 | ||
145 | ;----------------------------------------------------------------------- | |
146 | ; | |
147 | ||
148 | #define PARTID 0x52 /* Partition table id */ | |
149 | /* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */ | |
150 | #define IPLADDR 0x2000 /* Bootloader load address */ | |
151 | ||
152 | #define DRAM_WAITSTATES 1 /* Number of additional clock cycles for dram read access */ | |
153 | #define REFR_RATE 64000 /* dram refresh rate in cycles/s. */ | |
154 | /* Most drams need 1/15.6µs. */ | |
155 | #define RXBUFSIZE 128 /* USART recieve buffer size. Must be power of 2 */ | |
156 | #define TXBUFSIZE 32 /* USART transmit buffer size. Must be power of 2 */ | |
157 | ||
158 | #define I2C_CLOCK 100000 /* 100kHz */ | |
159 | #define I2C_BUFSIZE 17 /* largest message size including address byte (SLA) */ | |
160 | ||
161 | ||
9c15f366 L |
162 | #define MMC_SPI2X 1 /* 0 = SPI CLK/4, 1 = SPI CLK/2 */ |
163 | ||
80e1fa71 | 164 | #define MEMFILL_VAL 0x76 /* Fill ram with HALT opcode. */ |
9c15f366 L |
165 | #define DBG_TRACE_BOTTOM 0x01 /* Page boundaries for INS_DEBUG and PRINT_PC */ |
166 | #define DBG_TRACE_TOP 0xdc /* Trace is off, below bottom page and above top page. */ | |
98979541 | 167 | #define SRAMFILL_VAL 0x5A /* Fill unused SRAM */ |
9c15f366 | 168 | |
5c8bb361 L |
169 | #ifndef DRAM_8BIT |
170 | #define DRAM_8BIT 1 /* 1 = 8bit wide data bus to DRAM (ie two 4-bit Chips)*/ | |
171 | #endif /* 0 = only one 4 bit wide DRAM chip */ | |
172 | #ifndef F_CPU | |
173 | #define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */ | |
174 | #endif | |
175 | #ifndef BAUD | |
176 | #define BAUD 115200 /* console baud rate */ | |
177 | #endif | |
825ecc9d L |
178 | #ifndef I2C_SUPPORT |
179 | #define I2C_SUPPORT DRAM_8BIT /* I2C requires 8 bit DRAM */ | |
180 | #endif | |
181 | #if I2C_SUPPORT && !DRAM_8BIT | |
182 | #error "I2C_SUPPORT requires 8 bit DRAM (DRAM_8BIT=1)!" | |
5c8bb361 | 183 | #endif |
825ecc9d | 184 | #ifndef ADC_SUPPORT |
2ccaac16 | 185 | #define ADC_SUPPORT 1 |
5c8bb361 L |
186 | #endif |
187 | ||
188 | #ifndef EM_Z80 | |
189 | #define EM_Z80 1 /* Emulate Z80 if true, else 8080 */ | |
190 | #endif | |
2ccaac16 | 191 | |
ce520bff L |
192 | #ifndef CPMDSK_SUPPORT |
193 | #define CPMDSK_SUPPORT 1 /* Include Support for CP/M partitions */ | |
194 | #endif | |
195 | ||
5c8bb361 | 196 | #ifndef FAT16_SUPPORT |
ce520bff L |
197 | #define FAT16_SUPPORT 1 /* Include Support for a FAT16 partition */ |
198 | #endif /* which may contain CP/M image files. */ | |
2ccaac16 | 199 | |
5c8bb361 L |
200 | #ifndef RAMDISKCNT |
201 | #define RAMDISKCNT 0 /* Number of RAM disks */ | |
202 | #endif | |
203 | #define RAMDISKNR 'I'-'A' /* Drive "letter" for first RAM disk */ | |
204 | ||
205 | /* MMC/SD Bootloader support. */ | |
206 | #define BOOTLDRSIZE 2048 /* Bytes needed for Bootloader (1024 Words Bootsection Size) */ | |
207 | #define DEVID_S "ACPM" | |
208 | #ifndef MMCBOOTLOADER | |
209 | #define MMCBOOTLOADER 1 | |
210 | #endif | |
211 | #ifndef TESTVERSION | |
212 | #define TESTVERSION 0 | |
213 | #endif | |
214 | ||
9c15f366 L |
215 | ;----------------------------------------------------------------------- |
216 | ; Port declarations | |
217 | ||
218 | #if DRAM_8BIT /* Implies software uart */ | |
219 | ||
220 | ;Port D | |
221 | .equ RAM_D0 = 0 | |
222 | .equ RAM_D1 = 1 | |
223 | .equ RAM_D2 = 2 | |
224 | .equ RAM_D3 = 3 | |
225 | .equ RAM_D4 = 4 | |
226 | .equ RAM_D5 = 5 | |
227 | .equ RAM_D6 = 6 | |
228 | .equ RAM_D7 = 7 | |
229 | .equ RAM_A0 = 0 | |
230 | .equ RAM_A1 = 1 | |
231 | .equ RAM_A2 = 2 | |
232 | .equ RAM_A3 = 3 | |
233 | .equ RAM_A4 = 4 | |
234 | .equ RAM_A5 = 5 | |
235 | .equ RAM_A6 = 6 | |
236 | .equ RAM_A7 = 7 | |
237 | ||
238 | ;Port B | |
239 | .equ MMC_MOSI = 3 | |
240 | .equ MMC_MISO = 4 | |
241 | .equ MMC_SCK = 5 | |
242 | .equ RAM_A8 = 3 | |
243 | .equ RAM_A9 = 4 | |
244 | .equ RAM_A10 = 5 | |
245 | ||
246 | .equ RXD = 0 | |
247 | .equ TXD = 1 | |
248 | .equ MMC_CS = 2 | |
249 | ||
250 | .equ P_MMC_CS = PORTB | |
251 | .equ P_A8 = PORTB | |
252 | .equ P_RXD = PORTB | |
79986122 | 253 | .equ P_TXD = PORTB |
9c15f366 L |
254 | |
255 | ;Port C | |
256 | .equ RAM_RAS = 0 | |
257 | .equ RAM_CAS = 1 | |
258 | .equ RAM_OE = 2 | |
259 | .equ RAM_W = 3 | |
260 | ||
261 | .equ P_RAS = PORTC | |
262 | .equ P_CAS = PORTC | |
263 | .equ P_OE = PORTC | |
264 | .equ P_W = PORTC | |
265 | ||
266 | ||
267 | #else /* 4 bit RAM, hardware uart */ | |
268 | ||
269 | ; Port D | |
270 | .equ RXD = 0 | |
271 | .equ TXD = 1 | |
272 | .equ RAM_OE = 2 | |
273 | .equ RAM_A8 = 3 | |
274 | .equ MMC_CS = 4 | |
275 | .equ RAM_A5 = 5 | |
276 | .equ RAM_A6 = 6 | |
277 | .equ RAM_A7 = 7 | |
278 | ||
279 | .equ P_RXD = PORTD | |
280 | .equ P_OE = PORTD | |
281 | .equ P_A8 = PORTD | |
282 | .equ P_MMC_CS = PORTD | |
283 | .equ P_AH = PORTD | |
284 | ; RAM_A[7..5] | |
285 | .equ RAM_AH_MASK = (1<<RAM_A8)|(1<<RAM_A7)|(1<<RAM_A6)|(1<<RAM_A5) | |
286 | .equ PD_OUTPUT_MASK = (1<<MMC_CS) | (1<<RAM_OE) | RAM_AH_MASK | |
287 | ||
288 | ||
289 | ;Port B | |
290 | .equ RAM_A4 = 0 | |
291 | .equ RAM_A3 = 1 | |
292 | .equ RAM_A2 = 2 | |
293 | .equ RAM_A1 = 3 | |
294 | .equ MMC_MOSI = 3 | |
295 | .equ RAM_A0 = 4 | |
296 | .equ MMC_MISO = 4 | |
297 | .equ RAM_RAS = 5 | |
298 | .equ MMC_SCK = 5 | |
299 | ||
300 | .equ P_RAS = PORTB | |
301 | .equ P_AL = PORTB | |
302 | ; RAM_A[4..0] | |
303 | .equ RAM_AL_MASK = (1<<RAM_A4)|(1<<RAM_A3)|(1<<RAM_A2)|(1<<RAM_A1)|(1<<RAM_A0) | |
304 | .equ PB_OUTPUT_MASK = (1<<RAM_ras) | RAM_AL_MASK | |
305 | ||
306 | ;Port C | |
307 | .equ RAM_D0 = 0 | |
308 | .equ RAM_D1 = 1 | |
309 | .equ RAM_D2 = 2 | |
310 | .equ RAM_D3 = 3 | |
311 | .equ RAM_W = 4 | |
312 | .equ RAM_CAS = 5 | |
313 | ||
314 | .equ P_DQ = PORTC | |
315 | .equ P_W = PORTC | |
316 | .equ P_CAS = PORTC | |
317 | ||
318 | .equ RAM_DQ_MASK = (1<<RAM_D3)|(1<<RAM_D2)|(1<<RAM_D1)|(1<<RAM_D0) | |
319 | .equ PC_OUTPUT_MASK = (1<<RAM_CAS)|(1<<RAM_W) | |
320 | ||
321 | #endif /* DRAM_8BIT */ | |
322 | ||
323 | ||
324 | ;----------------------------------------------------------------------- | |
325 | ;Register definitions | |
326 | ||
327 | .def _tmp0 = r0 | |
328 | .def _tmp1 = r1 | |
329 | ||
330 | .def _RAS0 = r2 | |
331 | .def _CAS0 = r3 | |
332 | .def _OE = r4 | |
333 | .def _WE = r5 | |
334 | .def _255 = r6 | |
335 | .def _0 = r7 | |
825ecc9d L |
336 | |
337 | .def z_c = r8 ; | |
338 | .def z_b = r9 ; | |
339 | .def z_e = r10 ; | |
340 | .def z_d = r11 ; | |
341 | .def z_l = r12 ; | |
342 | .def z_h = r13 ; | |
343 | .def z_spl = r14 ; | |
9c15f366 L |
344 | .def z_sph = r15 ; |
345 | .def temp = r16 ; | |
346 | .def temp2 = r17 ; | |
825ecc9d L |
347 | .def temp3 = r18 ; |
348 | ;.def temp4 = r19 ; | |
349 | .def intstat = r19 ;interpreter status / interrupt status | |
9c15f366 | 350 | .def z_flags = r20 ; |
825ecc9d | 351 | .def z_a = r21 ; |
9c15f366 L |
352 | .def opl = r22 ; |
353 | .def oph = r23 ; | |
354 | .def z_pcl = r24 ; | |
355 | .def z_pch = r25 ; | |
356 | ; xl ;r26 | |
357 | ; xh ;r27 | |
358 | ; yl ;r28 | |
359 | ; yh ;r29 | |
825ecc9d L |
360 | ; zl ;r30 |
361 | ; zh ;r31 | |
9c15f366 L |
362 | |
363 | ||
fa9059af | 364 | .equ i_break = 0 ;break detected flag |
80e1fa71 L |
365 | .equ i_trace = 1 ;cpu interpreter trace flag |
366 | .equ i_halt = 2 ;executing halt instruction | |
9c15f366 L |
367 | |
368 | #if defined __ATmega8__ | |
623dd899 L |
369 | #if DRAM_8BIT |
370 | ||
371 | .equ flags = UBRRL ;UART is unused with 8-Bit RAM | |
372 | #else | |
373 | .equ flags = TWBR ;TWI is unused with 4-Bit RAM | |
374 | #endif | |
375 | .equ P_PUD = SFIOR | |
376 | ||
377 | #else | |
378 | ||
379 | .equ flags = GPIOR0 | |
380 | .equ P_PUD = MCUCR | |
381 | ||
382 | #endif /* __ATmega8__ */ | |
9c15f366 L |
383 | |
384 | ; Flags: | |
385 | .equ hostact = 7 ;host active flag | |
386 | .equ hostwrt = 6 ;host written flag | |
387 | .equ rsflag = 5 ;read sector flag | |
388 | .equ readop = 4 ;1 if read operation | |
80e1fa71 L |
389 | |
390 | .equ prefixfd = 1 ;Opcode prefix DD=0, FD=1 | |
9c15f366 | 391 | |
80e1fa71 | 392 | |
79986122 L |
393 | #if EM_Z80 |
394 | #define CPUSTR "Z80" | |
395 | #else | |
396 | #define CPUSTR "8080" | |
397 | #endif | |
5c8bb361 L |
398 | #if TESTVERSION |
399 | #define TESTSTR "Test" | |
400 | #else | |
401 | #define TESTSTR "" | |
402 | #endif | |
79986122 | 403 | |
9c15f366 L |
404 | #if defined __ATmega8__ |
405 | .equ RXTXDR0 = UDR | |
406 | .equ UCSR0A = UCSRA | |
407 | .equ UDRE0 = UDRE | |
408 | .equ UCSR0B = UCSRB | |
409 | .equ RXCIE0 = RXCIE | |
410 | .equ UDRIE0 = UDRIE | |
411 | .equ RXEN0 = RXEN | |
412 | .equ TXEN0 = TXEN | |
413 | .equ UCSR0C = UCSRC | |
414 | .equ UCSZ00 = UCSZ0 | |
415 | .equ UCSZ01 = UCSZ1 | |
416 | .equ UBRR0H = UBRRH | |
417 | .equ UBRR0L = UBRRL | |
418 | .equ OCR2A = OCR2 | |
419 | .equ OC2Aaddr= OC2addr | |
420 | .equ TCCR2A = TCCR2 | |
421 | .equ TCCR2B = TCCR2 | |
422 | .equ TIMSK1 = TIMSK | |
423 | .equ TIMSK2 = TIMSK | |
424 | .equ OCIE2A = OCIE2 | |
425 | .equ TIFR1 = TIFR | |
426 | .equ ICIE1 = TICIE1 | |
427 | #else | |
428 | .equ RXTXDR0 = UDR0 | |
429 | #endif | |
430 | ||
431 | ; vim:set ts=8 noet nowrap | |
432 |