[avrcpm.git] / avr / config.inc

;    Configuration, hardware definition, ...
;    
;    Copyright (C) 2010 Sprite_tm
;    Copyright (C) 2010 Leo C.
;
;    This file is part of avrcpm.
;
;    avrcpm is free software: you can redistribute it and/or modify it
;    under the terms of the GNU General Public License as published by
;    the Free Software Foundation, either version 3 of the License, or
;    (at your option) any later version.
;
;    avrcpm is distributed in the hope that it will be useful,
;    but WITHOUT ANY WARRANTY; without even the implied warranty of
;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;    GNU General Public License for more details.
;
;    You should have received a copy of the GNU General Public License
;    along with avrcpm.  If not, see <http://www.gnu.org/licenses/>.
;
;    $Id$
;


#define VMAJOR 3		/* Version number */
#define VMINOR 1

#ifndef DRAM_8BIT
  #define DRAM_8BIT 1		/* 1 = 8bit wide DRAM */
#endif
#ifndef F_CPU
  #define F_CPU  20000000	/* system clock in Hz; defaults to 20MHz */
#endif
#ifndef BAUD
  #define BAUD   38400		/* console baud rate */
#endif
#ifndef I2C
    #define I2C  0		/* I2C requires 8 bit DRAM */
#endif
#if I2C && !DRAM_8BIT
  #error "I2C requires 8 bit DRAM (DRAM_8BIT=1)!"
#endif

#define EM_Z80	1		/* Emulate Z80 if true, else 8080 */

#ifndef FAT16_SUPPORT
  #define FAT16_SUPPORT 1	/* Include Support for FAT16 Partitions */
#endif				/*  which may contain CP/M image files. */ 
#define RAMDISKCNT    4		/* Number of RAM disks */
#define RAMDISKNR     'I'-'A'	/* Drive "letter" for first RAM disk */

#define PARTID 0x52		/* Partition table id */
				/* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */
#define IPLADDR	0x2000		/* Bootloader load address */

#define DRAM_WAITSTATES 1	/* Number of additional clock cycles for dram read access */
#define REFR_RATE   64000       /* dram refresh rate in cycles/s. */
				/* Most drams need 1/15.6µs. */
#define	RXBUFSIZE 128		/* USART recieve buffer size. Must be power of 2 */
#define	TXBUFSIZE 128		/* USART transmit buffer size. Must be power of 2 */

#define I2C_CLOCK  100000	/* 100kHz */
#define I2C_BUFSIZE    17 	/* largest message size including address byte (SLA) */


.equ BOOTWAIT      = 1
.equ MEMTEST       = 1
.equ MEMFILL       = 1
.equ MMC_DEBUG     = 0		/* Increase for more debugging */
.equ FAT16_DEBUG   = 0
.equ FAT16_RWDEBUG = 0
.equ FAT16_DBG_FAT = 0
.equ DISK_DEBUG    = 0		/* Increase for more debugging */
.equ HOSTRW_DEBUG  = 0
.equ HEAP_DEBUG	   = 0
.equ PORT_DEBUG    = 0
.equ INS_DEBUG     = 0
.equ STACK_DBG     = 0
.equ PRINT_PC      = 0
.equ TIMER_DEBUG   = 0

#define MMC_SPI2X  1		/* 0 = SPI CLK/4, 1 = SPI CLK/2 */

#define MEMFILL_VAL      0x76	/* Fill ram with HALT opcode. */
#define DBG_TRACE_BOTTOM 0x01	/* Page boundaries for INS_DEBUG and PRINT_PC  */
#define DBG_TRACE_TOP	 0xdc	/* Trace is off, below bottom page and above top page. */

#if EM_Z80
  #define CPUSTR "Z80"
#else
  #define CPUSTR "8080"
#endif

;-----------------------------------------------------------------------
; Port declarations

#if DRAM_8BIT	/* Implies software uart */

;Port D
.equ RAM_D0	= 0
.equ RAM_D1	= 1
.equ RAM_D2	= 2
.equ RAM_D3	= 3
.equ RAM_D4	= 4
.equ RAM_D5	= 5
.equ RAM_D6	= 6
.equ RAM_D7	= 7
.equ RAM_A0	= 0
.equ RAM_A1	= 1
.equ RAM_A2	= 2
.equ RAM_A3	= 3
.equ RAM_A4	= 4
.equ RAM_A5	= 5
.equ RAM_A6	= 6
.equ RAM_A7	= 7

;Port B
.equ MMC_MOSI	= 3
.equ MMC_MISO	= 4
.equ MMC_SCK	= 5
.equ RAM_A8	= 3
.equ RAM_A9	= 4
.equ RAM_A10	= 5

.equ RXD	= 0
.equ TXD	= 1
.equ MMC_CS	= 2

.equ P_MMC_CS	= PORTB
.equ P_A8	= PORTB
.equ P_RXD	= PORTB

;Port C
.equ RAM_RAS	= 0
.equ RAM_CAS	= 1
.equ RAM_OE	= 2
.equ RAM_W	= 3

.equ P_RAS	= PORTC
.equ P_CAS	= PORTC
.equ P_OE	= PORTC
.equ P_W	= PORTC


#else	/* 4 bit RAM, hardware uart */

; Port D
.equ RXD	= 0
.equ TXD	= 1
.equ RAM_OE	= 2
.equ RAM_A8	= 3
.equ MMC_CS	= 4
.equ RAM_A5	= 5
.equ RAM_A6	= 6
.equ RAM_A7	= 7

.equ P_RXD	= PORTD
.equ P_OE	= PORTD
.equ P_A8	= PORTD
.equ P_MMC_CS	= PORTD
.equ P_AH	= PORTD
	             ; RAM_A[7..5]
.equ RAM_AH_MASK = (1<<RAM_A8)|(1<<RAM_A7)|(1<<RAM_A6)|(1<<RAM_A5)
.equ PD_OUTPUT_MASK = (1<<MMC_CS) | (1<<RAM_OE) | RAM_AH_MASK


;Port B
.equ RAM_A4	= 0
.equ RAM_A3	= 1
.equ RAM_A2	= 2
.equ RAM_A1	= 3
.equ MMC_MOSI	= 3
.equ RAM_A0	= 4
.equ MMC_MISO	= 4
.equ RAM_RAS	= 5
.equ MMC_SCK	= 5

.equ P_RAS	= PORTB
.equ P_AL	= PORTB
			; RAM_A[4..0]
.equ RAM_AL_MASK = (1<<RAM_A4)|(1<<RAM_A3)|(1<<RAM_A2)|(1<<RAM_A1)|(1<<RAM_A0)
.equ PB_OUTPUT_MASK = (1<<RAM_ras) | RAM_AL_MASK

;Port C
.equ RAM_D0	= 0
.equ RAM_D1	= 1
.equ RAM_D2	= 2
.equ RAM_D3	= 3
.equ RAM_W	= 4
.equ RAM_CAS	= 5

.equ P_DQ	= PORTC
.equ P_W	= PORTC
.equ P_CAS	= PORTC

.equ RAM_DQ_MASK = (1<<RAM_D3)|(1<<RAM_D2)|(1<<RAM_D1)|(1<<RAM_D0)
.equ PC_OUTPUT_MASK = (1<<RAM_CAS)|(1<<RAM_W)

#endif	/* DRAM_8BIT */


;-----------------------------------------------------------------------
;Register definitions

.def	_tmp0	= r0
.def	_tmp1	= r1

.def	_RAS0	= r2
.def	_CAS0	= r3
.def	_OE	= r4
.def	_WE	= r5
.def	_255	= r6
.def	_0	= r7
.def	z_a	= r9
;.def	stx_bitcount  = r9
;.def	stx_dr	      = r10

.def	srx_lastedgel = r10
.def	srx_lastedgeh = r11
;.def	insstore= r8	;
;.def	insop	= r13	;

.def	insdecl	= r12	;
.def	insdech	= r13	;
.def	z_spl	= r14
.def	z_sph	= r15	;
.def	temp	= r16 	;
.def	temp2	= r17 	;
.def	temp3	= r18
.def	temp4	= r19
.def	z_flags	= r20	;
.def	intstat	= r21	; interpreter status / interrupt status
.def	opl	= r22	;
.def	oph	= r23	;
.def	z_pcl	= r24	;
.def	z_pch	= r25	;
; xl 		;r26
; xh		;r27
; yl		;r28
; yh		;r29
; zl		;r30	;
; zh		;r31	;


.equ	i_break = 0			;break detected flag
.equ	i_trace = 1			;cpu interpreter trace flag
.equ	i_halt  = 2			;executing halt instruction

#if defined __ATmega8__
.equ	flags	= TWBR
.equ	P_PUD	= SFIOR
#else
.equ	flags	= GPIOR0
.equ	P_PUD	= MCUCR
#endif

; Flags:
	.equ	hostact	= 7		;host active flag
	.equ	hostwrt	= 6		;host written flag
	.equ	rsflag	= 5		;read sector flag
	.equ	readop	= 4		;1 if read operation

	.equ	prefixfd = 1		;Opcode prefix DD=0, FD=1
	.equ	trace	 = 0

; This is the base z80 port address for clock access
#define	TIMERPORT   0x40
#define TIMER_CTL   TIMERPORT
#define TIMER_MSECS TIMERPORT+1
#define TIMER_SECS  TIMER_MSECS+2
#define	CLOCKPORT   TIMERPORT+7

#define starttimercmd	1
#define quitTimerCmd	2
#define printTimerCmd	15
#define uptimeCmd	16

#define DEBUGPORT   0x4F

#define startTraceCmd 1
#define stopTraceCmd  0

; Virtual I2C Interface
#define I2CSTAT	0x05
#define I2CCTRL	0x05
#define I2CBLEN	0x06
#define I2CADR	0x07
#define I2CADRL	0x07
#define I2CADRH	0x08

; Port-Expander PCF8574
#define PORT	0x80
#define PORT0	0x80
#define PORT1	0x81
#define PORT2	0x82
#define PORT3	0x83
#define PORT4	0x84
#define PORT5	0x85
#define PORT6	0x86
#define PORT7	0x87


#if defined __ATmega8__
.equ	RXTXDR0	= UDR
.equ	UCSR0A	= UCSRA
.equ	 UDRE0	= UDRE
.equ	UCSR0B	= UCSRB
.equ	 RXCIE0	= RXCIE
.equ	 UDRIE0	= UDRIE
.equ	 RXEN0	= RXEN
.equ	 TXEN0	= TXEN
.equ	UCSR0C	= UCSRC
.equ	 UCSZ00	= UCSZ0
.equ	 UCSZ01	= UCSZ1
.equ	UBRR0H	= UBRRH
.equ	UBRR0L	= UBRRL
.equ	OCR2A	= OCR2
.equ	OC2Aaddr= OC2addr
.equ	TCCR2A	= TCCR2
.equ	TCCR2B	= TCCR2
.equ	TIMSK1	= TIMSK
.equ	TIMSK2	= TIMSK
.equ	OCIE2A	= OCIE2
.equ	TIFR1	= TIFR
.equ	ICIE1	= TICIE1
#else
.equ	RXTXDR0	= UDR0
#endif

; vim:set ts=8 noet nowrap
Commit	Line	Data
9c15f366 L	1	; Configuration, hardware definition, ...
	2	;
	3	; Copyright (C) 2010 Sprite_tm
	4	; Copyright (C) 2010 Leo C.
	5	;
	6	; This file is part of avrcpm.
	7	;
	8	; avrcpm is free software: you can redistribute it and/or modify it
	9	; under the terms of the GNU General Public License as published by
	10	; the Free Software Foundation, either version 3 of the License, or
	11	; (at your option) any later version.
	12	;
	13	; avrcpm is distributed in the hope that it will be useful,
	14	; but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	; GNU General Public License for more details.
	17	;
	18	; You should have received a copy of the GNU General Public License
	19	; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
	20	;
	21	; $Id$
	22	;
	23
	24
db81b524	25	#define VMAJOR 3 /* Version number */
fb050095	26	#define VMINOR 1
9c15f366 L	27
9c15f366 L	28	#ifndef DRAM_8BIT
678fc0b0	29	#define DRAM_8BIT 1 /* 1 = 8bit wide DRAM */
9c15f366 L	30	#endif
	31	#ifndef F_CPU
	32	#define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */
	33	#endif
	34	#ifndef BAUD
	35	#define BAUD 38400 /* console baud rate */
	36	#endif
d8fa6a36	37	#ifndef I2C
de15c768	38	#define I2C 0 /* I2C requires 8 bit DRAM */
d8fa6a36 L	39	#endif
	40	#if I2C && !DRAM_8BIT
	41	#error "I2C requires 8 bit DRAM (DRAM_8BIT=1)!"
	42	#endif
9c15f366	43
d8fa6a36	44	#define EM_Z80 1 /* Emulate Z80 if true, else 8080 */
80e1fa71	45
3f75a0d3 L	46	#ifndef FAT16_SUPPORT
	47	#define FAT16_SUPPORT 1 /* Include Support for FAT16 Partitions */
	48	#endif /* which may contain CP/M image files. */
abeec861	49	#define RAMDISKCNT 4 /* Number of RAM disks */
b741422e	50	#define RAMDISKNR 'I'-'A' /* Drive "letter" for first RAM disk */
9c15f366 L	51
	52	#define PARTID 0x52 /* Partition table id */
	53	/* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */
	54	#define IPLADDR 0x2000 /* Bootloader load address */
	55
	56	#define DRAM_WAITSTATES 1 /* Number of additional clock cycles for dram read access */
	57	#define REFR_RATE 64000 /* dram refresh rate in cycles/s. */
	58	/* Most drams need 1/15.6µs. */
	59	#define RXBUFSIZE 128 /* USART recieve buffer size. Must be power of 2 */
	60	#define TXBUFSIZE 128 /* USART transmit buffer size. Must be power of 2 */
	61
d8fa6a36 L	62	#define I2C_CLOCK 100000 /* 100kHz */
d8fa6a36 L	63	#define I2C_BUFSIZE 17 /* largest message size including address byte (SLA) */
9c15f366	64
9c15f366	65
dd7aea8c L	66	.equ BOOTWAIT = 1
	67	.equ MEMTEST = 1
	68	.equ MEMFILL = 1
e832c81a L	69	.equ MMC_DEBUG = 0 /* Increase for more debugging */
e832c81a L	70	.equ FAT16_DEBUG = 0
a5b2e36e	71	.equ FAT16_RWDEBUG = 0
b2017655	72	.equ FAT16_DBG_FAT = 0
e832c81a L	73	.equ DISK_DEBUG = 0 /* Increase for more debugging */
e832c81a L	74	.equ HOSTRW_DEBUG = 0
dd7aea8c L	75	.equ HEAP_DEBUG = 0
	76	.equ PORT_DEBUG = 0
	77	.equ INS_DEBUG = 0
e832c81a L	78	.equ STACK_DBG = 0
e832c81a L	79	.equ PRINT_PC = 0
de15c768	80	.equ TIMER_DEBUG = 0
9c15f366 L	81
	82	#define MMC_SPI2X 1 /* 0 = SPI CLK/4, 1 = SPI CLK/2 */
	83
80e1fa71	84	#define MEMFILL_VAL 0x76 /* Fill ram with HALT opcode. */
9c15f366 L	85	#define DBG_TRACE_BOTTOM 0x01 /* Page boundaries for INS_DEBUG and PRINT_PC */
	86	#define DBG_TRACE_TOP 0xdc /* Trace is off, below bottom page and above top page. */
	87
d8fa6a36 L	88	#if EM_Z80
	89	#define CPUSTR "Z80"
	90	#else
	91	#define CPUSTR "8080"
	92	#endif
	93
9c15f366 L	94	;-----------------------------------------------------------------------
	95	; Port declarations
	96
	97	#if DRAM_8BIT /* Implies software uart */
	98
	99	;Port D
	100	.equ RAM_D0 = 0
	101	.equ RAM_D1 = 1
	102	.equ RAM_D2 = 2
	103	.equ RAM_D3 = 3
	104	.equ RAM_D4 = 4
	105	.equ RAM_D5 = 5
	106	.equ RAM_D6 = 6
	107	.equ RAM_D7 = 7
	108	.equ RAM_A0 = 0
	109	.equ RAM_A1 = 1
	110	.equ RAM_A2 = 2
	111	.equ RAM_A3 = 3
	112	.equ RAM_A4 = 4
	113	.equ RAM_A5 = 5
	114	.equ RAM_A6 = 6
	115	.equ RAM_A7 = 7
	116
	117	;Port B
	118	.equ MMC_MOSI = 3
	119	.equ MMC_MISO = 4
	120	.equ MMC_SCK = 5
	121	.equ RAM_A8 = 3
	122	.equ RAM_A9 = 4
	123	.equ RAM_A10 = 5
	124
	125	.equ RXD = 0
	126	.equ TXD = 1
	127	.equ MMC_CS = 2
	128
	129	.equ P_MMC_CS = PORTB
	130	.equ P_A8 = PORTB
	131	.equ P_RXD = PORTB
	132
	133	;Port C
	134	.equ RAM_RAS = 0
	135	.equ RAM_CAS = 1
	136	.equ RAM_OE = 2
	137	.equ RAM_W = 3
	138
	139	.equ P_RAS = PORTC
	140	.equ P_CAS = PORTC
	141	.equ P_OE = PORTC
	142	.equ P_W = PORTC
	143
	144
	145	#else /* 4 bit RAM, hardware uart */
	146
	147	; Port D
	148	.equ RXD = 0
	149	.equ TXD = 1
	150	.equ RAM_OE = 2
	151	.equ RAM_A8 = 3
	152	.equ MMC_CS = 4
	153	.equ RAM_A5 = 5
	154	.equ RAM_A6 = 6
	155	.equ RAM_A7 = 7
	156
	157	.equ P_RXD = PORTD
158	.equ P_OE = PORTD
159	.equ P_A8 = PORTD
160	.equ P_MMC_CS = PORTD
161	.equ P_AH = PORTD
162	; RAM_A[7..5]
163	.equ RAM_AH_MASK = (1<<RAM_A8)\|(1<<RAM_A7)\|(1<<RAM_A6)\|(1<<RAM_A5)
164	.equ PD_OUTPUT_MASK = (1<<MMC_CS) \| (1<<RAM_OE) \| RAM_AH_MASK
165
166
167	;Port B
168	.equ RAM_A4 = 0
169	.equ RAM_A3 = 1
170	.equ RAM_A2 = 2
171	.equ RAM_A1 = 3
172	.equ MMC_MOSI = 3
173	.equ RAM_A0 = 4
174	.equ MMC_MISO = 4
175	.equ RAM_RAS = 5
176	.equ MMC_SCK = 5
177
178	.equ P_RAS = PORTB
179	.equ P_AL = PORTB
180	; RAM_A[4..0]
181	.equ RAM_AL_MASK = (1<<RAM_A4)\|(1<<RAM_A3)\|(1<<RAM_A2)\|(1<<RAM_A1)\|(1<<RAM_A0)
182	.equ PB_OUTPUT_MASK = (1<<RAM_ras) \| RAM_AL_MASK
183
184	;Port C
185	.equ RAM_D0 = 0
186	.equ RAM_D1 = 1
187	.equ RAM_D2 = 2
188	.equ RAM_D3 = 3
189	.equ RAM_W = 4
190	.equ RAM_CAS = 5
191
192	.equ P_DQ = PORTC
193	.equ P_W = PORTC
194	.equ P_CAS = PORTC
195
196	.equ RAM_DQ_MASK = (1<<RAM_D3)\|(1<<RAM_D2)\|(1<<RAM_D1)\|(1<<RAM_D0)
197	.equ PC_OUTPUT_MASK = (1<<RAM_CAS)\|(1<<RAM_W)
198
199	#endif /* DRAM_8BIT */
200
201
202	;-----------------------------------------------------------------------
203	;Register definitions
204
205	.def _tmp0 = r0
206	.def _tmp1 = r1
207
208	.def _RAS0 = r2
209	.def _CAS0 = r3
210	.def _OE = r4
211	.def _WE = r5
212	.def _255 = r6
213	.def _0 = r7
214	.def z_a = r9
215	;.def stx_bitcount = r9
216	;.def stx_dr = r10
fa9059af	217
9c15f366 L	218	.def srx_lastedgel = r10
9c15f366 L	219	.def srx_lastedgeh = r11
fa9059af	220	;.def insstore= r8 ;
9c15f366	221	;.def insop = r13 ;
fa9059af	222
9c15f366 L	223	.def insdecl = r12 ;
	224	.def insdech = r13 ;
	225	.def z_spl = r14
	226	.def z_sph = r15 ;
	227	.def temp = r16 ;
	228	.def temp2 = r17 ;
	229	.def temp3 = r18
	230	.def temp4 = r19
	231	.def z_flags = r20 ;
fa9059af	232	.def intstat = r21 ; interpreter status / interrupt status
9c15f366 L	233	.def opl = r22 ;
	234	.def oph = r23 ;
	235	.def z_pcl = r24 ;
	236	.def z_pch = r25 ;
	237	; xl ;r26
	238	; xh ;r27
	239	; yl ;r28
	240	; yh ;r29
	241	; zl ;r30 ;
	242	; zh ;r31 ;
	243
	244
fa9059af	245	.equ i_break = 0 ;break detected flag
80e1fa71 L	246	.equ i_trace = 1 ;cpu interpreter trace flag
80e1fa71 L	247	.equ i_halt = 2 ;executing halt instruction
9c15f366 L	248
	249	#if defined __ATmega8__
	250	.equ flags = TWBR
	251	.equ P_PUD = SFIOR
	252	#else
	253	.equ flags = GPIOR0
	254	.equ P_PUD = MCUCR
	255	#endif
	256
	257	; Flags:
	258	.equ hostact = 7 ;host active flag
	259	.equ hostwrt = 6 ;host written flag
	260	.equ rsflag = 5 ;read sector flag
	261	.equ readop = 4 ;1 if read operation
80e1fa71 L	262
	263	.equ prefixfd = 1 ;Opcode prefix DD=0, FD=1
	264	.equ trace = 0
9c15f366 L	265
	266	; This is the base z80 port address for clock access
	267	#define TIMERPORT 0x40
	268	#define TIMER_CTL TIMERPORT
	269	#define TIMER_MSECS TIMERPORT+1
	270	#define TIMER_SECS TIMER_MSECS+2
fb050095	271	#define CLOCKPORT TIMERPORT+7
9c15f366 L	272
	273	#define starttimercmd 1
	274	#define quitTimerCmd 2
	275	#define printTimerCmd 15
	276	#define uptimeCmd 16
	277
80e1fa71 L	278	#define DEBUGPORT 0x4F
	279
	280	#define startTraceCmd 1
	281	#define stopTraceCmd 0
	282
d8fa6a36 L	283	; Virtual I2C Interface
	284	#define I2CSTAT 0x05
	285	#define I2CCTRL 0x05
	286	#define I2CBLEN 0x06
	287	#define I2CADR 0x07
	288	#define I2CADRL 0x07
	289	#define I2CADRH 0x08
	290
	291	; Port-Expander PCF8574
	292	#define PORT 0x80
	293	#define PORT0 0x80
	294	#define PORT1 0x81
	295	#define PORT2 0x82
	296	#define PORT3 0x83
	297	#define PORT4 0x84
	298	#define PORT5 0x85
	299	#define PORT6 0x86
	300	#define PORT7 0x87
	301
80e1fa71	302
9c15f366 L	303	#if defined __ATmega8__
	304	.equ RXTXDR0 = UDR
	305	.equ UCSR0A = UCSRA
	306	.equ UDRE0 = UDRE
	307	.equ UCSR0B = UCSRB
	308	.equ RXCIE0 = RXCIE
	309	.equ UDRIE0 = UDRIE
	310	.equ RXEN0 = RXEN
	311	.equ TXEN0 = TXEN
	312	.equ UCSR0C = UCSRC
	313	.equ UCSZ00 = UCSZ0
	314	.equ UCSZ01 = UCSZ1
	315	.equ UBRR0H = UBRRH
	316	.equ UBRR0L = UBRRL
	317	.equ OCR2A = OCR2
	318	.equ OC2Aaddr= OC2addr
	319	.equ TCCR2A = TCCR2
	320	.equ TCCR2B = TCCR2
	321	.equ TIMSK1 = TIMSK
	322	.equ TIMSK2 = TIMSK
	323	.equ OCIE2A = OCIE2
	324	.equ TIFR1 = TIFR
	325	.equ ICIE1 = TICIE1
	326	#else
	327	.equ RXTXDR0 = UDR0
	328	#endif
	329
	330	; vim:set ts=8 noet nowrap
	331