1 ; Configuration, hardware definition, ...
3 ; Copyright (C) 2010 Sprite_tm
4 ; Copyright (C) 2010 Leo C.
6 ; This file is part of avrcpm.
8 ; avrcpm is free software: you can redistribute it and/or modify it
9 ; under the terms of the GNU General Public License as published by
10 ; the Free Software Foundation, either version 3 of the License, or
11 ; (at your option) any later version.
13 ; avrcpm is distributed in the hope that it will be useful,
14 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ; GNU General Public License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
25 #define VMAJOR 3 /* Version number */
29 #define DRAM_8BIT 1 /* 1 = 8bit wide DRAM */
32 #define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */
35 #define BAUD 38400 /* console baud rate */
41 ;#define RAMSIZE 256*K*4 /* 1 chip 256Kx4 */
42 #define RAMSIZE 4*M*4 * 2 /* 2 chips 4Mx4 */
44 #define EM_Z80 1 /* Emulate Z80 if true */
47 #define FAT16_SUPPORT 1 /* Include Support for FAT16 Partitions */
48 #endif /* which may contain CP/M image files. */
49 #define RAMDISKCNT 4 /* Number of RAM disks */
50 #define RAMDISKNR 'I'-'A' /* Drive "letter" for first RAM disk */
52 #define PARTID 0x52 /* Partition table id */
53 /* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */
54 #define IPLADDR 0x2000 /* Bootloader load address */
56 #define DRAM_WAITSTATES 1 /* Number of additional clock cycles for dram read access */
57 #define REFR_RATE 64000 /* dram refresh rate in cycles/s. */
58 /* Most drams need 1/15.6µs. */
59 #define RXBUFSIZE 128 /* USART recieve buffer size. Must be power of 2 */
60 #define TXBUFSIZE 128 /* USART transmit buffer size. Must be power of 2 */
72 .equ MMC_DEBUG = 0 /* Increase for more debugging */
74 .equ FAT16_RWDEBUG = 0
75 .equ FAT16_DBG_FAT = 0
76 .equ DISK_DEBUG = 0 /* Increase for more debugging */
84 #define MMC_SPI2X 1 /* 0 = SPI CLK/4, 1 = SPI CLK/2 */
86 #define MEMFILL_VAL 0x76 /* Fill ram with HALT opcode. */
87 #define DBG_TRACE_BOTTOM 0x01 /* Page boundaries for INS_DEBUG and PRINT_PC */
88 #define DBG_TRACE_TOP 0xdc /* Trace is off, below bottom page and above top page. */
90 ;-----------------------------------------------------------------------
93 #if DRAM_8BIT /* Implies software uart */
125 .equ P_MMC_CS = PORTB
141 #else /* 4 bit RAM, hardware uart */
156 .equ P_MMC_CS = PORTD
159 .equ RAM_AH_MASK = (1<<RAM_A8)|(1<<RAM_A7)|(1<<RAM_A6)|(1<<RAM_A5)
160 .equ PD_OUTPUT_MASK = (1<<MMC_CS) | (1<<RAM_OE) | RAM_AH_MASK
177 .equ RAM_AL_MASK = (1<<RAM_A4)|(1<<RAM_A3)|(1<<RAM_A2)|(1<<RAM_A1)|(1<<RAM_A0)
178 .equ PB_OUTPUT_MASK = (1<<RAM_ras) | RAM_AL_MASK
192 .equ RAM_DQ_MASK = (1<<RAM_D3)|(1<<RAM_D2)|(1<<RAM_D1)|(1<<RAM_D0)
193 .equ PC_OUTPUT_MASK = (1<<RAM_CAS)|(1<<RAM_W)
195 #endif /* DRAM_8BIT */
198 ;-----------------------------------------------------------------------
199 ;Register definitions
211 ;.def stx_bitcount = r9
214 .def srx_lastedgel = r10
215 .def srx_lastedgeh = r11
228 .def intstat = r21 ; interpreter status / interrupt status
241 .equ i_break = 0 ;break detected flag
242 .equ i_trace = 1 ;cpu interpreter trace flag
243 .equ i_halt = 2 ;executing halt instruction
245 #if defined __ATmega8__
254 .equ hostact = 7 ;host active flag
255 .equ hostwrt = 6 ;host written flag
256 .equ rsflag = 5 ;read sector flag
257 .equ readop = 4 ;1 if read operation
259 .equ prefixfd = 1 ;Opcode prefix DD=0, FD=1
262 ; This is the base z80 port address for clock access
263 #define TIMERPORT 0x40
264 #define TIMER_CTL TIMERPORT
265 #define TIMER_MSECS TIMERPORT+1
266 #define TIMER_SECS TIMER_MSECS+2
267 #define CLOCKPORT TIMERPORT+7
269 #define starttimercmd 1
270 #define quitTimerCmd 2
271 #define printTimerCmd 15
274 #define DEBUGPORT 0x4F
276 #define startTraceCmd 1
277 #define stopTraceCmd 0
280 #if defined __ATmega8__
295 .equ OC2Aaddr= OC2addr
307 ; vim:set ts=8 noet nowrap