1 ; Configuration, hardware definition, ...
3 ; Copyright (C) 2010 Sprite_tm
4 ; Copyright (C) 2010 Leo C.
6 ; This file is part of avrcpm.
8 ; avrcpm is free software: you can redistribute it and/or modify it
9 ; under the terms of the GNU General Public License as published by
10 ; the Free Software Foundation, either version 3 of the License, or
11 ; (at your option) any later version.
13 ; avrcpm is distributed in the hope that it will be useful,
14 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ; GNU General Public License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
25 #define VMAJOR 2 /* Version number */
29 #define DRAM_8BIT 0 /* 1 = 8bit wide DRAM */
32 #define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */
35 #define BAUD 38400 /* console baud rate */
38 #define PARTID 0x52 /* Partition table id */
39 /* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */
43 ;#define RAMSIZE 256*K*4 /* 1 chip 256Kx4 */
44 #define RAMSIZE 4*M*4 * 2 /* 2 chips 4Mx4 */
46 #define RAMDISKCNT 0 /* Number of RAM disks */
47 #define RAMDISKNR 'I'-'A' /* Drive "letter" for first RAM disk */
49 #define PARTID 0x52 /* Partition table id */
50 /* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */
51 #define IPLADDR 0x2000 /* Bootloader load address */
53 #define DRAM_WAITSTATES 1 /* Number of additional clock cycles for dram read access */
54 #define REFR_RATE 64000 /* dram refresh rate in cycles/s. */
55 /* Most drams need 1/15.6µs. */
56 #define RXBUFSIZE 128 /* USART recieve buffer size. Must be power of 2 */
57 #define TXBUFSIZE 128 /* USART transmit buffer size. Must be power of 2 */
61 #define EM_Z80 0 /* we don't have any z80 instructions yet */
64 .equ MMC_DEBUG = 0 /* Increase for more debugging */
69 .equ DISK_DEBUG = 0 /* Increase for more debugging */
75 #define MMC_SPI2X 1 /* 0 = SPI CLK/4, 1 = SPI CLK/2 */
77 #define MEMFILL_VAL 0xCB /* Fill ram with cbs, which will trigger an invalid opcode error. */
78 #define DBG_TRACE_BOTTOM 0x01 /* Page boundaries for INS_DEBUG and PRINT_PC */
79 #define DBG_TRACE_TOP 0xdc /* Trace is off, below bottom page and above top page. */
81 ;-----------------------------------------------------------------------
84 #if DRAM_8BIT /* Implies software uart */
116 .equ P_MMC_CS = PORTB
132 #else /* 4 bit RAM, hardware uart */
147 .equ P_MMC_CS = PORTD
150 .equ RAM_AH_MASK = (1<<RAM_A8)|(1<<RAM_A7)|(1<<RAM_A6)|(1<<RAM_A5)
151 .equ PD_OUTPUT_MASK = (1<<MMC_CS) | (1<<RAM_OE) | RAM_AH_MASK
168 .equ RAM_AL_MASK = (1<<RAM_A4)|(1<<RAM_A3)|(1<<RAM_A2)|(1<<RAM_A1)|(1<<RAM_A0)
169 .equ PB_OUTPUT_MASK = (1<<RAM_ras) | RAM_AL_MASK
183 .equ RAM_DQ_MASK = (1<<RAM_D3)|(1<<RAM_D2)|(1<<RAM_D1)|(1<<RAM_D0)
184 .equ PC_OUTPUT_MASK = (1<<RAM_CAS)|(1<<RAM_W)
186 #endif /* DRAM_8BIT */
189 ;-----------------------------------------------------------------------
190 ;Register definitions
202 ;.def stx_bitcount = r9
204 .def srx_lastedgel = r10
205 .def srx_lastedgeh = r11
232 #if defined __ATmega8__
241 .equ hostact = 7 ;host active flag
242 .equ hostwrt = 6 ;host written flag
243 .equ rsflag = 5 ;read sector flag
244 .equ readop = 4 ;1 if read operation
247 ; This is the base z80 port address for clock access
248 #define TIMERPORT 0x40
249 #define TIMER_CTL TIMERPORT
250 #define TIMER_MSECS TIMERPORT+1
251 #define TIMER_SECS TIMER_MSECS+2
253 #define starttimercmd 1
254 #define quitTimerCmd 2
255 #define printTimerCmd 15
258 #if defined __ATmega8__
273 .equ OC2Aaddr= OC2addr
285 ; vim:set ts=8 noet nowrap