avr/config.inc

   1 ;    Configuration, hardware definition, ...
   2 ;
   3 ;    Copyright (C) 2010 Sprite_tm
   4 ;    Copyright (C) 2010 Leo C.
   5 ;
   6 ;    This file is part of avrcpm.
   7 ;
   8 ;    avrcpm is free software: you can redistribute it and/or modify it
   9 ;    under the terms of the GNU General Public License as published by
  10 ;    the Free Software Foundation, either version 3 of the License, or
  11 ;    (at your option) any later version.
  12 ;
  13 ;    avrcpm is distributed in the hope that it will be useful,
  14 ;    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;    GNU General Public License for more details.
  17 ;
  18 ;    You should have received a copy of the GNU General Public License
  19 ;    along with avrcpm.  If not, see <http://www.gnu.org/licenses/>.
  20 ;
  21 ;    $Id$
  22
  23
  24 #define VMAJOR 3                /* Version number */
  25 #define VMINOR 2
  26
  27 ;-----------------------------------------------------------------------
  28 ;
  29 ;             Hardware and feature configuration
  30 ;
  31
  32 ; Supported MCUs are: atmega328P atmega168 atmega88 atmega8
  33 ; Z80 emulation currently needs atmega328P, so this is the default.
  34 ;#define atmega328P
  35
  36 ; MCU frequency in Hz.
  37 ;#define F_CPU 20000000
  38
  39 ; Set this to 0, if you have a (one) DRAM chip whith 4 Bit data bus.
  40 ;#define DRAM_8BIT 1
  41
  42 ; Baudrate of serial port (console).
  43 ;#define BAUD 115200
  44
  45 ; I2C_SUPPORT defaults to 1 on 8-bit-ram systems and must be 0 on 4-bit-ram systems.
  46 ; Set this do 0, if you don't have  I2C peripherals and want to save some flash
  47 ; or use the I2C pins for other purposes.
  48 ;#define I2C_SUPPORT
  49
  50 ; Emulate Z80 cpu if 1, 8080 otherwise.
  51 ;
  52 ;#define EM_Z80 1
  53
  54 ; Uncomment and set RAMDISKCOUNT to 1-4 if you want to test the experimental and
  55 ; unsupported ramdisk feature . Number depends on actual ram size (256kx4 - 4Mx8)
  56 ; and bios dpb/dph definitions.
  57 ;#define RAMDISKCNT    0
  58
  59 ; Uncomment and set to 0, if you need to save flash (ie. ATmega88).
  60 ;#define FAT16_SUPPORT 1
  61
  62 ; Uncomment and set to 0, if you need to save flash.
  63 ;#define MMCBOOTLOADER 1
  64
  65
  66 ;-----------------------------------------------------------------------
  67 ;Debugging aids
  68
  69 .equ BOOTWAIT      = 1
  70 .equ MEMTEST       = 1
  71 .equ MEMFILL       = 1
  72 .equ MMC_DEBUG     = 0          /* Increase for more debugging */
  73 .equ FAT16_DEBUG   = 0
  74 .equ FAT16_RWDEBUG = 0
  75 .equ FAT16_DBG_FAT = 0
  76 .equ DISK_DEBUG    = 0          /* Increase for more debugging */
  77 .equ HOSTRW_DEBUG  = 0
  78 .equ HEAP_DEBUG    = 0
  79 .equ PORT_DEBUG    = 0
  80 .equ INS_DEBUG     = 0
  81 .equ STACK_DBG     = 0
  82 .equ PRINT_PC      = 0
  83 .equ TIMER_DEBUG   = 0
  84
  85 ;-----------------------------------------------------------------------
  86 ; Z80/8080 Virtual Ports
  87
  88 #define TIMERPORT   0x40                /* Base z80 port address for clock access */
  89 #define TIMER_CTL   TIMERPORT
  90 #define TIMER_MSECS TIMERPORT+1
  91 #define TIMER_SECS  TIMER_MSECS+2
  92 #define CLOCKPORT   TIMERPORT+7         /* Real time clock BCD (ss,mm,hh,DD,MM,YYYY) */
  93
  94 #define starttimercmd   1
  95 #define quitTimerCmd    2
  96 #define printTimerCmd   15
  97 #define uptimeCmd       16
  98
  99 #define DEBUGPORT   0x4F
 100
 101 #define startTraceCmd 1                 /* 'OUT (DEBUGPORT),startTraceCmd' starts tracing */
 102 #define stopTraceCmd  0
 103
 104 ; Virtual I2C Interface
 105 #define I2CSTAT 0x05
 106 #define I2CCTRL 0x05
 107 #define I2CBLEN 0x06
 108 #define I2CADR  0x07
 109 #define I2CADRL 0x07
 110 #define I2CADRH 0x08
 111
 112 ; Simple ADC Interface
 113 #define ADC80   0x17
 114 #define ADC81   0x18
 115
 116 ; Port-Expander PCF8574
 117 #define PORT    0x80
 118 #define PORT0   0x80
 119 #define PORT1   0x81
 120 #define PORT2   0x82
 121 #define PORT3   0x83
 122 #define PORT4   0x84
 123 #define PORT5   0x85
 124 #define PORT6   0x86
 125 #define PORT7   0x87
 126
 127 ;-----------------------------------------------------------------------
 128 ;
 129
 130 #define PARTID 0x52             /* Partition table id */
 131                                 /* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */
 132 #define IPLADDR 0x2000          /* Bootloader load address */
 133
 134 #define DRAM_WAITSTATES 1       /* Number of additional clock cycles for dram read access */
 135 #define REFR_RATE   64000       /* dram refresh rate in cycles/s. */
 136                                 /* Most drams need 1/15.6µs. */
 137 #define RXBUFSIZE 128           /* USART recieve buffer size. Must be power of 2 */
 138 #define TXBUFSIZE 32            /* USART transmit buffer size. Must be power of 2 */
 139
 140 #define I2C_CLOCK  100000       /* 100kHz */
 141 #define I2C_BUFSIZE    17       /* largest message size including address byte (SLA) */
 142
 143
 144 #define MMC_SPI2X  1            /* 0 = SPI CLK/4, 1 = SPI CLK/2 */
 145
 146 #define MEMFILL_VAL      0x76   /* Fill ram with HALT opcode. */
 147 #define DBG_TRACE_BOTTOM 0x01   /* Page boundaries for INS_DEBUG and PRINT_PC  */
 148 #define DBG_TRACE_TOP    0xdc   /* Trace is off, below bottom page and above top page. */
 149
 150 #ifndef DRAM_8BIT
 151   #define DRAM_8BIT 1           /* 1 = 8bit wide data bus to DRAM (ie two 4-bit Chips)*/
 152 #endif                          /* 0 = only one 4 bit wide DRAM chip */
 153 #ifndef F_CPU
 154   #define F_CPU 20000000        /* system clock in Hz; defaults to 20MHz */
 155 #endif
 156 #ifndef BAUD
 157   #define BAUD   115200         /* console baud rate */
 158 #endif
 159 #ifndef I2C_SUPPORT
 160   #define I2C_SUPPORT DRAM_8BIT /* I2C requires 8 bit DRAM */
 161 #endif
 162 #if I2C_SUPPORT && !DRAM_8BIT
 163   #error "I2C_SUPPORT requires 8 bit DRAM (DRAM_8BIT=1)!"
 164 #endif
 165 #ifndef ADC_SUPPORT
 166   #define ADC_SUPPORT 0
 167 #endif
 168
 169 #ifndef EM_Z80
 170   #define EM_Z80 1              /* Emulate Z80 if true, else 8080 */
 171 #endif
 172 #ifndef FAT16_SUPPORT
 173   #define FAT16_SUPPORT 1       /* Include Support for FAT16 Partitions */
 174 #endif                          /*  which may contain CP/M image files. */
 175 #ifndef RAMDISKCNT
 176   #define RAMDISKCNT   0        /* Number of RAM disks */
 177 #endif
 178 #define RAMDISKNR     'I'-'A'   /* Drive "letter" for first RAM disk */
 179
 180 /* MMC/SD Bootloader support.   */
 181 #define BOOTLDRSIZE 2048        /* Bytes needed for Bootloader (1024 Words Bootsection Size) */
 182 #define DEVID_S "ACPM"
 183 #ifndef MMCBOOTLOADER
 184   #define MMCBOOTLOADER 1
 185 #endif
 186 #ifndef TESTVERSION
 187   #define TESTVERSION 0
 188 #endif
 189
 190 ;-----------------------------------------------------------------------
 191 ; Port declarations
 192
 193 #if DRAM_8BIT   /* Implies software uart */
 194
 195 ;Port D
 196 .equ RAM_D0     = 0
 197 .equ RAM_D1     = 1
 198 .equ RAM_D2     = 2
 199 .equ RAM_D3     = 3
 200 .equ RAM_D4     = 4
 201 .equ RAM_D5     = 5
 202 .equ RAM_D6     = 6
 203 .equ RAM_D7     = 7
 204 .equ RAM_A0     = 0
 205 .equ RAM_A1     = 1
 206 .equ RAM_A2     = 2
 207 .equ RAM_A3     = 3
 208 .equ RAM_A4     = 4
 209 .equ RAM_A5     = 5
 210 .equ RAM_A6     = 6
 211 .equ RAM_A7     = 7
 212
 213 ;Port B
 214 .equ MMC_MOSI   = 3
 215 .equ MMC_MISO   = 4
 216 .equ MMC_SCK    = 5
 217 .equ RAM_A8     = 3
 218 .equ RAM_A9     = 4
 219 .equ RAM_A10    = 5
 220
 221 .equ RXD        = 0
 222 .equ TXD        = 1
 223 .equ MMC_CS     = 2
 224
 225 .equ P_MMC_CS   = PORTB
 226 .equ P_A8       = PORTB
 227 .equ P_RXD      = PORTB
 228 .equ P_TXD      = PORTB
 229
 230 ;Port C
 231 .equ RAM_RAS    = 0
 232 .equ RAM_CAS    = 1
 233 .equ RAM_OE     = 2
 234 .equ RAM_W      = 3
 235
 236 .equ P_RAS      = PORTC
 237 .equ P_CAS      = PORTC
 238 .equ P_OE       = PORTC
 239 .equ P_W        = PORTC
 240
 241
 242 #else   /* 4 bit RAM, hardware uart */
 243
 244 ; Port D
 245 .equ RXD        = 0
 246 .equ TXD        = 1
 247 .equ RAM_OE     = 2
 248 .equ RAM_A8     = 3
 249 .equ MMC_CS     = 4
 250 .equ RAM_A5     = 5
 251 .equ RAM_A6     = 6
 252 .equ RAM_A7     = 7
 253
 254 .equ P_RXD      = PORTD
 255 .equ P_OE       = PORTD
 256 .equ P_A8       = PORTD
 257 .equ P_MMC_CS   = PORTD
 258 .equ P_AH       = PORTD
 259                      ; RAM_A[7..5]
 260 .equ RAM_AH_MASK = (1<<RAM_A8)|(1<<RAM_A7)|(1<<RAM_A6)|(1<<RAM_A5)
 261 .equ PD_OUTPUT_MASK = (1<<MMC_CS) | (1<<RAM_OE) | RAM_AH_MASK
 262
 263
 264 ;Port B
 265 .equ RAM_A4     = 0
 266 .equ RAM_A3     = 1
 267 .equ RAM_A2     = 2
 268 .equ RAM_A1     = 3
 269 .equ MMC_MOSI   = 3
 270 .equ RAM_A0     = 4
 271 .equ MMC_MISO   = 4
 272 .equ RAM_RAS    = 5
 273 .equ MMC_SCK    = 5
 274
 275 .equ P_RAS      = PORTB
 276 .equ P_AL       = PORTB
 277                         ; RAM_A[4..0]
 278 .equ RAM_AL_MASK = (1<<RAM_A4)|(1<<RAM_A3)|(1<<RAM_A2)|(1<<RAM_A1)|(1<<RAM_A0)
 279 .equ PB_OUTPUT_MASK = (1<<RAM_ras) | RAM_AL_MASK
 280
 281 ;Port C
 282 .equ RAM_D0     = 0
 283 .equ RAM_D1     = 1
 284 .equ RAM_D2     = 2
 285 .equ RAM_D3     = 3
 286 .equ RAM_W      = 4
 287 .equ RAM_CAS    = 5
 288
 289 .equ P_DQ       = PORTC
 290 .equ P_W        = PORTC
 291 .equ P_CAS      = PORTC
 292
 293 .equ RAM_DQ_MASK = (1<<RAM_D3)|(1<<RAM_D2)|(1<<RAM_D1)|(1<<RAM_D0)
 294 .equ PC_OUTPUT_MASK = (1<<RAM_CAS)|(1<<RAM_W)
 295
 296 #endif  /* DRAM_8BIT */
 297
 298
 299 ;-----------------------------------------------------------------------
 300 ;Register definitions
 301
 302 .def    _tmp0   = r0
 303 .def    _tmp1   = r1
 304
 305 .def    _RAS0   = r2
 306 .def    _CAS0   = r3
 307 .def    _OE     = r4
 308 .def    _WE     = r5
 309 .def    _255    = r6
 310 .def    _0      = r7
 311
 312 .def    z_c     = r8    ;
 313 .def    z_b     = r9    ;
 314 .def    z_e     = r10   ;
 315 .def    z_d     = r11   ;
 316 .def    z_l     = r12   ;
 317 .def    z_h     = r13   ;
 318 .def    z_spl   = r14   ;
 319 .def    z_sph   = r15   ;
 320 .def    temp    = r16   ;
 321 .def    temp2   = r17   ;
 322 .def    temp3   = r18   ;
 323 ;.def   temp4   = r19   ;
 324 .def    intstat = r19   ;interpreter status / interrupt status
 325 .def    z_flags = r20   ;
 326 .def    z_a     = r21   ;
 327 .def    opl     = r22   ;
 328 .def    oph     = r23   ;
 329 .def    z_pcl   = r24   ;
 330 .def    z_pch   = r25   ;
 331 ; xl            ;r26
 332 ; xh            ;r27
 333 ; yl            ;r28
 334 ; yh            ;r29
 335 ; zl            ;r30
 336 ; zh            ;r31
 337
 338
 339 .equ    i_break = 0                     ;break detected flag
 340 .equ    i_trace = 1                     ;cpu interpreter trace flag
 341 .equ    i_halt  = 2                     ;executing halt instruction
 342
 343 #if defined __ATmega8__
 344  #if DRAM_8BIT
 345
 346         .equ    flags   = UBRRL         ;UART is unused with 8-Bit RAM
 347  #else
 348         .equ    flags   = TWBR          ;TWI is unused with 4-Bit RAM
 349  #endif
 350         .equ    P_PUD   = SFIOR
 351
 352 #else
 353
 354         .equ    flags   = GPIOR0
 355         .equ    P_PUD   = MCUCR
 356
 357 #endif /* __ATmega8__ */
 358
 359 ; Flags:
 360         .equ    hostact = 7             ;host active flag
 361         .equ    hostwrt = 6             ;host written flag
 362         .equ    rsflag  = 5             ;read sector flag
 363         .equ    readop  = 4             ;1 if read operation
 364
 365         .equ    prefixfd = 1            ;Opcode prefix DD=0, FD=1
 366
 367
 368 #if EM_Z80
 369   #define CPUSTR "Z80"
 370 #else
 371   #define CPUSTR "8080"
 372 #endif
 373 #if TESTVERSION
 374   #define TESTSTR "Test"
 375 #else
 376   #define TESTSTR ""
 377 #endif
 378
 379 #if defined __ATmega8__
 380 .equ    RXTXDR0 = UDR
 381 .equ    UCSR0A  = UCSRA
 382 .equ     UDRE0  = UDRE
 383 .equ    UCSR0B  = UCSRB
 384 .equ     RXCIE0 = RXCIE
 385 .equ     UDRIE0 = UDRIE
 386 .equ     RXEN0  = RXEN
 387 .equ     TXEN0  = TXEN
 388 .equ    UCSR0C  = UCSRC
 389 .equ     UCSZ00 = UCSZ0
 390 .equ     UCSZ01 = UCSZ1
 391 .equ    UBRR0H  = UBRRH
 392 .equ    UBRR0L  = UBRRL
 393 .equ    OCR2A   = OCR2
 394 .equ    OC2Aaddr= OC2addr
 395 .equ    TCCR2A  = TCCR2
 396 .equ    TCCR2B  = TCCR2
 397 .equ    TIMSK1  = TIMSK
 398 .equ    TIMSK2  = TIMSK
 399 .equ    OCIE2A  = OCIE2
 400 .equ    TIFR1   = TIFR
 401 .equ    ICIE1   = TICIE1
 402 #else
 403 .equ    RXTXDR0 = UDR0
 404 #endif
 405
 406 ; vim:set ts=8 noet nowrap
 407