1 ; Configuration, hardware definition, ...
3 ; Copyright (C) 2010 Sprite_tm
4 ; Copyright (C) 2010 Leo C.
6 ; This file is part of avrcpm.
8 ; avrcpm is free software: you can redistribute it and/or modify it
9 ; under the terms of the GNU General Public License as published by
10 ; the Free Software Foundation, either version 3 of the License, or
11 ; (at your option) any later version.
13 ; avrcpm is distributed in the hope that it will be useful,
14 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ; GNU General Public License for more details.
18 ; You should have received a copy of the GNU General Public License
19 ; along with avrcpm. If not, see <http://www.gnu.org/licenses/>.
25 #define VMAJOR 2 /* Version number */
29 #define DRAM_8BIT 1 /* 1 = 8bit wide DRAM */
32 #define F_CPU 20000000 /* system clock in Hz; defaults to 20MHz */
35 #define BAUD 38400 /* console baud rate */
41 ;#define RAMSIZE 256*K*4 /* 1 chip 256Kx4 */
42 #define RAMSIZE 4*M*4 * 2 /* 2 chips 4Mx4 */
45 #define FAT16_SUPPORT 1 /* Include Support for FAT16 Partitions */
46 #endif /* which may contain CP/M image files. */
47 #define RAMDISKCNT 0 /* Number of RAM disks */
48 #define RAMDISKNR 'I'-'A' /* Drive "letter" for first RAM disk */
50 #define PARTID 0x52 /* Partition table id */
51 /* http://www.win.tue.nl/~aeb/partitions/partition_types-1.html */
52 #define IPLADDR 0x2000 /* Bootloader load address */
54 #define DRAM_WAITSTATES 1 /* Number of additional clock cycles for dram read access */
55 #define REFR_RATE 64000 /* dram refresh rate in cycles/s. */
56 /* Most drams need 1/15.6µs. */
57 #define RXBUFSIZE 128 /* USART recieve buffer size. Must be power of 2 */
58 #define TXBUFSIZE 128 /* USART transmit buffer size. Must be power of 2 */
62 #define EM_Z80 0 /* we don't have any z80 instructions yet */
65 .equ MMC_DEBUG = 0 /* Increase for more debugging */
67 .equ FAT16_RWDEBUG = 0
68 .equ FAT16_DBG_FAT = 0
73 .equ DISK_DEBUG = 0 /* Increase for more debugging */
80 #define MMC_SPI2X 1 /* 0 = SPI CLK/4, 1 = SPI CLK/2 */
82 #define MEMFILL_VAL 0xCB /* Fill ram with cbs, which will trigger an invalid opcode error. */
83 #define DBG_TRACE_BOTTOM 0x01 /* Page boundaries for INS_DEBUG and PRINT_PC */
84 #define DBG_TRACE_TOP 0xdc /* Trace is off, below bottom page and above top page. */
86 ;-----------------------------------------------------------------------
89 #if DRAM_8BIT /* Implies software uart */
121 .equ P_MMC_CS = PORTB
137 #else /* 4 bit RAM, hardware uart */
152 .equ P_MMC_CS = PORTD
155 .equ RAM_AH_MASK = (1<<RAM_A8)|(1<<RAM_A7)|(1<<RAM_A6)|(1<<RAM_A5)
156 .equ PD_OUTPUT_MASK = (1<<MMC_CS) | (1<<RAM_OE) | RAM_AH_MASK
173 .equ RAM_AL_MASK = (1<<RAM_A4)|(1<<RAM_A3)|(1<<RAM_A2)|(1<<RAM_A1)|(1<<RAM_A0)
174 .equ PB_OUTPUT_MASK = (1<<RAM_ras) | RAM_AL_MASK
188 .equ RAM_DQ_MASK = (1<<RAM_D3)|(1<<RAM_D2)|(1<<RAM_D1)|(1<<RAM_D0)
189 .equ PC_OUTPUT_MASK = (1<<RAM_CAS)|(1<<RAM_W)
191 #endif /* DRAM_8BIT */
194 ;-----------------------------------------------------------------------
195 ;Register definitions
207 ;.def stx_bitcount = r9
209 .def srx_lastedgel = r10
210 .def srx_lastedgeh = r11
237 #if defined __ATmega8__
246 .equ hostact = 7 ;host active flag
247 .equ hostwrt = 6 ;host written flag
248 .equ rsflag = 5 ;read sector flag
249 .equ readop = 4 ;1 if read operation
252 ; This is the base z80 port address for clock access
253 #define TIMERPORT 0x40
254 #define TIMER_CTL TIMERPORT
255 #define TIMER_MSECS TIMERPORT+1
256 #define TIMER_SECS TIMER_MSECS+2
258 #define starttimercmd 1
259 #define quitTimerCmd 2
260 #define printTimerCmd 15
263 #if defined __ATmega8__
278 .equ OC2Aaddr= OC2addr
290 ; vim:set ts=8 noet nowrap