;
; You should have received a copy of the GNU General Public License
; along with this program. If not, see <http://www.gnu.org/licenses/>.
+;
+; $Id$
+;
;.nolist
#if defined atmega8
#define RXBUFSIZE 64 /* USART recieve buffer size. Must be power of 2 */
#define TXBUFSIZE 64 /* USART transmit buffer size. Must be power of 2 */
+#define DRAM_WAITSTATES 1 /* Number of additional clock cycles for dram read access */
#define REFR_RATE 64000 /* dram refresh rate in cycles/s. */
/* Most drams need 1/15.6µs. */
#define REFR_PRE 8 /* timer prescale factor */
#define REFR_CNT F_CPU / REFR_RATE / REFR_PRE
-#if defined __ATmega8__
- .equ refr_vect = OC2addr
-#else
- .equ refr_vect = OC2Aaddr
-#endif
#define DRAM_WORD_ACCESS 0 /* experimental */
.equ ZFL_C = 0
;Register definitions
-.undef xl ;r26
-.undef xh ;r27
.def _tmp = r0 ; 0
.def _0 = r1
.def oph = r23 ;
.def z_pcl = r24 ;
.def z_pch = r25 ;
-.def adrl = r26 ;
-.def adrh = r27 ;
; yl ;r28
; yh ;r29
; zl ;r30 ;
.equ UBRR0H = UBRRH
.equ UBRR0L = UBRRL
.equ OCR2A = OCR2
+.equ OC2Aaddr= OC2addr
.equ TCCR2A = TCCR2
.equ TCCR2B = TCCR2
.equ TIMSK1 = TIMSK
+;----------------------------------------
+; add wait states
+; dram_wait number_of_cycles
+
+.macro dram_wait
+.if @0 > 1
+ rjmp PC+1
+ dram_wait @0 - 2
+.elif @0 > 0
+ nop
+ dram_wait @0 - 1
+.endif
+.endm
+
+
.cseg
.org 0
rjmp start ; reset vector
-.org refr_vect
+.org OC2Aaddr
rjmp refrint ; tim2cmpa
.org OC1Aaddr ; Timer/Counter1 Compare Match A
rjmp sysclockint ; 1ms system timer
ldi temp,(1<<WDCE)
outm8 WDTCSR,temp
+; - Clear RAM
+
+ ldi zl,low(SRAM_START)
+ ldi zh,high(SRAM_START)
+ ldi temp2,high(ramtop)
+clr_l:
+ st z+,_0
+ cpi zl,low(ramtop)
+ cpc zh,temp2
+ brne clr_l
+
; - Setup Ports
ldi temp,(1<<PUD) ;disable pullups
outm8 P_PUD,temp
; - Init serial port
- sts rxcount,_0 ; reset receive buffer
- sts rxidx_r,_0
- sts rxidx_w,_0
- sts txcount,_0 ; reset transmit buffer
- sts txidx_r,_0
- sts txidx_w,_0
-
ldi temp, (1<<TXEN0) | (1<<RXEN0) | (1<<RXCIE0)
outm8 UCSR0B,temp
.ifdef URSEL
ldi temp, LOW(UBRR_VAL)
outm8 UBRR0L,temp
-;Init timer2. Refresh-call should happen every (8ms/512)=312 cycles.
-
- ldi temp,REFR_CNT*2 ; 2 cycles per int
- outm8 OCR2A,temp
- inm8 temp,TCCR2A
- ori temp,(1<<WGM21) ;CTC mode
- outm8 TCCR2A,temp
- inm8 temp,TCCR2B
- ori temp,REFR_CS ;clk/REFR_PRE
- outm8 TCCR2B,temp
- inm8 temp,TIMSK2
- ori temp, (1<<OCIE2A)
- outm8 TIMSK2,temp
-
; Init clock/timer system
- ldi zl,low(timer_base)
- ldi zh,high(timer_base)
- ldi temp2,timer_size
-ti_loop:
- st z+,_0
- dec temp2
- brne ti_loop
-
; Init timer 1 as 1 ms system clock tick.
ldi temp,high(F_CPU/1000)
ori temp,(1<<OCIE1A)
outm8 TIMSK1,temp
+;Init timer2. Refresh-call should happen every (8ms/512)=312 cycles.
+
+ ldi temp,REFR_CNT*2 ; 2 cycles per int
+ outm8 OCR2A,temp
+ inm8 temp,TCCR2A
+ ori temp,(1<<WGM21) ;CTC mode
+ outm8 TCCR2A,temp
+ inm8 temp,TCCR2B
+ ori temp,REFR_CS ;clk/REFR_PRE
+ outm8 TCCR2B,temp
+ inm8 temp,TIMSK2
+ ori temp, (1<<OCIE2A)
+ outm8 TIMSK2,temp
+
sei
.db "Testing RAM: fill...",0,0
;Fill RAM
- ldi adrl,0
- ldi adrh,0
+ ldi xl,0
+ ldi xh,0
ramtestw:
- mov temp,adrh
- eor temp,adrl
+ mov temp,xh
+ eor temp,xl
rcall memwritebyte
- adiw adrl,1
+ adiw xl,1
brcc ramtestw
rcall printstr
.db "wait...",0
.db "reread...",13,0,0
;re-read RAM
- ldi adrl,0
- ldi adrh,0
+ ldi xl,0
+ ldi xh,0
ramtestr:
rcall memReadByte
- mov temp2,adrh
- eor temp2,adrl
+ mov temp2,xh
+ eor temp2,xl
cp temp,temp2
breq ramtestrok
rcall printhex
ldi temp,'<'
rcall uartPutc
- mov temp,adrh
- eor temp,adrl
+ mov temp,xh
+ eor temp,xl
rcall printhex
ldi temp,'@'
rcall uartPutc
- mov temp,adrh
+ mov temp,xh
rcall printhex
- mov temp,adrl
+ mov temp,xl
rcall printhex
ldi temp,13
rcall uartPutc
ramtestrok:
- adiw adrl,1
+ adiw xl,1
brcc ramtestr
.endif
.if MEMFILL_CB
;Fill ram with cbs, which (for now) will trigger an invalid opcode error.
- ldi adrl,0
- ldi adrh,0
+ ldi xl,0
+ ldi xh,0
ramfillw:
ldi temp,0xcb
rcall memwritebyte
- adiw adrl,1
+ adiw xl,1
brcc ramfillw
.endif
;Load initial sector from MMC (512 bytes)
- ldi adrh,0
- ldi adrl,0
- rcall mmcReadSect
+ ldi yh,0
+ ldi yl,0
+ ldi xh,0
+ ldi xl,0
+ rcall mmcReadSect
;Save to Z80 RAM (only 128 bytes because that's retro)
ldi zl,low(hostbuf)
ldi zh,high(hostbuf)
- ldi adrh,0x20
- ldi adrl,0x00
+ ldi xh,0x20
+ ldi xl,0x00
iplwriteloop:
ld temp,z+
rcall memWriteByte
- adiw adrl,1
+ adiw xl,1
cpi zl,low(hostbuf+128)
brne iplwriteloop
cpi zh,high(hostbuf+128)
.endif
; *** Stage 1: Fetch next opcode
- movw adrl,z_pcl
+ movw xl,z_pcl
rcall memReadByte
;18 - Sector select
;20 - Write addr l
;21 - Write addr h
-;22 - Trigger - write 1 to read, 2 to write a sector using the above info;
-; 3 - 5, write to allocated/dirctory/unallocated
+;22 - Trigger - write to read, to write a sector using the above info;
+; , write to allocated/dirctory/unallocated
.equ READ_FUNC = 7
.equ WRITE_FUNC = 6
;Convert track/sector to an LBA address (in 128byte blocks)
- lds adrl,seeksec ;
- ldi adrh,0 ;
+ lds xl,seeksec ;
+ ldi xh,0 ;
lds temp3,seektrk ;
lds temp4,seektrk+1 ;
ldi temp,CPMSPT ;
mul temp3,temp ;
- add adrl,r0 ;
- adc adrh,r1 ;
+ add xl,r0 ;
+ adc xh,r1 ;
mul temp4,temp ;
- add adrh,r0 ;adrh:adrl := sec + trk * SectorsPerTrack
+ add xh,r0 ;xh:xl := sec + trk * SectorsPerTrack
clr _0
- mov temp,adrl
+ mov temp,xl
andi temp,SECMSK ;mask buffer number
push temp ;save for later
-.if DISK_DEBUG
- rcall printstr
- .db "; bufnr: ",0,0
- rcall printhex
-.endif
;Convert from CP/M LBA blocks to host LBA blocks
ldi temp,SECSHF
dsk_sh1:
- lsr adrh
- ror adrl
+ lsr xh
+ ror xl
dec temp
brne dsk_sh1
- ;adrh:adrl = host block to seek
+ ;xh:xl = host block to seek
; active host sector?
sbis flags,hostact ;host active?
rjmp dsk_filhst ;fill host if not
; same disk, same block?
lds temp3,hostlba
lds temp4,hostlba+1
- cp adrl,temp3
- cpc adrh,temp4
+ cp xl,temp3
+ cpc xh,temp4
breq dsk_match
;
dsk_nomatch:
;may have to fill the host buffer
lds temp,seekdsk
sts hostdsk,temp
- sts hostlba,adrl
- sts hostlba+1,adrh
+ sts hostlba,xl
+ sts hostlba+1,xh
sbic flags,rsflag ;need to read?
rcall dsk_readhost ;yes, if 1
.endif
clr _0
- lds adrl,dmaadr
- lds adrh,dmaadr+1
- push yl
- ldi yl,128 ;length of move
+ lds xl,dmaadr
+ lds xh,dmaadr+1
+ ldi temp3,128 ;length of move
sbic flags,readop ;which way?
rjmp dsk_rmove ;skip if read
; mark write operation
sbi flags,hostwrt ;hostwrt = 1
dsk_wmove:
- rcall memReadByte
- st z+,temp
- adiw adrl,1
- dec yl
+ rcall memReadByte
+ st z+,temp
+ adiw xl,1
+ dec temp3
brne dsk_wmove
rjmp dsk_rwmfin
dsk_rmove:
ld temp,z+
rcall memWriteByte
- adiw adrl,1
- dec yl
+ adiw xl,1
+ dec temp3
brne dsk_rmove
dsk_rwmfin:
- pop yl
; data has been moved to/from host buffer
lds temp,wrtype ;write type
cpi temp,WRDIR ;to directory?
;error flag in erflag.
;Return erflag non-zero if error
- push adrh
- push adrl
- lds adrl,hostlba
- lds adrh,hostlba+1
+ push yh
+ push yl
+ push xh
+ push xl
+ lds xl,hostlba
+ lds xh,hostlba+1
+ ldi yl,0
+ ldi yh,0
rcall mmcWriteSect
- pop adrl
- pop adrh
+ pop xl
+ pop xh
+ pop yl
+ pop yh
sts erflag,_0
ret
;Read "hostsiz" bytes into hostbuf and return
;error flag in erflag.
- push adrh
- push adrl
- lds adrl,hostlba
- lds adrh,hostlba+1
+ push yh
+ push yl
+ push xh
+ push xl
+ lds xl,hostlba
+ lds xh,hostlba+1
+ ldi yl,0
+ ldi yh,0
rcall mmcReadSect
- pop adrl
- pop adrh
+ pop xl
+ pop xh
+ pop yl
+ pop yh
sts erflag,_0
ret
mmcByte:
.if MMC_DEBUG
- push zl
- push zh
rcall printstr
.db "MMC: <--",0
rcall printhex
in temp,SPDR
.if MMC_DEBUG
- push temp
rcall printstr
.db ", -->",0
rcall printhex
rcall printstr
.db ".",13,0
- pop temp
- pop zh
- pop zl
.endif
ret
ret
-;Call this with adrh:adrl = sector number
-;16bit lba address means a max reach of 32M.
+;Call this with yh:yl:xh:xl = sector number
+;
mmcReadSect:
ldi temp,0x50
out SPCR,temp
rcall mmcByteNoSend
ldi temp,0x51 ;cmd (read sector)
rcall mmcByte
- ldi temp,0
- lsl adrl
- rol adrh
- rol temp
+ lsl xl ;convert to byte address (*512)
+ rol xh
+ rol yl
+ mov temp,yl
rcall mmcByte
- mov temp,adrh ;pxl
+ mov temp,xh ;pxl
rcall mmcByte
- mov temp,adrl ;pyh
+ mov temp,xl ;pyh
rcall mmcByte
ldi temp,0 ;pyl
rcall mmcByte
ret
-;Call this with adrh:adrl = sector number
-;16bit lba address means a max reach of 32M.
+;Call this with yh:yl:xh:xl = sector number
+;
mmcWriteSect:
ldi temp,0x50
out SPCR,temp
ldi temp,0x58 ;cmd (write sector)
rcall mmcByte
- ldi temp,0
- lsl adrl
- rol adrh
- rol temp
+ lsl xl ;convert to byte address (*512)
+ rol xh
+ rol yl
+ mov temp,yl
rcall mmcByte
- mov temp,adrh ;pxl
+ mov temp,xh ;pxl
rcall mmcByte
- mov temp,adrl ;pyh
+ mov temp,xl ;pyh
rcall mmcByte
ldi temp,0 ;pyl
rcall mmcByte
out P_AH,temp
.endm
-;Loads the byte on address adrh:adrl into temp.
-;must not alter adrh:adrl
+;Loads the byte on address xh:xl into temp.
+;must not alter xh:xl
dram_read:
cli
- DRAM_SETADDR adrh, ~0,(1<<ram_ras), ~(1<<ram_a8), (1<<ram_oe)
+ DRAM_SETADDR xh, ~0,(1<<ram_ras), ~(1<<ram_a8), (1<<ram_oe)
cbi P_RAS,ram_ras
- DRAM_SETADDR adrl, ~(1<<ram_ras),0, ~((1<<ram_oe)), (1<<ram_a8)
+ DRAM_SETADDR xl, ~(1<<ram_ras),0, ~((1<<ram_oe)), (1<<ram_a8)
cbi P_CAS,ram_cas
cbi P_A8,ram_a8
- nop
+ dram_wait DRAM_WAITSTATES ;
in temp,P_DQ-2 ; PIN
sbi P_CAS,ram_cas
cbi P_CAS,ram_cas
andi temp,0x0f
swap temp
- nop
+ dram_wait DRAM_WAITSTATES ;
in temp2,P_DQ-2 ; PIN
andi temp2,0x0f
or temp,temp2
#if DRAM_WORD_ACCESS
dram_read_w:
- cpi adrl,255
+ cpi xl,255
brne dram_read_w1
rcall dram_read
push temp
- adiw adrl,1
+ adiw xl,1
rcall dram_read
mov temp2,temp
pop temp
dram_read_w1:
cli
- DRAM_SETADDR adrh, ~0,(1<<ram_ras), ~(1<<ram_a8),(1<<ram_oe)
+ DRAM_SETADDR xh, ~0,(1<<ram_ras), ~(1<<ram_a8),(1<<ram_oe)
cbi P_RAS,ram_ras
- DRAM_SETADDR adrl, ~(1<<ram_ras),0, ~((1<<ram_oe)), (1<<ram_a8)
+ DRAM_SETADDR xl, ~(1<<ram_ras),0, ~((1<<ram_oe)), (1<<ram_a8)
cbi P_CAS,ram_cas
cbi P_A8,ram_a8
nop
; push temp
mov _wl,temp
- inc adrl
- DRAM_SETADDR adrl, ~(1<<ram_ras),0, ~((1<<ram_oe)), (1<<ram_a8)
+ inc xl
+ DRAM_SETADDR xl, ~(1<<ram_ras),0, ~((1<<ram_oe)), (1<<ram_a8)
cbi P_CAS,ram_cas
cbi P_A8,ram_a8
nop
ret
#endif
-;Writes the byte in temp to adrh:adrl
-;must not alter adrh:adrl
+;Writes the byte in temp to xh:xl
+;must not alter xh:xl
dram_write:
cli
andi temp,RAM_DQ_MASK & ~(1<<ram_w)
ori temp,(1<<ram_cas)
out PORTC,temp
- DRAM_SETADDR adrh, ~0,(1<<ram_ras), ~(1<<ram_a8),(1<<ram_oe)
+ DRAM_SETADDR xh, ~0,(1<<ram_ras), ~(1<<ram_a8),(1<<ram_oe)
cbi P_RAS,ram_ras
- DRAM_SETADDR adrl, ~(1<<ram_ras),0, ~((1<<ram_a8)),(1<<ram_oe)
+ DRAM_SETADDR xl, ~(1<<ram_ras),0, ~((1<<ram_a8)),(1<<ram_oe)
cbi PORTC,ram_cas
sbi PORTC,ram_cas
#if DRAM_WORD_ACCESS
dram_write_w:
- cpi adrl,255
+ cpi xl,255
brne dram_write_w1
push temp2
rcall dram_write
pop temp
- adiw adrl,1
+ adiw xl,1
rcall dram_write
ret
ori temp,(1<<ram_cas)
out PORTC,temp
- DRAM_SETADDR adrh, ~0,(1<<ram_ras), ~(1<<ram_a8),(1<<ram_oe)
+ DRAM_SETADDR xh, ~0,(1<<ram_ras), ~(1<<ram_a8),(1<<ram_oe)
cbi P_RAS,ram_ras
- DRAM_SETADDR adrl, ~(1<<ram_ras),0, ~((1<<ram_a8)),(1<<ram_oe)
+ DRAM_SETADDR xl, ~(1<<ram_ras),0, ~((1<<ram_a8)),(1<<ram_oe)
cbi PORTC,ram_cas
sbi PORTC,ram_cas
sbi PORTC,ram_cas
pop temp
- inc adrl
+ inc xl
mov temp2,temp
andi temp,RAM_DQ_MASK & ~(1<<ram_w)
ori temp,(1<<ram_cas)
out PORTC,temp
- DRAM_SETADDR adrl, ~(1<<ram_ras),0, ~((1<<ram_a8)),(1<<ram_oe)
+ DRAM_SETADDR xl, ~(1<<ram_ras),0, ~((1<<ram_a8)),(1<<ram_oe)
cbi PORTC,ram_cas
sbi PORTC,ram_cas
; nop ;1 |0 |0
sbi P_RAS,ram_ras ;2 |0 |0
; |0 |0
+ dram_wait DRAM_WAITSTATES-1 ;
; nop ;1 |0 |0
cbi P_RAS,ram_ras ;2 |0 1|
; |0 1|
; 1| 1|
reti ;4 --> 21 cycles
-; ****************************************************************************
; ------------- system timer 1ms ---------------
.dseg
txfifo:
.byte TXBUFSIZE
+ramtop:
.cseg
; Save received character in a circular buffer. Do nothing if buffer overflows.
ret
do_fetch_mbc:
- movw adrl,z_c
+ movw xl,z_c
rcall memReadByte
mov opl,temp
ret
do_fetch_mde:
- movw adrl,z_e
+ movw xl,z_e
rcall memReadByte
mov opl,temp
ret
do_fetch_mhl:
- movw adrl,z_l
+ movw xl,z_l
rcall memReadByte
mov opl,temp
ret
do_fetch_msp:
- movw adrl,z_spl
+ movw xl,z_spl
#if DRAM_WORD_ACCESS
rcall memReadWord
movw opl,temp
#else
rcall memReadByte
mov opl,temp
- adiw adrl,1
+ adiw xl,1
rcall memReadByte
mov oph,temp
#endif
ret
do_fetch_dir8:
- movw adrl,z_pcl
+ movw xl,z_pcl
rcall memReadByte
adiw z_pcl,1
mov opl,temp
ret
do_fetch_dir16:
- movw adrl,z_pcl
+ movw xl,z_pcl
#if DRAM_WORD_ACCESS
rcall memReadWord
movw opl,temp
#else
rcall memReadByte
mov opl,temp
- adiw adrl,1
+ adiw xl,1
rcall memReadByte
mov oph,temp
#endif
ret
do_fetch_rst:
- movw adrl,z_pcl
- subi adrl,1
- sbci adrh,0
+ movw xl,z_pcl
+ subi xl,1
+ sbci xh,0
rcall memReadByte
andi temp,0x38
ldi oph,0
ret
do_store_mbc:
- movw adrl,z_c
+ movw xl,z_c
mov temp,opl
rcall memWriteByte
ret
do_store_mde:
- movw adrl,z_e
+ movw xl,z_e
mov temp,opl
rcall memWriteByte
ret
do_store_mhl:
- movw adrl,z_l
+ movw xl,z_l
mov temp,opl
rcall memWriteByte
ret
do_store_msp:
- movw adrl,z_spl
+ movw xl,z_spl
#if DRAM_WORD_ACCESS
movw temp,opl
rcall memWriteWord
#else
mov temp,opl
rcall memWriteByte
- adiw adrl,1
+ adiw xl,1
mov temp,oph
rcall memWriteByte
#endif
ret
do_store_am:
- movw adrl,opl
+ movw xl,opl
mov temp,z_a
rcall memWriteByte
ret
;----------------------------------------------------------------
-.equ AVR_T = 6
-.equ AVR_H = 5
-.equ AVR_S = 4
-.equ AVR_V = 3
-.equ AVR_N = 2
-.equ AVR_Z = 1
-.equ AVR_C = 0
+.equ AVR_T = SREG_T
+.equ AVR_H = SREG_H
+.equ AVR_S = SREG_S
+.equ AVR_V = SREG_V
+.equ AVR_N = SREG_N
+.equ AVR_Z = SREG_Z
+.equ AVR_C = SREG_C
;------------------------------------------------;
; Move single bit between two registers
;
;
do_op_sthl: ;store hl to mem loc in opl:h
- movw adrl,opl
+ movw xl,opl
#if DRAM_WORD_ACCESS
movw temp,z_l
rcall memWriteWord
#else
mov temp,z_l
rcall memWriteByte
- adiw adrl,1
+ adiw xl,1
mov temp,z_h
rcall memWriteByte
#endif
;
;
do_op_rmem16:
- movw adrl,opl
+ movw xl,opl
#if DRAM_WORD_ACCESS
rcall memReadWord
movw opl,temp
#else
rcall memReadByte
mov opl,temp
- adiw adrl,1
+ adiw xl,1
rcall memReadByte
mov oph,temp
#endif
;
;
do_op_rmem8:
- movw adrl,opl
+ movw xl,opl
rcall memReadByte
mov opl,temp
ret
;
;
do_op_push16:
- movw adrl,z_spl
- subi adrl,2
- sbci adrh,0
- movw z_spl,adrl
+ movw xl,z_spl
+ subi xl,2
+ sbci xh,0
+ movw z_spl,xl
#if DRAM_WORD_ACCESS
movw temp,opl
rcall memWriteWord
#else
mov temp,opl
rcall memWriteByte
- adiw adrl,1
+ adiw xl,1
mov temp,oph
rcall memWriteByte
#endif
;
;
do_op_pop16:
- movw adrl,z_spl
+ movw xl,z_spl
#if DRAM_WORD_ACCESS
rcall memReadWord
movw opl,temp
#else
rcall memReadByte
mov opl,temp
- adiw adrl,1
+ adiw xl,1
rcall memReadByte
mov oph,temp
#endif
projects / avrcpm.git / commitdiff