[irmp.git] / main.c

/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
 * main.c - demo main module to test irmp decoder\r
 *\r
 * Copyright (c) 2009-2015 Frank Meyer - frank(at)fli4l.de\r
 *\r
 * $Id: main.c,v 1.27 2015/02/27 10:19:20 fm Exp $\r
 *\r
 * This demo module is runnable on AVRs and LM4F120 Launchpad (ARM Cortex M4)\r
 *\r
 * ATMEGA88 @ 8 MHz internal RC      Osc with BODLEVEL 4.3V: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9\r
 * ATMEGA88 @ 8 MHz external Crystal Osc with BODLEVEL 4.3V: lfuse: 0xFF hfuse: 0xDC efuse: 0xF9\r
 *\r
 * This program is free software; you can redistribute it and/or modify\r
 * it under the terms of the GNU General Public License as published by\r
 * the Free Software Foundation; either version 2 of the License, or\r
 * (at your option) any later version.\r
 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
 */\r
\r
#include "irmp.h"\r
\r
#ifndef F_CPU\r
#error F_CPU unknown\r
#endif\r
\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
 * ATMEL AVR part:\r
 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
 */\r
#if defined (ATMEL_AVR)\r
\r
#include "irmp.h"\r
#define BAUD  9600L\r
#include <util/setbaud.h>\r
\r
#ifdef UBRR0H\r
\r
#define UART0_UBRRH                             UBRR0H\r
#define UART0_UBRRL                             UBRR0L\r
#define UART0_UCSRA                             UCSR0A\r
#define UART0_UCSRB                             UCSR0B\r
#define UART0_UCSRC                             UCSR0C\r
#define UART0_UDRE_BIT_VALUE                    (1<<UDRE0)\r
#define UART0_UCSZ1_BIT_VALUE                   (1<<UCSZ01)\r
#define UART0_UCSZ0_BIT_VALUE                   (1<<UCSZ00)\r
#ifdef URSEL0\r
#define UART0_URSEL_BIT_VALUE                   (1<<URSEL0)\r
#else\r
#define UART0_URSEL_BIT_VALUE                   (0)\r
#endif\r
#define UART0_TXEN_BIT_VALUE                    (1<<TXEN0)\r
#define UART0_UDR                               UDR0\r
#define UART0_U2X                               U2X0\r
\r
#else\r
\r
#define UART0_UBRRH                             UBRRH\r
#define UART0_UBRRL                             UBRRL\r
#define UART0_UCSRA                             UCSRA\r
#define UART0_UCSRB                             UCSRB\r
#define UART0_UCSRC                             UCSRC\r
#define UART0_UDRE_BIT_VALUE                    (1<<UDRE)\r
#define UART0_UCSZ1_BIT_VALUE                   (1<<UCSZ1)\r
#define UART0_UCSZ0_BIT_VALUE                   (1<<UCSZ0)\r
#ifdef URSEL\r
#define UART0_URSEL_BIT_VALUE                   (1<<URSEL)\r
#else\r
#define UART0_URSEL_BIT_VALUE                   (0)\r
#endif\r
#define UART0_TXEN_BIT_VALUE                    (1<<TXEN)\r
#define UART0_UDR                               UDR\r
#define UART0_U2X                               U2X\r
\r
#endif //UBRR0H\r
\r
static void\r
uart_init (void)\r
{\r
    UART0_UBRRH = UBRRH_VALUE;                                                                      // set baud rate\r
    UART0_UBRRL = UBRRL_VALUE;\r
\r
#if USE_2X\r
    UART0_UCSRA |= (1<<UART0_U2X);\r
#else\r
    UART0_UCSRA &= ~(1<<UART0_U2X);\r
#endif\r
\r
    UART0_UCSRC = UART0_UCSZ1_BIT_VALUE | UART0_UCSZ0_BIT_VALUE | UART0_URSEL_BIT_VALUE;\r
    UART0_UCSRB |= UART0_TXEN_BIT_VALUE;                                                            // enable UART TX\r
}\r
\r
static void\r
uart_putc (unsigned char ch)\r
{\r
    while (!(UART0_UCSRA & UART0_UDRE_BIT_VALUE))\r
    {\r
        ;\r
    }\r
\r
    UART0_UDR = ch;\r
}\r
\r
static void\r
uart_puts (char * s)\r
{\r
    while (*s)\r
    {\r
        uart_putc (*s);\r
        s++;\r
    }\r
}\r
\r
static void\r
uart_puts_P (PGM_P s)\r
{\r
    uint8_t ch;\r
\r
    while ((ch = pgm_read_byte(s)) != '\0')\r
    {\r
        uart_putc (ch);\r
        s++;\r
    }\r
}\r
\r
static char *\r
itoh (char * buf, uint8_t digits, uint16_t number)\r
{\r
    for (buf[digits] = 0; digits--; number >>= 4)\r
    {\r
        buf[digits] = "0123456789ABCDEF"[number & 0x0F];\r
    }\r
    return buf;\r
}\r
\r
static void\r
timer1_init (void)\r
{\r
#if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__)                // ATtiny45 / ATtiny85:\r
\r
#if F_CPU >= 16000000L\r
    OCR1C   =  (F_CPU / F_INTERRUPTS / 8) - 1;                              // compare value: 1/15000 of CPU frequency, presc = 8\r
    TCCR1   = (1 << CTC1) | (1 << CS12);                                    // switch CTC Mode on, set prescaler to 8\r
#else\r
    OCR1C   =  (F_CPU / F_INTERRUPTS / 4) - 1;                              // compare value: 1/15000 of CPU frequency, presc = 4\r
    TCCR1   = (1 << CTC1) | (1 << CS11) | (1 << CS10);                      // switch CTC Mode on, set prescaler to 4\r
#endif\r
\r
#else                                                                       // ATmegaXX:\r
    OCR1A   =  (F_CPU / F_INTERRUPTS) - 1;                                  // compare value: 1/15000 of CPU frequency\r
    TCCR1B  = (1 << WGM12) | (1 << CS10);                                   // switch CTC Mode on, set prescaler to 1\r
#endif\r
\r
#ifdef TIMSK1\r
    TIMSK1  = 1 << OCIE1A;                                                  // OCIE1A: Interrupt by timer compare\r
#else\r
    TIMSK   = 1 << OCIE1A;                                                  // OCIE1A: Interrupt by timer compare\r
#endif\r
}\r
\r
#ifdef TIM1_COMPA_vect                                                      // ATtiny84\r
#define COMPA_VECT  TIM1_COMPA_vect\r
#else\r
#define COMPA_VECT  TIMER1_COMPA_vect                                       // ATmega\r
#endif\r
\r
ISR(COMPA_VECT)                                                             // Timer1 output compare A interrupt service routine, called every 1/15000 sec\r
{\r
  (void) irmp_ISR();                                                        // call irmp ISR\r
  // call other timer interrupt routines...\r
}\r
\r
int\r
main (void)\r
{\r
    IRMP_DATA   irmp_data;\r
    char        buf[3];\r
\r
    irmp_init();                                                            // initialize irmp\r
    timer1_init();                                                          // initialize timer1\r
    uart_init();                                                            // initialize uart\r
\r
    sei ();                                                                 // enable interrupts\r
\r
    for (;;)\r
    {\r
        if (irmp_get_data (&irmp_data))\r
        {\r
            uart_puts_P (PSTR("protocol: 0x"));\r
            itoh (buf, 2, irmp_data.protocol);\r
            uart_puts (buf);\r
\r
#if IRMP_PROTOCOL_NAMES == 1\r
            uart_puts_P (PSTR("   "));\r
            uart_puts_P (pgm_read_word (&(irmp_protocol_names[irmp_data.protocol])));\r
#endif\r
\r
            uart_puts_P (PSTR("   address: 0x"));\r
            itoh (buf, 4, irmp_data.address);\r
            uart_puts (buf);\r
\r
            uart_puts_P (PSTR("   command: 0x"));\r
            itoh (buf, 4, irmp_data.command);\r
            uart_puts (buf);\r
\r
            uart_puts_P (PSTR("   flags: 0x"));\r
            itoh (buf, 2, irmp_data.flags);\r
            uart_puts (buf);\r
\r
            uart_puts_P (PSTR("\r\n"));\r
        }\r
    }\r
}\r
\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
 * LM4F120 Launchpad (ARM Cortex M4):\r
 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
 */\r
#elif defined(STELLARIS_ARM_CORTEX_M4)\r
\r
void\r
timer1_init (void)\r
{\r
    SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);\r
    TimerConfigure(TIMER1_BASE, TIMER_CFG_32_BIT_PER);\r
\r
    TimerLoadSet(TIMER1_BASE, TIMER_A, (F_CPU / F_INTERRUPTS) -1);\r
    IntEnable(INT_TIMER1A);\r
    TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);\r
    TimerEnable(TIMER1_BASE, TIMER_A);\r
    // Important: Timer1IntHandler has to be configured in startup_ccs.c !\r
}\r
\r
void\r
Timer1IntHandler(void)                                                      // Timer1 Interrupt Handler\r
{\r
  (void) irmp_ISR();                                                        // call irmp ISR\r
  // call other timer interrupt routines...\r
}\r
\r
int\r
main (void)\r
{\r
    IRMP_DATA irmp_data;\r
\r
    ROM_FPUEnable();\r
    ROM_FPUStackingEnable();\r
    ROM_SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);\r
\r
    irmp_init();                                                            // initialize irmp\r
    timer1_init();                                                          // initialize timer1\r
    sei ();                                                                 // enable interrupts\r
\r
    for (;;)\r
    {\r
        if (irmp_get_data (&irmp_data))\r
        {\r
            // ir signal decoded, do something here...\r
            // irmp_data.protocol is the protocol, see irmp.h\r
            // irmp_data.address is the address/manufacturer code of ir sender\r
            // irmp_data.command is the command code\r
            // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
        }\r
    }\r
}\r
\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
 * PIC18F4520 with XC8 compiler:\r
 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
 */\r
#elif defined (__XC8)\r
\r
#define _XTAL_FREQ  32000000UL                                              // 32MHz clock\r
#define FOSC        _XTAL_FREQ\r
#define FCY         FOSC / 4UL                                              // --> 8MHz\r
\r
#define BAUDRATE 19200UL\r
#define BRG (( FCY  16  BAUDRATE ) -1UL)\r
\r
#include <stdio.h>\r
#include <stdlib.h>\r
\r
int\r
main (void)\r
{\r
    IRMP_DATA irmp_data;\r
\r
    irmp_init();                                                            // initialize irmp\r
\r
    // infinite loop, interrupts will blink PORTD pins and handle UART communications.\r
    while (1)\r
    {\r
        LATBbits.LATB0 = ~LATBbits.LATB0;\r
\r
        if (irmp_get_data (&irmp_data))\r
        {\r
            // ir signal decoded, do something here...\r
            // irmp_data.protocol is the protocol, see irmp.h\r
            // irmp_data.address is the address/manufacturer code of ir sender\r
            // irmp_data.command is the command code\r
            // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
            printf("proto %d addr %d cmd %d\n", irmp_data.protocol, irmp_data.address, irmp_data.command );\r
        }\r
    }\r
}\r
\r
void interrupt high_priority high_isr(void)\r
{\r
    if (TMR2IF)\r
    {\r
        TMR2IF = 0;                                                         // clear Timer 0 interrupt flag\r
        irmp_ISR();\r
    }\r
}\r
\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
 * STM32:\r
 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
 */\r
#elif defined(ARM_STM32)\r
\r
uint32_t\r
SysCtlClockGet(void)\r
{\r
    RCC_ClocksTypeDef RCC_ClocksStatus;\r
    RCC_GetClocksFreq(&RCC_ClocksStatus);\r
    return RCC_ClocksStatus.SYSCLK_Frequency;\r
}\r
\r
void\r
timer2_init (void)\r
{\r
    TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;\r
    NVIC_InitTypeDef NVIC_InitStructure;\r
    RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);\r
\r
    TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;\r
    TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;\r
    TIM_TimeBaseStructure.TIM_Period = 7;\r
    TIM_TimeBaseStructure.TIM_Prescaler = ((F_CPU / F_INTERRUPTS)/8) - 1;\r
    TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);\r
\r
    TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);\r
\r
    NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;\r
    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;\r
    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;\r
    NVIC_Init(&NVIC_InitStructure);\r
\r
    TIM_Cmd(TIM2, ENABLE);\r
}\r
\r
void\r
TIM2_IRQHandler(void)                                                  // Timer2 Interrupt Handler\r
{\r
  TIM_ClearITPendingBit(TIM2, TIM_IT_Update);\r
  (void) irmp_ISR();                                                        // call irmp ISR\r
  // call other timer interrupt routines...\r
}\r
\r
int\r
main (void)\r
{\r
    IRMP_DATA irmp_data;\r
        \r
    irmp_init();                                                            // initialize irmp\r
    timer2_init();                                                          // initialize timer2\r
\r
    for (;;)\r
    {\r
        if (irmp_get_data (&irmp_data))\r
        {\r
            // ir signal decoded, do something here...\r
            // irmp_data.protocol is the protocol, see irmp.h\r
            // irmp_data.address is the address/manufacturer code of ir sender\r
            // irmp_data.command is the command code\r
            // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
        }\r
    }\r
}\r
#endif\r
Commit	Line	Data
4225a882	1	/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	2	* main.c - demo main module to test irmp decoder\r
	3	*\r
0834784c	4	* Copyright (c) 2009-2015 Frank Meyer - frank(at)fli4l.de\r
4225a882	5	*\r
ad4d3d41	6	* $Id: main.c,v 1.27 2015/02/27 10:19:20 fm Exp $\r
cb8474cc	7	*\r
775fabfa	8	* This demo module is runnable on AVRs and LM4F120 Launchpad (ARM Cortex M4)\r
4225a882	9	*\r
775fabfa	10	* ATMEGA88 @ 8 MHz internal RC Osc with BODLEVEL 4.3V: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9\r
775fabfa	11	* ATMEGA88 @ 8 MHz external Crystal Osc with BODLEVEL 4.3V: lfuse: 0xFF hfuse: 0xDC efuse: 0xF9\r
4225a882	12	*\r
	13	* This program is free software; you can redistribute it and/or modify\r
	14	* it under the terms of the GNU General Public License as published by\r
	15	* the Free Software Foundation; either version 2 of the License, or\r
	16	* (at your option) any later version.\r
	17	*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	18	*/\r
	19	\r
1f54e86c	20	#include "irmp.h"\r
4225a882	21	\r
4225a882	22	#ifndef F_CPU\r
061e654c	23	#error F_CPU unknown\r
4225a882	24	#endif\r
4225a882	25	\r
775fabfa	26	/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	27	* ATMEL AVR part:\r
	28	*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	29	*/\r
	30	#if defined (ATMEL_AVR)\r
	31	\r
622f5f59	32	#include "irmp.h"\r
	33	#define BAUD 9600L\r
	34	#include <util/setbaud.h>\r
	35	\r
	36	#ifdef UBRR0H\r
	37	\r
	38	#define UART0_UBRRH UBRR0H\r
	39	#define UART0_UBRRL UBRR0L\r
	40	#define UART0_UCSRA UCSR0A\r
	41	#define UART0_UCSRB UCSR0B\r
	42	#define UART0_UCSRC UCSR0C\r
	43	#define UART0_UDRE_BIT_VALUE (1<<UDRE0)\r
	44	#define UART0_UCSZ1_BIT_VALUE (1<<UCSZ01)\r
	45	#define UART0_UCSZ0_BIT_VALUE (1<<UCSZ00)\r
	46	#ifdef URSEL0\r
	47	#define UART0_URSEL_BIT_VALUE (1<<URSEL0)\r
	48	#else\r
	49	#define UART0_URSEL_BIT_VALUE (0)\r
	50	#endif\r
	51	#define UART0_TXEN_BIT_VALUE (1<<TXEN0)\r
	52	#define UART0_UDR UDR0\r
	53	#define UART0_U2X U2X0\r
061e654c	54	\r
622f5f59	55	#else\r
	56	\r
	57	#define UART0_UBRRH UBRRH\r
	58	#define UART0_UBRRL UBRRL\r
	59	#define UART0_UCSRA UCSRA\r
	60	#define UART0_UCSRB UCSRB\r
	61	#define UART0_UCSRC UCSRC\r
	62	#define UART0_UDRE_BIT_VALUE (1<<UDRE)\r
	63	#define UART0_UCSZ1_BIT_VALUE (1<<UCSZ1)\r
	64	#define UART0_UCSZ0_BIT_VALUE (1<<UCSZ0)\r
	65	#ifdef URSEL\r
	66	#define UART0_URSEL_BIT_VALUE (1<<URSEL)\r
	67	#else\r
	68	#define UART0_URSEL_BIT_VALUE (0)\r
	69	#endif\r
	70	#define UART0_TXEN_BIT_VALUE (1<<TXEN)\r
	71	#define UART0_UDR UDR\r
	72	#define UART0_U2X U2X\r
	73	\r
	74	#endif //UBRR0H\r
	75	\r
	76	static void\r
	77	uart_init (void)\r
	78	{\r
	79	UART0_UBRRH = UBRRH_VALUE; // set baud rate\r
	80	UART0_UBRRL = UBRRL_VALUE;\r
	81	\r
	82	#if USE_2X\r
	83	UART0_UCSRA \|= (1<<UART0_U2X);\r
	84	#else\r
	85	UART0_UCSRA &= ~(1<<UART0_U2X);\r
	86	#endif\r
	87	\r
	88	UART0_UCSRC = UART0_UCSZ1_BIT_VALUE \| UART0_UCSZ0_BIT_VALUE \| UART0_URSEL_BIT_VALUE;\r
	89	UART0_UCSRB \|= UART0_TXEN_BIT_VALUE; // enable UART TX\r
	90	}\r
	91	\r
	92	static void\r
	93	uart_putc (unsigned char ch)\r
	94	{\r
	95	while (!(UART0_UCSRA & UART0_UDRE_BIT_VALUE))\r
	96	{\r
	97	;\r
	98	}\r
	99	\r
	100	UART0_UDR = ch;\r
	101	}\r
	102	\r
	103	static void\r
	104	uart_puts (char * s)\r
	105	{\r
	106	while (*s)\r
	107	{\r
	108	uart_putc (*s);\r
	109	s++;\r
	110	}\r
	111	}\r
	112	\r
	113	static void\r
	114	uart_puts_P (PGM_P s)\r
	115	{\r
	116	uint8_t ch;\r
	117	\r
	118	while ((ch = pgm_read_byte(s)) != '\0')\r
119	{\r
120	uart_putc (ch);\r
121	s++;\r
122	}\r
123	}\r
124	\r
ad4d3d41	125	static char *\r
ad4d3d41	126	itoh (char * buf, uint8_t digits, uint16_t number)\r
622f5f59	127	{\r
ad4d3d41	128	for (buf[digits] = 0; digits--; number >>= 4)\r
622f5f59	129	{\r
ad4d3d41	130	buf[digits] = "0123456789ABCDEF"[number & 0x0F];\r
622f5f59	131	}\r
ad4d3d41	132	return buf;\r
622f5f59	133	}\r
	134	\r
	135	static void\r
1f54e86c	136	timer1_init (void)\r
4225a882	137	{\r
476267f4	138	#if defined (__AVR_ATtiny45__) \|\| defined (__AVR_ATtiny85__) // ATtiny45 / ATtiny85:\r
0f700c8e	139	\r
	140	#if F_CPU >= 16000000L\r
	141	OCR1C = (F_CPU / F_INTERRUPTS / 8) - 1; // compare value: 1/15000 of CPU frequency, presc = 8\r
	142	TCCR1 = (1 << CTC1) \| (1 << CS12); // switch CTC Mode on, set prescaler to 8\r
	143	#else\r
764bd2bc	144	OCR1C = (F_CPU / F_INTERRUPTS / 4) - 1; // compare value: 1/15000 of CPU frequency, presc = 4\r
7644ac04	145	TCCR1 = (1 << CTC1) \| (1 << CS11) \| (1 << CS10); // switch CTC Mode on, set prescaler to 4\r
0f700c8e	146	#endif\r
0f700c8e	147	\r
7644ac04	148	#else // ATmegaXX:\r
	149	OCR1A = (F_CPU / F_INTERRUPTS) - 1; // compare value: 1/15000 of CPU frequency\r
	150	TCCR1B = (1 << WGM12) \| (1 << CS10); // switch CTC Mode on, set prescaler to 1\r
1f54e86c	151	#endif\r
4225a882	152	\r
775fabfa	153	#ifdef TIMSK1\r
7644ac04	154	TIMSK1 = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
775fabfa	155	#else\r
7644ac04	156	TIMSK = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
1f54e86c	157	#endif\r
4225a882	158	}\r
4225a882	159	\r
7644ac04	160	#ifdef TIM1_COMPA_vect // ATtiny84\r
775fabfa	161	#define COMPA_VECT TIM1_COMPA_vect\r
7644ac04	162	#else\r
775fabfa	163	#define COMPA_VECT TIMER1_COMPA_vect // ATmega\r
7644ac04	164	#endif\r
775fabfa	165	\r
775fabfa	166	ISR(COMPA_VECT) // Timer1 output compare A interrupt service routine, called every 1/15000 sec\r
7644ac04	167	{\r
	168	(void) irmp_ISR(); // call irmp ISR\r
	169	// call other timer interrupt routines...\r
	170	}\r
	171	\r
775fabfa	172	int\r
	173	main (void)\r
	174	{\r
622f5f59	175	IRMP_DATA irmp_data;\r
622f5f59	176	char buf[3];\r
775fabfa	177	\r
	178	irmp_init(); // initialize irmp\r
	179	timer1_init(); // initialize timer1\r
622f5f59	180	uart_init(); // initialize uart\r
622f5f59	181	\r
775fabfa	182	sei (); // enable interrupts\r
	183	\r
	184	for (;;)\r
	185	{\r
	186	if (irmp_get_data (&irmp_data))\r
	187	{\r
622f5f59	188	uart_puts_P (PSTR("protocol: 0x"));\r
ad4d3d41	189	itoh (buf, 2, irmp_data.protocol);\r
622f5f59	190	uart_puts (buf);\r
	191	\r
	192	#if IRMP_PROTOCOL_NAMES == 1\r
	193	uart_puts_P (PSTR(" "));\r
f07dac6b	194	uart_puts_P (pgm_read_word (&(irmp_protocol_names[irmp_data.protocol])));\r
622f5f59	195	#endif\r
	196	\r
	197	uart_puts_P (PSTR(" address: 0x"));\r
ad4d3d41	198	itoh (buf, 4, irmp_data.address);\r
622f5f59	199	uart_puts (buf);\r
	200	\r
	201	uart_puts_P (PSTR(" command: 0x"));\r
ad4d3d41	202	itoh (buf, 4, irmp_data.command);\r
622f5f59	203	uart_puts (buf);\r
	204	\r
	205	uart_puts_P (PSTR(" flags: 0x"));\r
ad4d3d41	206	itoh (buf, 2, irmp_data.flags);\r
622f5f59	207	uart_puts (buf);\r
	208	\r
	209	uart_puts_P (PSTR("\r\n"));\r
775fabfa	210	}\r
	211	}\r
	212	}\r
	213	\r
	214	/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	215	* LM4F120 Launchpad (ARM Cortex M4):\r
	216	*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	217	*/\r
	218	#elif defined(STELLARIS_ARM_CORTEX_M4)\r
	219	\r
	220	void\r
	221	timer1_init (void)\r
	222	{\r
	223	SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);\r
	224	TimerConfigure(TIMER1_BASE, TIMER_CFG_32_BIT_PER);\r
	225	\r
	226	TimerLoadSet(TIMER1_BASE, TIMER_A, (F_CPU / F_INTERRUPTS) -1);\r
	227	IntEnable(INT_TIMER1A);\r
	228	TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);\r
	229	TimerEnable(TIMER1_BASE, TIMER_A);\r
	230	// Important: Timer1IntHandler has to be configured in startup_ccs.c !\r
	231	}\r
	232	\r
	233	void\r
	234	Timer1IntHandler(void) // Timer1 Interrupt Handler\r
	235	{\r
	236	(void) irmp_ISR(); // call irmp ISR\r
	237	// call other timer interrupt routines...\r
	238	}\r
7644ac04	239	\r
4225a882	240	int\r
	241	main (void)\r
	242	{\r
1f54e86c	243	IRMP_DATA irmp_data;\r
4225a882	244	\r
afd1e690	245	ROM_FPUEnable();\r
	246	ROM_FPUStackingEnable();\r
	247	ROM_SysCtlClockSet(SYSCTL_SYSDIV_5\|SYSCTL_USE_PLL\|SYSCTL_XTAL_16MHZ\|SYSCTL_OSC_MAIN);\r
afd1e690	248	\r
1f54e86c	249	irmp_init(); // initialize irmp\r
775fabfa	250	timer1_init(); // initialize timer1\r
1f54e86c	251	sei (); // enable interrupts\r
4225a882	252	\r
1f54e86c	253	for (;;)\r
4225a882	254	{\r
1f54e86c	255	if (irmp_get_data (&irmp_data))\r
	256	{\r
	257	// ir signal decoded, do something here...\r
	258	// irmp_data.protocol is the protocol, see irmp.h\r
	259	// irmp_data.address is the address/manufacturer code of ir sender\r
	260	// irmp_data.command is the command code\r
	261	// irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
	262	}\r
4225a882	263	}\r
4225a882	264	}\r
775fabfa	265	\r
4a7dc859	266	/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	267	* PIC18F4520 with XC8 compiler:\r
	268	*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	269	*/\r
	270	#elif defined (__XC8)\r
	271	\r
	272	#define _XTAL_FREQ 32000000UL // 32MHz clock\r
	273	#define FOSC _XTAL_FREQ\r
	274	#define FCY FOSC / 4UL // --> 8MHz\r
	275	\r
	276	#define BAUDRATE 19200UL\r
	277	#define BRG (( FCY 16 BAUDRATE ) -1UL)\r
	278	\r
	279	#include <stdio.h>\r
	280	#include <stdlib.h>\r
	281	\r
	282	int\r
	283	main (void)\r
	284	{\r
	285	IRMP_DATA irmp_data;\r
	286	\r
	287	irmp_init(); // initialize irmp\r
	288	\r
	289	// infinite loop, interrupts will blink PORTD pins and handle UART communications.\r
	290	while (1)\r
	291	{\r
	292	LATBbits.LATB0 = ~LATBbits.LATB0;\r
	293	\r
	294	if (irmp_get_data (&irmp_data))\r
	295	{\r
	296	// ir signal decoded, do something here...\r
	297	// irmp_data.protocol is the protocol, see irmp.h\r
	298	// irmp_data.address is the address/manufacturer code of ir sender\r
	299	// irmp_data.command is the command code\r
	300	// irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
	301	printf("proto %d addr %d cmd %d\n", irmp_data.protocol, irmp_data.address, irmp_data.command );\r
	302	}\r
	303	}\r
	304	}\r
	305	\r
	306	void interrupt high_priority high_isr(void)\r
	307	{\r
	308	if (TMR2IF)\r
	309	{\r
	310	TMR2IF = 0; // clear Timer 0 interrupt flag\r
	311	irmp_ISR();\r
	312	}\r
	313	}\r
	314	\r
622f5f59	315	/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	316	* STM32:\r
	317	*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	318	*/\r
	319	#elif defined(ARM_STM32)\r
	320	\r
	321	uint32_t\r
	322	SysCtlClockGet(void)\r
	323	{\r
	324	RCC_ClocksTypeDef RCC_ClocksStatus;\r
	325	RCC_GetClocksFreq(&RCC_ClocksStatus);\r
	326	return RCC_ClocksStatus.SYSCLK_Frequency;\r
	327	}\r
	328	\r
	329	void\r
	330	timer2_init (void)\r
	331	{\r
	332	TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;\r
	333	NVIC_InitTypeDef NVIC_InitStructure;\r
	334	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);\r
	335	\r
	336	TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;\r
	337	TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;\r
	338	TIM_TimeBaseStructure.TIM_Period = 7;\r
	339	TIM_TimeBaseStructure.TIM_Prescaler = ((F_CPU / F_INTERRUPTS)/8) - 1;\r
	340	TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);\r
	341	\r
	342	TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);\r
	343	\r
	344	NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;\r
	345	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
	346	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;\r
	347	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;\r
	348	NVIC_Init(&NVIC_InitStructure);\r
	349	\r
	350	TIM_Cmd(TIM2, ENABLE);\r
	351	}\r
	352	\r
	353	void\r
	354	TIM2_IRQHandler(void) // Timer2 Interrupt Handler\r
	355	{\r
	356	TIM_ClearITPendingBit(TIM2, TIM_IT_Update);\r
	357	(void) irmp_ISR(); // call irmp ISR\r
	358	// call other timer interrupt routines...\r
	359	}\r
	360	\r
	361	int\r
	362	main (void)\r
	363	{\r
	364	IRMP_DATA irmp_data;\r
	365	\r
	366	irmp_init(); // initialize irmp\r
	367	timer2_init(); // initialize timer2\r
	368	\r
	369	for (;;)\r
	370	{\r
	371	if (irmp_get_data (&irmp_data))\r
	372	{\r
	373	// ir signal decoded, do something here...\r
	374	// irmp_data.protocol is the protocol, see irmp.h\r
	375	// irmp_data.address is the address/manufacturer code of ir sender\r
	376	// irmp_data.command is the command code\r
	377	// irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
	378	}\r
379	}\r
380	}\r
775fabfa	381	#endif\r