[irmp.git] / irmp-main-avr-uart.c

/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
 * irmp-main-avr-uart.c - demo main module to test IRMP decoder on AVR with UART\r
 *\r
 * Copyright (c) 2009-2016 Frank Meyer - frank(at)fli4l.de\r
 *\r
 * $Id: irmp-main-avr-uart.c,v 1.4 2016/11/18 11:48:47 fm Exp $\r
 *\r
 * This demo module is runnable on AVRs with UART\r
 *\r
 * ATMEGA88 @ 8 MHz internal RC      Osc with BODLEVEL 4.3V: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9\r
 * ATMEGA88 @ 8 MHz external Crystal Osc with BODLEVEL 4.3V: lfuse: 0xFF hfuse: 0xDC efuse: 0xF9\r
 *\r
 * This program is free software; you can redistribute it and/or modify\r
 * it under the terms of the GNU General Public License as published by\r
 * the Free Software Foundation; either version 2 of the License, or\r
 * (at your option) any later version.\r
 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
 */\r
\r
#include "irmp.h"\r
\r
#ifndef F_CPU\r
#error F_CPU unknown\r
#endif\r
\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
 * ATMEL AVR part:\r
 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
 */\r
#define BAUD  9600L\r
#include <util/setbaud.h>\r
\r
#ifdef UBRR0H\r
\r
#define UART0_UBRRH                             UBRR0H\r
#define UART0_UBRRL                             UBRR0L\r
#define UART0_UCSRA                             UCSR0A\r
#define UART0_UCSRB                             UCSR0B\r
#define UART0_UCSRC                             UCSR0C\r
#define UART0_UDRE_BIT_VALUE                    (1<<UDRE0)\r
#define UART0_UCSZ1_BIT_VALUE                   (1<<UCSZ01)\r
#define UART0_UCSZ0_BIT_VALUE                   (1<<UCSZ00)\r
#ifdef URSEL0\r
#define UART0_URSEL_BIT_VALUE                   (1<<URSEL0)\r
#else\r
#define UART0_URSEL_BIT_VALUE                   (0)\r
#endif\r
#define UART0_TXEN_BIT_VALUE                    (1<<TXEN0)\r
#define UART0_UDR                               UDR0\r
#define UART0_U2X                               U2X0\r
\r
#else\r
\r
#define UART0_UBRRH                             UBRRH\r
#define UART0_UBRRL                             UBRRL\r
#define UART0_UCSRA                             UCSRA\r
#define UART0_UCSRB                             UCSRB\r
#define UART0_UCSRC                             UCSRC\r
#define UART0_UDRE_BIT_VALUE                    (1<<UDRE)\r
#define UART0_UCSZ1_BIT_VALUE                   (1<<UCSZ1)\r
#define UART0_UCSZ0_BIT_VALUE                   (1<<UCSZ0)\r
#ifdef URSEL\r
#define UART0_URSEL_BIT_VALUE                   (1<<URSEL)\r
#else\r
#define UART0_URSEL_BIT_VALUE                   (0)\r
#endif\r
#define UART0_TXEN_BIT_VALUE                    (1<<TXEN)\r
#define UART0_UDR                               UDR\r
#define UART0_U2X                               U2X\r
\r
#endif //UBRR0H\r
\r
static void\r
uart_init (void)\r
{\r
    UART0_UBRRH = UBRRH_VALUE;                                                                      // set baud rate\r
    UART0_UBRRL = UBRRL_VALUE;\r
\r
#if USE_2X\r
    UART0_UCSRA |= (1<<UART0_U2X);\r
#else\r
    UART0_UCSRA &= ~(1<<UART0_U2X);\r
#endif\r
\r
    UART0_UCSRC = UART0_UCSZ1_BIT_VALUE | UART0_UCSZ0_BIT_VALUE | UART0_URSEL_BIT_VALUE;\r
    UART0_UCSRB |= UART0_TXEN_BIT_VALUE;                                                            // enable UART TX\r
}\r
\r
static void\r
uart_putc (unsigned char ch)\r
{\r
    while (!(UART0_UCSRA & UART0_UDRE_BIT_VALUE))\r
    {\r
        ;\r
    }\r
\r
    UART0_UDR = ch;\r
}\r
\r
static void\r
uart_puts (char * s)\r
{\r
    while (*s)\r
    {\r
        uart_putc (*s);\r
        s++;\r
    }\r
}\r
\r
static void\r
uart_puts_P (PGM_P s)\r
{\r
    uint8_t ch;\r
\r
    while ((ch = pgm_read_byte(s)) != '\0')\r
    {\r
        uart_putc (ch);\r
        s++;\r
    }\r
}\r
\r
static char *\r
itoh (char * buf, uint8_t digits, uint16_t number)\r
{\r
    for (buf[digits] = 0; digits--; number >>= 4)\r
    {\r
        buf[digits] = "0123456789ABCDEF"[number & 0x0F];\r
    }\r
    return buf;\r
}\r
\r
static void\r
timer1_init (void)\r
{\r
#if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__)                // ATtiny45 / ATtiny85:\r
\r
#if F_CPU >= 16000000L\r
    OCR1C   =  (F_CPU / F_INTERRUPTS / 8) - 1;                              // compare value: 1/15000 of CPU frequency, presc = 8\r
    TCCR1   = (1 << CTC1) | (1 << CS12);                                    // switch CTC Mode on, set prescaler to 8\r
#else\r
    OCR1C   =  (F_CPU / F_INTERRUPTS / 4) - 1;                              // compare value: 1/15000 of CPU frequency, presc = 4\r
    TCCR1   = (1 << CTC1) | (1 << CS11) | (1 << CS10);                      // switch CTC Mode on, set prescaler to 4\r
#endif\r
\r
#else                                                                       // ATmegaXX:\r
    OCR1A   =  (F_CPU / F_INTERRUPTS) - 1;                                  // compare value: 1/15000 of CPU frequency\r
    TCCR1B  = (1 << WGM12) | (1 << CS10);                                   // switch CTC Mode on, set prescaler to 1\r
#endif\r
\r
#ifdef TIMSK1\r
    TIMSK1  = 1 << OCIE1A;                                                  // OCIE1A: Interrupt by timer compare\r
#else\r
    TIMSK   = 1 << OCIE1A;                                                  // OCIE1A: Interrupt by timer compare\r
#endif\r
}\r
\r
#ifdef TIM1_COMPA_vect                                                      // ATtiny84\r
#define COMPA_VECT  TIM1_COMPA_vect\r
#else\r
#define COMPA_VECT  TIMER1_COMPA_vect                                       // ATmega\r
#endif\r
\r
ISR(COMPA_VECT)                                                             // Timer1 output compare A interrupt service routine, called every 1/15000 sec\r
{\r
  (void) irmp_ISR();                                                        // call irmp ISR\r
  // call other timer interrupt routines...\r
}\r
\r
int\r
main (void)\r
{\r
    IRMP_DATA   irmp_data;\r
    char        buf[5];\r
\r
    irmp_init();                                                            // initialize irmp\r
    timer1_init();                                                          // initialize timer1\r
    uart_init();                                                            // initialize uart\r
\r
    sei ();                                                                 // enable interrupts\r
\r
    for (;;)\r
    {\r
        if (irmp_get_data (&irmp_data))\r
        {\r
            uart_puts_P (PSTR("protocol: 0x"));\r
            itoh (buf, 2, irmp_data.protocol);\r
            uart_puts (buf);\r
\r
#if IRMP_PROTOCOL_NAMES == 1\r
            uart_puts_P (PSTR("   "));\r
            uart_puts_P (pgm_read_word (&(irmp_protocol_names[irmp_data.protocol])));\r
#endif\r
\r
            uart_puts_P (PSTR("   address: 0x"));\r
            itoh (buf, 4, irmp_data.address);\r
            uart_puts (buf);\r
\r
            uart_puts_P (PSTR("   command: 0x"));\r
            itoh (buf, 4, irmp_data.command);\r
            uart_puts (buf);\r
\r
            uart_puts_P (PSTR("   flags: 0x"));\r
            itoh (buf, 2, irmp_data.flags);\r
            uart_puts (buf);\r
\r
            uart_puts_P (PSTR("\r\n"));\r
        }\r
    }\r
}\r
Commit	Line	Data
4225a882	1	/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
7365350c	2	* irmp-main-avr-uart.c - demo main module to test IRMP decoder on AVR with UART\r
4225a882	3	*\r
ea29682a	4	* Copyright (c) 2009-2016 Frank Meyer - frank(at)fli4l.de\r
4225a882	5	*\r
17cabd54	6	* $Id: irmp-main-avr-uart.c,v 1.4 2016/11/18 11:48:47 fm Exp $\r
cb8474cc	7	*\r
ea29682a	8	* This demo module is runnable on AVRs with UART\r
4225a882	9	*\r
775fabfa	10	* ATMEGA88 @ 8 MHz internal RC Osc with BODLEVEL 4.3V: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9\r
775fabfa	11	* ATMEGA88 @ 8 MHz external Crystal Osc with BODLEVEL 4.3V: lfuse: 0xFF hfuse: 0xDC efuse: 0xF9\r
4225a882	12	*\r
	13	* This program is free software; you can redistribute it and/or modify\r
	14	* it under the terms of the GNU General Public License as published by\r
	15	* the Free Software Foundation; either version 2 of the License, or\r
	16	* (at your option) any later version.\r
	17	*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	18	*/\r
	19	\r
1f54e86c	20	#include "irmp.h"\r
4225a882	21	\r
4225a882	22	#ifndef F_CPU\r
061e654c	23	#error F_CPU unknown\r
4225a882	24	#endif\r
4225a882	25	\r
775fabfa	26	/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	27	* ATMEL AVR part:\r
	28	*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	29	*/\r
622f5f59	30	#define BAUD 9600L\r
	31	#include <util/setbaud.h>\r
	32	\r
	33	#ifdef UBRR0H\r
	34	\r
	35	#define UART0_UBRRH UBRR0H\r
	36	#define UART0_UBRRL UBRR0L\r
	37	#define UART0_UCSRA UCSR0A\r
	38	#define UART0_UCSRB UCSR0B\r
	39	#define UART0_UCSRC UCSR0C\r
	40	#define UART0_UDRE_BIT_VALUE (1<<UDRE0)\r
	41	#define UART0_UCSZ1_BIT_VALUE (1<<UCSZ01)\r
	42	#define UART0_UCSZ0_BIT_VALUE (1<<UCSZ00)\r
	43	#ifdef URSEL0\r
	44	#define UART0_URSEL_BIT_VALUE (1<<URSEL0)\r
	45	#else\r
	46	#define UART0_URSEL_BIT_VALUE (0)\r
	47	#endif\r
	48	#define UART0_TXEN_BIT_VALUE (1<<TXEN0)\r
	49	#define UART0_UDR UDR0\r
	50	#define UART0_U2X U2X0\r
061e654c	51	\r
622f5f59	52	#else\r
	53	\r
	54	#define UART0_UBRRH UBRRH\r
	55	#define UART0_UBRRL UBRRL\r
	56	#define UART0_UCSRA UCSRA\r
	57	#define UART0_UCSRB UCSRB\r
	58	#define UART0_UCSRC UCSRC\r
	59	#define UART0_UDRE_BIT_VALUE (1<<UDRE)\r
	60	#define UART0_UCSZ1_BIT_VALUE (1<<UCSZ1)\r
	61	#define UART0_UCSZ0_BIT_VALUE (1<<UCSZ0)\r
	62	#ifdef URSEL\r
	63	#define UART0_URSEL_BIT_VALUE (1<<URSEL)\r
	64	#else\r
	65	#define UART0_URSEL_BIT_VALUE (0)\r
	66	#endif\r
	67	#define UART0_TXEN_BIT_VALUE (1<<TXEN)\r
	68	#define UART0_UDR UDR\r
	69	#define UART0_U2X U2X\r
	70	\r
	71	#endif //UBRR0H\r
	72	\r
	73	static void\r
	74	uart_init (void)\r
	75	{\r
	76	UART0_UBRRH = UBRRH_VALUE; // set baud rate\r
	77	UART0_UBRRL = UBRRL_VALUE;\r
	78	\r
	79	#if USE_2X\r
	80	UART0_UCSRA \|= (1<<UART0_U2X);\r
	81	#else\r
	82	UART0_UCSRA &= ~(1<<UART0_U2X);\r
	83	#endif\r
	84	\r
	85	UART0_UCSRC = UART0_UCSZ1_BIT_VALUE \| UART0_UCSZ0_BIT_VALUE \| UART0_URSEL_BIT_VALUE;\r
	86	UART0_UCSRB \|= UART0_TXEN_BIT_VALUE; // enable UART TX\r
	87	}\r
	88	\r
	89	static void\r
	90	uart_putc (unsigned char ch)\r
	91	{\r
	92	while (!(UART0_UCSRA & UART0_UDRE_BIT_VALUE))\r
	93	{\r
	94	;\r
	95	}\r
	96	\r
	97	UART0_UDR = ch;\r
	98	}\r
	99	\r
	100	static void\r
	101	uart_puts (char * s)\r
	102	{\r
	103	while (*s)\r
	104	{\r
	105	uart_putc (*s);\r
	106	s++;\r
	107	}\r
	108	}\r
	109	\r
	110	static void\r
	111	uart_puts_P (PGM_P s)\r
	112	{\r
	113	uint8_t ch;\r
	114	\r
	115	while ((ch = pgm_read_byte(s)) != '\0')\r
116	{\r
117	uart_putc (ch);\r
118	s++;\r
119	}\r
120	}\r
121	\r
ad4d3d41	122	static char *\r
ad4d3d41	123	itoh (char * buf, uint8_t digits, uint16_t number)\r
622f5f59	124	{\r
ad4d3d41	125	for (buf[digits] = 0; digits--; number >>= 4)\r
622f5f59	126	{\r
ad4d3d41	127	buf[digits] = "0123456789ABCDEF"[number & 0x0F];\r
622f5f59	128	}\r
ad4d3d41	129	return buf;\r
622f5f59	130	}\r
	131	\r
	132	static void\r
1f54e86c	133	timer1_init (void)\r
4225a882	134	{\r
476267f4	135	#if defined (__AVR_ATtiny45__) \|\| defined (__AVR_ATtiny85__) // ATtiny45 / ATtiny85:\r
0f700c8e	136	\r
	137	#if F_CPU >= 16000000L\r
	138	OCR1C = (F_CPU / F_INTERRUPTS / 8) - 1; // compare value: 1/15000 of CPU frequency, presc = 8\r
	139	TCCR1 = (1 << CTC1) \| (1 << CS12); // switch CTC Mode on, set prescaler to 8\r
	140	#else\r
764bd2bc	141	OCR1C = (F_CPU / F_INTERRUPTS / 4) - 1; // compare value: 1/15000 of CPU frequency, presc = 4\r
7644ac04	142	TCCR1 = (1 << CTC1) \| (1 << CS11) \| (1 << CS10); // switch CTC Mode on, set prescaler to 4\r
0f700c8e	143	#endif\r
0f700c8e	144	\r
7644ac04	145	#else // ATmegaXX:\r
	146	OCR1A = (F_CPU / F_INTERRUPTS) - 1; // compare value: 1/15000 of CPU frequency\r
	147	TCCR1B = (1 << WGM12) \| (1 << CS10); // switch CTC Mode on, set prescaler to 1\r
1f54e86c	148	#endif\r
4225a882	149	\r
775fabfa	150	#ifdef TIMSK1\r
7644ac04	151	TIMSK1 = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
775fabfa	152	#else\r
7644ac04	153	TIMSK = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
1f54e86c	154	#endif\r
4225a882	155	}\r
4225a882	156	\r
7644ac04	157	#ifdef TIM1_COMPA_vect // ATtiny84\r
775fabfa	158	#define COMPA_VECT TIM1_COMPA_vect\r
7644ac04	159	#else\r
775fabfa	160	#define COMPA_VECT TIMER1_COMPA_vect // ATmega\r
7644ac04	161	#endif\r
775fabfa	162	\r
775fabfa	163	ISR(COMPA_VECT) // Timer1 output compare A interrupt service routine, called every 1/15000 sec\r
7644ac04	164	{\r
	165	(void) irmp_ISR(); // call irmp ISR\r
	166	// call other timer interrupt routines...\r
	167	}\r
	168	\r
775fabfa	169	int\r
	170	main (void)\r
	171	{\r
622f5f59	172	IRMP_DATA irmp_data;\r
17cabd54	173	char buf[5];\r
775fabfa	174	\r
	175	irmp_init(); // initialize irmp\r
	176	timer1_init(); // initialize timer1\r
622f5f59	177	uart_init(); // initialize uart\r
622f5f59	178	\r
775fabfa	179	sei (); // enable interrupts\r
	180	\r
	181	for (;;)\r
	182	{\r
	183	if (irmp_get_data (&irmp_data))\r
	184	{\r
622f5f59	185	uart_puts_P (PSTR("protocol: 0x"));\r
ad4d3d41	186	itoh (buf, 2, irmp_data.protocol);\r
622f5f59	187	uart_puts (buf);\r
	188	\r
	189	#if IRMP_PROTOCOL_NAMES == 1\r
	190	uart_puts_P (PSTR(" "));\r
f07dac6b	191	uart_puts_P (pgm_read_word (&(irmp_protocol_names[irmp_data.protocol])));\r
622f5f59	192	#endif\r
	193	\r
	194	uart_puts_P (PSTR(" address: 0x"));\r
ad4d3d41	195	itoh (buf, 4, irmp_data.address);\r
622f5f59	196	uart_puts (buf);\r
	197	\r
	198	uart_puts_P (PSTR(" command: 0x"));\r
ad4d3d41	199	itoh (buf, 4, irmp_data.command);\r
622f5f59	200	uart_puts (buf);\r
	201	\r
	202	uart_puts_P (PSTR(" flags: 0x"));\r
ad4d3d41	203	itoh (buf, 2, irmp_data.flags);\r
622f5f59	204	uart_puts (buf);\r
	205	\r
	206	uart_puts_P (PSTR("\r\n"));\r
775fabfa	207	}\r
	208	}\r
	209	}\r