[irmp.git] / main.c

/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
 * main.c - demo main module to test irmp decoder\r
 *\r
 * Copyright (c) 2009-2014 Frank Meyer - frank(at)fli4l.de\r
 *\r
 * $Id: main.c,v 1.20 2014/09/15 10:27:38 fm Exp $\r
 *\r
 * This demo module is runnable on AVRs and LM4F120 Launchpad (ARM Cortex M4)\r
 *\r
 * ATMEGA88 @ 8 MHz internal RC      Osc with BODLEVEL 4.3V: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9\r
 * ATMEGA88 @ 8 MHz external Crystal Osc with BODLEVEL 4.3V: lfuse: 0xFF hfuse: 0xDC efuse: 0xF9\r
 *\r
 * This program is free software; you can redistribute it and/or modify\r
 * it under the terms of the GNU General Public License as published by\r
 * the Free Software Foundation; either version 2 of the License, or\r
 * (at your option) any later version.\r
 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
 */\r
\r
#include "irmp.h"\r
\r
#ifndef F_CPU\r
#error F_CPU unkown\r
#endif\r
\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
 * ATMEL AVR part:\r
 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
 */\r
#if defined (ATMEL_AVR)\r
\r
#include "irmp.h"\r
#define BAUD  9600L\r
#include <util/setbaud.h>\r
\r
#ifdef UBRR0H\r
\r
#define UART0_UBRRH                             UBRR0H\r
#define UART0_UBRRL                             UBRR0L\r
#define UART0_UCSRA                             UCSR0A\r
#define UART0_UCSRB                             UCSR0B\r
#define UART0_UCSRC                             UCSR0C\r
#define UART0_UDRE_BIT_VALUE                    (1<<UDRE0)\r
#define UART0_UCSZ1_BIT_VALUE                   (1<<UCSZ01)\r
#define UART0_UCSZ0_BIT_VALUE                   (1<<UCSZ00)\r
#ifdef URSEL0\r
#define UART0_URSEL_BIT_VALUE                   (1<<URSEL0)\r
#else\r
#define UART0_URSEL_BIT_VALUE                   (0)\r
#endif\r
#define UART0_TXEN_BIT_VALUE                    (1<<TXEN0)\r
#define UART0_UDR                               UDR0\r
#define UART0_U2X                               U2X0\r
        \r
#else\r
\r
#define UART0_UBRRH                             UBRRH\r
#define UART0_UBRRL                             UBRRL\r
#define UART0_UCSRA                             UCSRA\r
#define UART0_UCSRB                             UCSRB\r
#define UART0_UCSRC                             UCSRC\r
#define UART0_UDRE_BIT_VALUE                    (1<<UDRE)\r
#define UART0_UCSZ1_BIT_VALUE                   (1<<UCSZ1)\r
#define UART0_UCSZ0_BIT_VALUE                   (1<<UCSZ0)\r
#ifdef URSEL\r
#define UART0_URSEL_BIT_VALUE                   (1<<URSEL)\r
#else\r
#define UART0_URSEL_BIT_VALUE                   (0)\r
#endif\r
#define UART0_TXEN_BIT_VALUE                    (1<<TXEN)\r
#define UART0_UDR                               UDR\r
#define UART0_U2X                               U2X\r
\r
#endif //UBRR0H\r
\r
static void\r
uart_init (void)\r
{\r
    UART0_UBRRH = UBRRH_VALUE;                                                                      // set baud rate\r
    UART0_UBRRL = UBRRL_VALUE;\r
\r
#if USE_2X\r
    UART0_UCSRA |= (1<<UART0_U2X);\r
#else\r
    UART0_UCSRA &= ~(1<<UART0_U2X);\r
#endif\r
\r
    UART0_UCSRC = UART0_UCSZ1_BIT_VALUE | UART0_UCSZ0_BIT_VALUE | UART0_URSEL_BIT_VALUE;\r
    UART0_UCSRB |= UART0_TXEN_BIT_VALUE;                                                            // enable UART TX\r
}\r
\r
static void\r
uart_putc (unsigned char ch)\r
{\r
    while (!(UART0_UCSRA & UART0_UDRE_BIT_VALUE))\r
    {\r
        ;\r
    }\r
\r
    UART0_UDR = ch;\r
}\r
\r
static void\r
uart_puts (char * s)\r
{\r
    while (*s)\r
    {\r
        uart_putc (*s);\r
        s++;\r
    }\r
}\r
\r
static void\r
uart_puts_P (PGM_P s)\r
{\r
    uint8_t ch;\r
\r
    while ((ch = pgm_read_byte(s)) != '\0')\r
    {\r
        uart_putc (ch);\r
        s++;\r
    }\r
}\r
\r
static uint8_t\r
itox (uint8_t val)\r
{\r
    uint8_t rtc;\r
\r
    val &= 0x0F;\r
\r
    if (val <= 9)\r
    {\r
        rtc = val + '0';\r
    }\r
    else\r
    {\r
        rtc = val - 10 + 'A';\r
    }\r
    return (rtc);\r
}\r
\r
static void\r
itoxx (char * xx, unsigned char i)\r
{\r
    *xx++ = itox (i >> 4);\r
    *xx++ = itox (i & 0x0F);\r
    *xx = '\0';\r
}\r
\r
static void\r
timer1_init (void)\r
{\r
#if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__)                // ATtiny45 / ATtiny85:\r
\r
#if F_CPU >= 16000000L\r
    OCR1C   =  (F_CPU / F_INTERRUPTS / 8) - 1;                              // compare value: 1/15000 of CPU frequency, presc = 8\r
    TCCR1   = (1 << CTC1) | (1 << CS12);                                    // switch CTC Mode on, set prescaler to 8\r
#else\r
    OCR1C   =  (F_CPU / F_INTERRUPTS / 4) - 1;                              // compare value: 1/15000 of CPU frequency, presc = 4\r
    TCCR1   = (1 << CTC1) | (1 << CS11) | (1 << CS10);                      // switch CTC Mode on, set prescaler to 4\r
#endif\r
\r
#else                                                                       // ATmegaXX:\r
    OCR1A   =  (F_CPU / F_INTERRUPTS) - 1;                                  // compare value: 1/15000 of CPU frequency\r
    TCCR1B  = (1 << WGM12) | (1 << CS10);                                   // switch CTC Mode on, set prescaler to 1\r
#endif\r
\r
#ifdef TIMSK1\r
    TIMSK1  = 1 << OCIE1A;                                                  // OCIE1A: Interrupt by timer compare\r
#else\r
    TIMSK   = 1 << OCIE1A;                                                  // OCIE1A: Interrupt by timer compare\r
#endif\r
}\r
\r
#ifdef TIM1_COMPA_vect                                                      // ATtiny84\r
#define COMPA_VECT  TIM1_COMPA_vect\r
#else\r
#define COMPA_VECT  TIMER1_COMPA_vect                                       // ATmega\r
#endif\r
\r
ISR(COMPA_VECT)                                                             // Timer1 output compare A interrupt service routine, called every 1/15000 sec\r
{\r
  (void) irmp_ISR();                                                        // call irmp ISR\r
  // call other timer interrupt routines...\r
}\r
\r
int\r
main (void)\r
{\r
    IRMP_DATA   irmp_data;\r
    char        buf[3];\r
\r
    irmp_init();                                                            // initialize irmp\r
    timer1_init();                                                          // initialize timer1\r
    uart_init();                                                            // initialize uart\r
\r
    sei ();                                                                 // enable interrupts\r
\r
    for (;;)\r
    {\r
        if (irmp_get_data (&irmp_data))\r
        {\r
            uart_puts_P (PSTR("protocol: 0x"));\r
            itoxx (buf, irmp_data.protocol);\r
            uart_puts (buf);\r
\r
#if IRMP_PROTOCOL_NAMES == 1\r
            uart_puts_P (PSTR("   "));\r
            uart_puts_P (irmp_protocol_names[irmp_data.protocol]);\r
#endif\r
\r
            uart_puts_P (PSTR("   address: 0x"));\r
            itoxx (buf, irmp_data.address >> 8);\r
            uart_puts (buf);\r
            itoxx (buf, irmp_data.address & 0xFF);\r
            uart_puts (buf);\r
\r
            uart_puts_P (PSTR("   command: 0x"));\r
            itoxx (buf, irmp_data.command >> 8);\r
            uart_puts (buf);\r
            itoxx (buf, irmp_data.command & 0xFF);\r
            uart_puts (buf);\r
\r
            uart_puts_P (PSTR("   flags: 0x"));\r
            itoxx (buf, irmp_data.flags);\r
            uart_puts (buf);\r
\r
            uart_puts_P (PSTR("\r\n"));\r
        }\r
    }\r
}\r
\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
 * LM4F120 Launchpad (ARM Cortex M4):\r
 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
 */\r
#elif defined(STELLARIS_ARM_CORTEX_M4)\r
\r
void\r
timer1_init (void)\r
{\r
    SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);\r
    TimerConfigure(TIMER1_BASE, TIMER_CFG_32_BIT_PER);\r
\r
    TimerLoadSet(TIMER1_BASE, TIMER_A, (F_CPU / F_INTERRUPTS) -1);\r
    IntEnable(INT_TIMER1A);\r
    TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);\r
    TimerEnable(TIMER1_BASE, TIMER_A);\r
    // Important: Timer1IntHandler has to be configured in startup_ccs.c !\r
}\r
\r
void\r
Timer1IntHandler(void)                                                      // Timer1 Interrupt Handler\r
{\r
  (void) irmp_ISR();                                                        // call irmp ISR\r
  // call other timer interrupt routines...\r
}\r
\r
int\r
main (void)\r
{\r
    IRMP_DATA irmp_data;\r
\r
    ROM_FPUEnable();\r
    ROM_FPUStackingEnable();\r
    ROM_SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);\r
\r
    irmp_init();                                                            // initialize irmp\r
    timer1_init();                                                          // initialize timer1\r
    sei ();                                                                 // enable interrupts\r
\r
    for (;;)\r
    {\r
        if (irmp_get_data (&irmp_data))\r
        {\r
            // ir signal decoded, do something here...\r
            // irmp_data.protocol is the protocol, see irmp.h\r
            // irmp_data.address is the address/manufacturer code of ir sender\r
            // irmp_data.command is the command code\r
            // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
        }\r
    }\r
}\r
\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
 * PIC18F4520 with XC8 compiler:\r
 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
 */\r
#elif defined (__XC8)\r
\r
#define _XTAL_FREQ  32000000UL                                              // 32MHz clock\r
#define FOSC        _XTAL_FREQ\r
#define FCY         FOSC / 4UL                                              // --> 8MHz\r
\r
#define BAUDRATE 19200UL\r
#define BRG (( FCY  16  BAUDRATE ) -1UL)\r
\r
#include <stdio.h>\r
#include <stdlib.h>\r
\r
int\r
main (void)\r
{\r
    IRMP_DATA irmp_data;\r
\r
    irmp_init();                                                            // initialize irmp\r
\r
    // infinite loop, interrupts will blink PORTD pins and handle UART communications.\r
    while (1)\r
    {\r
        LATBbits.LATB0 = ~LATBbits.LATB0;\r
\r
        if (irmp_get_data (&irmp_data))\r
        {\r
            // ir signal decoded, do something here...\r
            // irmp_data.protocol is the protocol, see irmp.h\r
            // irmp_data.address is the address/manufacturer code of ir sender\r
            // irmp_data.command is the command code\r
            // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
            printf("proto %d addr %d cmd %d\n", irmp_data.protocol, irmp_data.address, irmp_data.command );\r
        }\r
    }\r
}\r
\r
void interrupt high_priority high_isr(void)\r
{\r
    if (TMR2IF)\r
    {\r
        TMR2IF = 0;                                                         // clear Timer 0 interrupt flag\r
        irmp_ISR();\r
    }\r
}\r
\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
 * STM32:\r
 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
 */\r
#elif defined(ARM_STM32)\r
\r
uint32_t\r
SysCtlClockGet(void)\r
{\r
    RCC_ClocksTypeDef RCC_ClocksStatus;\r
    RCC_GetClocksFreq(&RCC_ClocksStatus);\r
    return RCC_ClocksStatus.SYSCLK_Frequency;\r
}\r
\r
void\r
timer2_init (void)\r
{\r
    TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;\r
    NVIC_InitTypeDef NVIC_InitStructure;\r
    RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);\r
\r
    TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;\r
    TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;\r
    TIM_TimeBaseStructure.TIM_Period = 7;\r
    TIM_TimeBaseStructure.TIM_Prescaler = ((F_CPU / F_INTERRUPTS)/8) - 1;\r
    TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);\r
\r
    TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);\r
\r
    NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;\r
    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;\r
    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;\r
    NVIC_Init(&NVIC_InitStructure);\r
\r
    TIM_Cmd(TIM2, ENABLE);\r
}\r
\r
void\r
TIM2_IRQHandler(void)                                                  // Timer2 Interrupt Handler\r
{\r
  TIM_ClearITPendingBit(TIM2, TIM_IT_Update);\r
  (void) irmp_ISR();                                                        // call irmp ISR\r
  // call other timer interrupt routines...\r
}\r
\r
int\r
main (void)\r
{\r
    IRMP_DATA irmp_data;\r
        \r
    irmp_init();                                                            // initialize irmp\r
    timer2_init();                                                          // initialize timer2\r
\r
    for (;;)\r
    {\r
        if (irmp_get_data (&irmp_data))\r
        {\r
            // ir signal decoded, do something here...\r
            // irmp_data.protocol is the protocol, see irmp.h\r
            // irmp_data.address is the address/manufacturer code of ir sender\r
            // irmp_data.command is the command code\r
            // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
        }\r
    }\r
}\r
#endif\r
Commit	Line	Data
4225a882	1	/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	2	* main.c - demo main module to test irmp decoder\r
	3	*\r
7fe8188d	4	* Copyright (c) 2009-2014 Frank Meyer - frank(at)fli4l.de\r
4225a882	5	*\r
622f5f59	6	* $Id: main.c,v 1.20 2014/09/15 10:27:38 fm Exp $\r
cb8474cc	7	*\r
775fabfa	8	* This demo module is runnable on AVRs and LM4F120 Launchpad (ARM Cortex M4)\r
4225a882	9	*\r
775fabfa	10	* ATMEGA88 @ 8 MHz internal RC Osc with BODLEVEL 4.3V: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9\r
775fabfa	11	* ATMEGA88 @ 8 MHz external Crystal Osc with BODLEVEL 4.3V: lfuse: 0xFF hfuse: 0xDC efuse: 0xF9\r
4225a882	12	*\r
	13	* This program is free software; you can redistribute it and/or modify\r
	14	* it under the terms of the GNU General Public License as published by\r
	15	* the Free Software Foundation; either version 2 of the License, or\r
	16	* (at your option) any later version.\r
	17	*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	18	*/\r
	19	\r
1f54e86c	20	#include "irmp.h"\r
4225a882	21	\r
	22	#ifndef F_CPU\r
	23	#error F_CPU unkown\r
	24	#endif\r
	25	\r
775fabfa	26	/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	27	* ATMEL AVR part:\r
	28	*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	29	*/\r
	30	#if defined (ATMEL_AVR)\r
	31	\r
622f5f59	32	#include "irmp.h"\r
	33	#define BAUD 9600L\r
	34	#include <util/setbaud.h>\r
	35	\r
	36	#ifdef UBRR0H\r
	37	\r
	38	#define UART0_UBRRH UBRR0H\r
	39	#define UART0_UBRRL UBRR0L\r
	40	#define UART0_UCSRA UCSR0A\r
	41	#define UART0_UCSRB UCSR0B\r
	42	#define UART0_UCSRC UCSR0C\r
	43	#define UART0_UDRE_BIT_VALUE (1<<UDRE0)\r
	44	#define UART0_UCSZ1_BIT_VALUE (1<<UCSZ01)\r
	45	#define UART0_UCSZ0_BIT_VALUE (1<<UCSZ00)\r
	46	#ifdef URSEL0\r
	47	#define UART0_URSEL_BIT_VALUE (1<<URSEL0)\r
	48	#else\r
	49	#define UART0_URSEL_BIT_VALUE (0)\r
	50	#endif\r
	51	#define UART0_TXEN_BIT_VALUE (1<<TXEN0)\r
	52	#define UART0_UDR UDR0\r
	53	#define UART0_U2X U2X0\r
	54	\r
	55	#else\r
	56	\r
	57	#define UART0_UBRRH UBRRH\r
	58	#define UART0_UBRRL UBRRL\r
	59	#define UART0_UCSRA UCSRA\r
	60	#define UART0_UCSRB UCSRB\r
	61	#define UART0_UCSRC UCSRC\r
	62	#define UART0_UDRE_BIT_VALUE (1<<UDRE)\r
	63	#define UART0_UCSZ1_BIT_VALUE (1<<UCSZ1)\r
	64	#define UART0_UCSZ0_BIT_VALUE (1<<UCSZ0)\r
	65	#ifdef URSEL\r
	66	#define UART0_URSEL_BIT_VALUE (1<<URSEL)\r
	67	#else\r
	68	#define UART0_URSEL_BIT_VALUE (0)\r
	69	#endif\r
	70	#define UART0_TXEN_BIT_VALUE (1<<TXEN)\r
	71	#define UART0_UDR UDR\r
	72	#define UART0_U2X U2X\r
	73	\r
	74	#endif //UBRR0H\r
	75	\r
	76	static void\r
	77	uart_init (void)\r
	78	{\r
	79	UART0_UBRRH = UBRRH_VALUE; // set baud rate\r
	80	UART0_UBRRL = UBRRL_VALUE;\r
	81	\r
	82	#if USE_2X\r
	83	UART0_UCSRA \|= (1<<UART0_U2X);\r
	84	#else\r
	85	UART0_UCSRA &= ~(1<<UART0_U2X);\r
	86	#endif\r
	87	\r
	88	UART0_UCSRC = UART0_UCSZ1_BIT_VALUE \| UART0_UCSZ0_BIT_VALUE \| UART0_URSEL_BIT_VALUE;\r
	89	UART0_UCSRB \|= UART0_TXEN_BIT_VALUE; // enable UART TX\r
	90	}\r
	91	\r
	92	static void\r
	93	uart_putc (unsigned char ch)\r
	94	{\r
	95	while (!(UART0_UCSRA & UART0_UDRE_BIT_VALUE))\r
96	{\r
97	;\r
98	}\r
99	\r
100	UART0_UDR = ch;\r
101	}\r
102	\r
103	static void\r
104	uart_puts (char * s)\r
105	{\r
106	while (*s)\r
107	{\r
108	uart_putc (*s);\r
109	s++;\r
110	}\r
111	}\r
112	\r
113	static void\r
114	uart_puts_P (PGM_P s)\r
115	{\r
116	uint8_t ch;\r
117	\r
118	while ((ch = pgm_read_byte(s)) != '\0')\r
119	{\r
120	uart_putc (ch);\r
121	s++;\r
122	}\r
123	}\r
124	\r
125	static uint8_t\r
126	itox (uint8_t val)\r
127	{\r
128	uint8_t rtc;\r
129	\r
130	val &= 0x0F;\r
131	\r
132	if (val <= 9)\r
133	{\r
134	rtc = val + '0';\r
135	}\r
136	else\r
137	{\r
138	rtc = val - 10 + 'A';\r
139	}\r
140	return (rtc);\r
141	}\r
142	\r
143	static void\r
144	itoxx (char * xx, unsigned char i)\r
145	{\r
146	*xx++ = itox (i >> 4);\r
147	*xx++ = itox (i & 0x0F);\r
148	*xx = '\0';\r
149	}\r
150	\r
151	static void\r
1f54e86c	152	timer1_init (void)\r
4225a882	153	{\r
476267f4	154	#if defined (__AVR_ATtiny45__) \|\| defined (__AVR_ATtiny85__) // ATtiny45 / ATtiny85:\r
0f700c8e	155	\r
	156	#if F_CPU >= 16000000L\r
	157	OCR1C = (F_CPU / F_INTERRUPTS / 8) - 1; // compare value: 1/15000 of CPU frequency, presc = 8\r
	158	TCCR1 = (1 << CTC1) \| (1 << CS12); // switch CTC Mode on, set prescaler to 8\r
	159	#else\r
764bd2bc	160	OCR1C = (F_CPU / F_INTERRUPTS / 4) - 1; // compare value: 1/15000 of CPU frequency, presc = 4\r
7644ac04	161	TCCR1 = (1 << CTC1) \| (1 << CS11) \| (1 << CS10); // switch CTC Mode on, set prescaler to 4\r
0f700c8e	162	#endif\r
0f700c8e	163	\r
7644ac04	164	#else // ATmegaXX:\r
	165	OCR1A = (F_CPU / F_INTERRUPTS) - 1; // compare value: 1/15000 of CPU frequency\r
	166	TCCR1B = (1 << WGM12) \| (1 << CS10); // switch CTC Mode on, set prescaler to 1\r
1f54e86c	167	#endif\r
4225a882	168	\r
775fabfa	169	#ifdef TIMSK1\r
7644ac04	170	TIMSK1 = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
775fabfa	171	#else\r
7644ac04	172	TIMSK = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
1f54e86c	173	#endif\r
4225a882	174	}\r
4225a882	175	\r
7644ac04	176	#ifdef TIM1_COMPA_vect // ATtiny84\r
775fabfa	177	#define COMPA_VECT TIM1_COMPA_vect\r
7644ac04	178	#else\r
775fabfa	179	#define COMPA_VECT TIMER1_COMPA_vect // ATmega\r
7644ac04	180	#endif\r
775fabfa	181	\r
775fabfa	182	ISR(COMPA_VECT) // Timer1 output compare A interrupt service routine, called every 1/15000 sec\r
7644ac04	183	{\r
	184	(void) irmp_ISR(); // call irmp ISR\r
	185	// call other timer interrupt routines...\r
	186	}\r
	187	\r
775fabfa	188	int\r
	189	main (void)\r
	190	{\r
622f5f59	191	IRMP_DATA irmp_data;\r
622f5f59	192	char buf[3];\r
775fabfa	193	\r
	194	irmp_init(); // initialize irmp\r
	195	timer1_init(); // initialize timer1\r
622f5f59	196	uart_init(); // initialize uart\r
622f5f59	197	\r
775fabfa	198	sei (); // enable interrupts\r
	199	\r
	200	for (;;)\r
	201	{\r
	202	if (irmp_get_data (&irmp_data))\r
	203	{\r
622f5f59	204	uart_puts_P (PSTR("protocol: 0x"));\r
	205	itoxx (buf, irmp_data.protocol);\r
	206	uart_puts (buf);\r
	207	\r
	208	#if IRMP_PROTOCOL_NAMES == 1\r
	209	uart_puts_P (PSTR(" "));\r
	210	uart_puts_P (irmp_protocol_names[irmp_data.protocol]);\r
	211	#endif\r
	212	\r
	213	uart_puts_P (PSTR(" address: 0x"));\r
	214	itoxx (buf, irmp_data.address >> 8);\r
	215	uart_puts (buf);\r
	216	itoxx (buf, irmp_data.address & 0xFF);\r
	217	uart_puts (buf);\r
	218	\r
	219	uart_puts_P (PSTR(" command: 0x"));\r
	220	itoxx (buf, irmp_data.command >> 8);\r
	221	uart_puts (buf);\r
	222	itoxx (buf, irmp_data.command & 0xFF);\r
	223	uart_puts (buf);\r
	224	\r
	225	uart_puts_P (PSTR(" flags: 0x"));\r
	226	itoxx (buf, irmp_data.flags);\r
	227	uart_puts (buf);\r
	228	\r
	229	uart_puts_P (PSTR("\r\n"));\r
775fabfa	230	}\r
	231	}\r
	232	}\r
	233	\r
	234	/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	235	* LM4F120 Launchpad (ARM Cortex M4):\r
	236	*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	237	*/\r
	238	#elif defined(STELLARIS_ARM_CORTEX_M4)\r
	239	\r
	240	void\r
	241	timer1_init (void)\r
	242	{\r
	243	SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);\r
	244	TimerConfigure(TIMER1_BASE, TIMER_CFG_32_BIT_PER);\r
	245	\r
	246	TimerLoadSet(TIMER1_BASE, TIMER_A, (F_CPU / F_INTERRUPTS) -1);\r
	247	IntEnable(INT_TIMER1A);\r
	248	TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);\r
	249	TimerEnable(TIMER1_BASE, TIMER_A);\r
	250	// Important: Timer1IntHandler has to be configured in startup_ccs.c !\r
	251	}\r
	252	\r
	253	void\r
	254	Timer1IntHandler(void) // Timer1 Interrupt Handler\r
	255	{\r
	256	(void) irmp_ISR(); // call irmp ISR\r
	257	// call other timer interrupt routines...\r
	258	}\r
7644ac04	259	\r
4225a882	260	int\r
	261	main (void)\r
	262	{\r
1f54e86c	263	IRMP_DATA irmp_data;\r
4225a882	264	\r
afd1e690	265	ROM_FPUEnable();\r
	266	ROM_FPUStackingEnable();\r
	267	ROM_SysCtlClockSet(SYSCTL_SYSDIV_5\|SYSCTL_USE_PLL\|SYSCTL_XTAL_16MHZ\|SYSCTL_OSC_MAIN);\r
afd1e690	268	\r
1f54e86c	269	irmp_init(); // initialize irmp\r
775fabfa	270	timer1_init(); // initialize timer1\r
1f54e86c	271	sei (); // enable interrupts\r
4225a882	272	\r
1f54e86c	273	for (;;)\r
4225a882	274	{\r
1f54e86c	275	if (irmp_get_data (&irmp_data))\r
	276	{\r
	277	// ir signal decoded, do something here...\r
	278	// irmp_data.protocol is the protocol, see irmp.h\r
	279	// irmp_data.address is the address/manufacturer code of ir sender\r
	280	// irmp_data.command is the command code\r
	281	// irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
	282	}\r
4225a882	283	}\r
4225a882	284	}\r
775fabfa	285	\r
4a7dc859	286	/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	287	* PIC18F4520 with XC8 compiler:\r
	288	*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	289	*/\r
	290	#elif defined (__XC8)\r
	291	\r
	292	#define _XTAL_FREQ 32000000UL // 32MHz clock\r
	293	#define FOSC _XTAL_FREQ\r
	294	#define FCY FOSC / 4UL // --> 8MHz\r
	295	\r
	296	#define BAUDRATE 19200UL\r
	297	#define BRG (( FCY 16 BAUDRATE ) -1UL)\r
	298	\r
	299	#include <stdio.h>\r
	300	#include <stdlib.h>\r
	301	\r
	302	int\r
	303	main (void)\r
	304	{\r
	305	IRMP_DATA irmp_data;\r
	306	\r
	307	irmp_init(); // initialize irmp\r
	308	\r
	309	// infinite loop, interrupts will blink PORTD pins and handle UART communications.\r
	310	while (1)\r
	311	{\r
	312	LATBbits.LATB0 = ~LATBbits.LATB0;\r
	313	\r
	314	if (irmp_get_data (&irmp_data))\r
	315	{\r
	316	// ir signal decoded, do something here...\r
	317	// irmp_data.protocol is the protocol, see irmp.h\r
	318	// irmp_data.address is the address/manufacturer code of ir sender\r
	319	// irmp_data.command is the command code\r
	320	// irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
	321	printf("proto %d addr %d cmd %d\n", irmp_data.protocol, irmp_data.address, irmp_data.command );\r
	322	}\r
	323	}\r
	324	}\r
	325	\r
	326	void interrupt high_priority high_isr(void)\r
	327	{\r
	328	if (TMR2IF)\r
	329	{\r
	330	TMR2IF = 0; // clear Timer 0 interrupt flag\r
	331	irmp_ISR();\r
	332	}\r
	333	}\r
	334	\r
622f5f59	335	/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	336	* STM32:\r
	337	*---------------------------------------------------------------------------------------------------------------------------------------------------\r
	338	*/\r
	339	#elif defined(ARM_STM32)\r
	340	\r
	341	uint32_t\r
	342	SysCtlClockGet(void)\r
	343	{\r
	344	RCC_ClocksTypeDef RCC_ClocksStatus;\r
	345	RCC_GetClocksFreq(&RCC_ClocksStatus);\r
	346	return RCC_ClocksStatus.SYSCLK_Frequency;\r
	347	}\r
	348	\r
	349	void\r
	350	timer2_init (void)\r
	351	{\r
	352	TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;\r
	353	NVIC_InitTypeDef NVIC_InitStructure;\r
	354	RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);\r
	355	\r
	356	TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;\r
	357	TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;\r
	358	TIM_TimeBaseStructure.TIM_Period = 7;\r
	359	TIM_TimeBaseStructure.TIM_Prescaler = ((F_CPU / F_INTERRUPTS)/8) - 1;\r
	360	TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);\r
	361	\r
	362	TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);\r
	363	\r
	364	NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;\r
	365	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
	366	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;\r
	367	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;\r
	368	NVIC_Init(&NVIC_InitStructure);\r
	369	\r
	370	TIM_Cmd(TIM2, ENABLE);\r
	371	}\r
	372	\r
	373	void\r
	374	TIM2_IRQHandler(void) // Timer2 Interrupt Handler\r
	375	{\r
	376	TIM_ClearITPendingBit(TIM2, TIM_IT_Update);\r
	377	(void) irmp_ISR(); // call irmp ISR\r
	378	// call other timer interrupt routines...\r
	379	}\r
	380	\r
	381	int\r
	382	main (void)\r
	383	{\r
	384	IRMP_DATA irmp_data;\r
	385	\r
	386	irmp_init(); // initialize irmp\r
	387	timer2_init(); // initialize timer2\r
	388	\r
	389	for (;;)\r
	390	{\r
	391	if (irmp_get_data (&irmp_data))\r
	392	{\r
	393	// ir signal decoded, do something here...\r
	394	// irmp_data.protocol is the protocol, see irmp.h\r
	395	// irmp_data.address is the address/manufacturer code of ir sender\r
	396	// irmp_data.command is the command code\r
	397	// irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
	398	}\r
399	}\r
400	}\r
775fabfa	401	#endif\r