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4225a882 1/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
2 * main.c - demo main module to test irmp decoder\r
3 *\r
2ac088b2 4 * Copyright (c) 2009-2013 Frank Meyer - frank(at)fli4l.de\r
4225a882 5 *\r
2ac088b2 6 * $Id: main.c,v 1.17 2013/01/17 07:33:14 fm Exp $\r
cb8474cc 7 *\r
775fabfa 8 * This demo module is runnable on AVRs and LM4F120 Launchpad (ARM Cortex M4)\r
4225a882 9 *\r
775fabfa 10 * ATMEGA88 @ 8 MHz internal RC Osc with BODLEVEL 4.3V: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9\r
11 * ATMEGA88 @ 8 MHz external Crystal Osc with BODLEVEL 4.3V: lfuse: 0xFF hfuse: 0xDC efuse: 0xF9\r
4225a882 12 *\r
13 * This program is free software; you can redistribute it and/or modify\r
14 * it under the terms of the GNU General Public License as published by\r
15 * the Free Software Foundation; either version 2 of the License, or\r
16 * (at your option) any later version.\r
17 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
18 */\r
19\r
1f54e86c 20#include "irmp.h"\r
4225a882 21\r
22#ifndef F_CPU\r
23#error F_CPU unkown\r
24#endif\r
25\r
775fabfa 26/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
27 * ATMEL AVR part:\r
28 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
29 */\r
30#if defined (ATMEL_AVR)\r
31\r
4225a882 32void\r
1f54e86c 33timer1_init (void)\r
4225a882 34{\r
476267f4 35#if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45 / ATtiny85:\r
0f700c8e 36\r
37#if F_CPU >= 16000000L\r
38 OCR1C = (F_CPU / F_INTERRUPTS / 8) - 1; // compare value: 1/15000 of CPU frequency, presc = 8\r
39 TCCR1 = (1 << CTC1) | (1 << CS12); // switch CTC Mode on, set prescaler to 8\r
40#else\r
764bd2bc 41 OCR1C = (F_CPU / F_INTERRUPTS / 4) - 1; // compare value: 1/15000 of CPU frequency, presc = 4\r
7644ac04 42 TCCR1 = (1 << CTC1) | (1 << CS11) | (1 << CS10); // switch CTC Mode on, set prescaler to 4\r
0f700c8e 43#endif\r
44\r
7644ac04 45#else // ATmegaXX:\r
46 OCR1A = (F_CPU / F_INTERRUPTS) - 1; // compare value: 1/15000 of CPU frequency\r
47 TCCR1B = (1 << WGM12) | (1 << CS10); // switch CTC Mode on, set prescaler to 1\r
1f54e86c 48#endif\r
4225a882 49\r
775fabfa 50#ifdef TIMSK1\r
7644ac04 51 TIMSK1 = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
775fabfa 52#else\r
7644ac04 53 TIMSK = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
1f54e86c 54#endif\r
4225a882 55}\r
56\r
7644ac04 57#ifdef TIM1_COMPA_vect // ATtiny84\r
775fabfa 58#define COMPA_VECT TIM1_COMPA_vect\r
7644ac04 59#else\r
775fabfa 60#define COMPA_VECT TIMER1_COMPA_vect // ATmega\r
7644ac04 61#endif\r
775fabfa 62\r
63ISR(COMPA_VECT) // Timer1 output compare A interrupt service routine, called every 1/15000 sec\r
7644ac04 64{\r
65 (void) irmp_ISR(); // call irmp ISR\r
66 // call other timer interrupt routines...\r
67}\r
68\r
775fabfa 69int\r
70main (void)\r
71{\r
72 IRMP_DATA irmp_data;\r
73\r
74 irmp_init(); // initialize irmp\r
75 timer1_init(); // initialize timer1\r
76 sei (); // enable interrupts\r
77\r
78 for (;;)\r
79 {\r
80 if (irmp_get_data (&irmp_data))\r
81 {\r
82 // ir signal decoded, do something here...\r
83 // irmp_data.protocol is the protocol, see irmp.h\r
84 // irmp_data.address is the address/manufacturer code of ir sender\r
85 // irmp_data.command is the command code\r
86 // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
87 }\r
88 }\r
89}\r
90\r
91/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
92 * LM4F120 Launchpad (ARM Cortex M4):\r
93 *---------------------------------------------------------------------------------------------------------------------------------------------------\r
94 */\r
95#elif defined(STELLARIS_ARM_CORTEX_M4)\r
96\r
97void\r
98timer1_init (void)\r
99{\r
100 SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);\r
101 TimerConfigure(TIMER1_BASE, TIMER_CFG_32_BIT_PER);\r
102\r
103 TimerLoadSet(TIMER1_BASE, TIMER_A, (F_CPU / F_INTERRUPTS) -1);\r
104 IntEnable(INT_TIMER1A);\r
105 TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);\r
106 TimerEnable(TIMER1_BASE, TIMER_A);\r
107 // Important: Timer1IntHandler has to be configured in startup_ccs.c !\r
108}\r
109\r
110void\r
111Timer1IntHandler(void) // Timer1 Interrupt Handler\r
112{\r
113 (void) irmp_ISR(); // call irmp ISR\r
114 // call other timer interrupt routines...\r
115}\r
7644ac04 116\r
4225a882 117int\r
118main (void)\r
119{\r
1f54e86c 120 IRMP_DATA irmp_data;\r
4225a882 121\r
afd1e690 122 ROM_FPUEnable();\r
123 ROM_FPUStackingEnable();\r
124 ROM_SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);\r
afd1e690 125\r
1f54e86c 126 irmp_init(); // initialize irmp\r
775fabfa 127 timer1_init(); // initialize timer1\r
1f54e86c 128 sei (); // enable interrupts\r
4225a882 129\r
1f54e86c 130 for (;;)\r
4225a882 131 {\r
1f54e86c 132 if (irmp_get_data (&irmp_data))\r
133 {\r
134 // ir signal decoded, do something here...\r
135 // irmp_data.protocol is the protocol, see irmp.h\r
136 // irmp_data.address is the address/manufacturer code of ir sender\r
137 // irmp_data.command is the command code\r
138 // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)\r
139 }\r
4225a882 140 }\r
4225a882 141}\r
775fabfa 142\r
143#endif\r