1 /*---------------------------------------------------------------------------------------------------------------------------------------------------
2 * main.c - demo main module to test irmp decoder
4 * Copyright (c) 2009-2014 Frank Meyer - frank(at)fli4l.de
6 * $Id: main.c,v 1.21 2014/09/17 09:44:47 fm Exp $
8 * This demo module is runnable on AVRs and LM4F120 Launchpad (ARM Cortex M4)
10 * ATMEGA88 @ 8 MHz internal RC Osc with BODLEVEL 4.3V: lfuse: 0xE2 hfuse: 0xDC efuse: 0xF9
11 * ATMEGA88 @ 8 MHz external Crystal Osc with BODLEVEL 4.3V: lfuse: 0xFF hfuse: 0xDC efuse: 0xF9
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *---------------------------------------------------------------------------------------------------------------------------------------------------
26 /*---------------------------------------------------------------------------------------------------------------------------------------------------
28 *---------------------------------------------------------------------------------------------------------------------------------------------------
30 #if defined (ATMEL_AVR)
34 #include <util/setbaud.h>
38 #define UART0_UBRRH UBRR0H
39 #define UART0_UBRRL UBRR0L
40 #define UART0_UCSRA UCSR0A
41 #define UART0_UCSRB UCSR0B
42 #define UART0_UCSRC UCSR0C
43 #define UART0_UDRE_BIT_VALUE (1<<UDRE0)
44 #define UART0_UCSZ1_BIT_VALUE (1<<UCSZ01)
45 #define UART0_UCSZ0_BIT_VALUE (1<<UCSZ00)
47 #define UART0_URSEL_BIT_VALUE (1<<URSEL0)
49 #define UART0_URSEL_BIT_VALUE (0)
51 #define UART0_TXEN_BIT_VALUE (1<<TXEN0)
52 #define UART0_UDR UDR0
53 #define UART0_U2X U2X0
57 #define UART0_UBRRH UBRRH
58 #define UART0_UBRRL UBRRL
59 #define UART0_UCSRA UCSRA
60 #define UART0_UCSRB UCSRB
61 #define UART0_UCSRC UCSRC
62 #define UART0_UDRE_BIT_VALUE (1<<UDRE)
63 #define UART0_UCSZ1_BIT_VALUE (1<<UCSZ1)
64 #define UART0_UCSZ0_BIT_VALUE (1<<UCSZ0)
66 #define UART0_URSEL_BIT_VALUE (1<<URSEL)
68 #define UART0_URSEL_BIT_VALUE (0)
70 #define UART0_TXEN_BIT_VALUE (1<<TXEN)
79 UART0_UBRRH
= UBRRH_VALUE
; // set baud rate
80 UART0_UBRRL
= UBRRL_VALUE
;
83 UART0_UCSRA
|= (1<<UART0_U2X
);
85 UART0_UCSRA
&= ~(1<<UART0_U2X
);
88 UART0_UCSRC
= UART0_UCSZ1_BIT_VALUE
| UART0_UCSZ0_BIT_VALUE
| UART0_URSEL_BIT_VALUE
;
89 UART0_UCSRB
|= UART0_TXEN_BIT_VALUE
; // enable UART TX
93 uart_putc (unsigned char ch
)
95 while (!(UART0_UCSRA
& UART0_UDRE_BIT_VALUE
))
114 uart_puts_P (PGM_P s
)
118 while ((ch
= pgm_read_byte(s
)) != '\0')
138 rtc
= val
- 10 + 'A';
144 itoxx (char * xx
, unsigned char i
)
146 *xx
++ = itox (i
>> 4);
147 *xx
++ = itox (i
& 0x0F);
154 #if defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45 / ATtiny85:
156 #if F_CPU >= 16000000L
157 OCR1C
= (F_CPU
/ F_INTERRUPTS
/ 8) - 1; // compare value: 1/15000 of CPU frequency, presc = 8
158 TCCR1
= (1 << CTC1
) | (1 << CS12
); // switch CTC Mode on, set prescaler to 8
160 OCR1C
= (F_CPU
/ F_INTERRUPTS
/ 4) - 1; // compare value: 1/15000 of CPU frequency, presc = 4
161 TCCR1
= (1 << CTC1
) | (1 << CS11
) | (1 << CS10
); // switch CTC Mode on, set prescaler to 4
165 OCR1A
= (F_CPU
/ F_INTERRUPTS
) - 1; // compare value: 1/15000 of CPU frequency
166 TCCR1B
= (1 << WGM12
) | (1 << CS10
); // switch CTC Mode on, set prescaler to 1
170 TIMSK1
= 1 << OCIE1A
; // OCIE1A: Interrupt by timer compare
172 TIMSK
= 1 << OCIE1A
; // OCIE1A: Interrupt by timer compare
176 #ifdef TIM1_COMPA_vect // ATtiny84
177 #define COMPA_VECT TIM1_COMPA_vect
179 #define COMPA_VECT TIMER1_COMPA_vect // ATmega
182 ISR(COMPA_VECT
) // Timer1 output compare A interrupt service routine, called every 1/15000 sec
184 (void) irmp_ISR(); // call irmp ISR
185 // call other timer interrupt routines...
194 irmp_init(); // initialize irmp
195 timer1_init(); // initialize timer1
196 uart_init(); // initialize uart
198 sei (); // enable interrupts
202 if (irmp_get_data (&irmp_data
))
204 uart_puts_P (PSTR("protocol: 0x"));
205 itoxx (buf
, irmp_data
.protocol
);
208 #if IRMP_PROTOCOL_NAMES == 1
209 uart_puts_P (PSTR(" "));
210 uart_puts_P (pgm_read_word (&(irmp_protocol_names
[irmp_data
.protocol
])));
213 uart_puts_P (PSTR(" address: 0x"));
214 itoxx (buf
, irmp_data
.address
>> 8);
216 itoxx (buf
, irmp_data
.address
& 0xFF);
219 uart_puts_P (PSTR(" command: 0x"));
220 itoxx (buf
, irmp_data
.command
>> 8);
222 itoxx (buf
, irmp_data
.command
& 0xFF);
225 uart_puts_P (PSTR(" flags: 0x"));
226 itoxx (buf
, irmp_data
.flags
);
229 uart_puts_P (PSTR("\r\n"));
234 /*---------------------------------------------------------------------------------------------------------------------------------------------------
235 * LM4F120 Launchpad (ARM Cortex M4):
236 *---------------------------------------------------------------------------------------------------------------------------------------------------
238 #elif defined(STELLARIS_ARM_CORTEX_M4)
243 SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1
);
244 TimerConfigure(TIMER1_BASE
, TIMER_CFG_32_BIT_PER
);
246 TimerLoadSet(TIMER1_BASE
, TIMER_A
, (F_CPU
/ F_INTERRUPTS
) -1);
247 IntEnable(INT_TIMER1A
);
248 TimerIntEnable(TIMER1_BASE
, TIMER_TIMA_TIMEOUT
);
249 TimerEnable(TIMER1_BASE
, TIMER_A
);
250 // Important: Timer1IntHandler has to be configured in startup_ccs.c !
254 Timer1IntHandler(void) // Timer1 Interrupt Handler
256 (void) irmp_ISR(); // call irmp ISR
257 // call other timer interrupt routines...
266 ROM_FPUStackingEnable();
267 ROM_SysCtlClockSet(SYSCTL_SYSDIV_5
|SYSCTL_USE_PLL
|SYSCTL_XTAL_16MHZ
|SYSCTL_OSC_MAIN
);
269 irmp_init(); // initialize irmp
270 timer1_init(); // initialize timer1
271 sei (); // enable interrupts
275 if (irmp_get_data (&irmp_data
))
277 // ir signal decoded, do something here...
278 // irmp_data.protocol is the protocol, see irmp.h
279 // irmp_data.address is the address/manufacturer code of ir sender
280 // irmp_data.command is the command code
281 // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)
286 /*---------------------------------------------------------------------------------------------------------------------------------------------------
287 * PIC18F4520 with XC8 compiler:
288 *---------------------------------------------------------------------------------------------------------------------------------------------------
290 #elif defined (__XC8)
292 #define _XTAL_FREQ 32000000UL // 32MHz clock
293 #define FOSC _XTAL_FREQ
294 #define FCY FOSC / 4UL // --> 8MHz
296 #define BAUDRATE 19200UL
297 #define BRG (( FCY 16 BAUDRATE ) -1UL)
307 irmp_init(); // initialize irmp
309 // infinite loop, interrupts will blink PORTD pins and handle UART communications.
312 LATBbits
.LATB0
= ~LATBbits
.LATB0
;
314 if (irmp_get_data (&irmp_data
))
316 // ir signal decoded, do something here...
317 // irmp_data.protocol is the protocol, see irmp.h
318 // irmp_data.address is the address/manufacturer code of ir sender
319 // irmp_data.command is the command code
320 // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)
321 printf("proto %d addr %d cmd %d\n", irmp_data
.protocol
, irmp_data
.address
, irmp_data
.command
);
326 void interrupt high_priority
high_isr(void)
330 TMR2IF
= 0; // clear Timer 0 interrupt flag
335 /*---------------------------------------------------------------------------------------------------------------------------------------------------
337 *---------------------------------------------------------------------------------------------------------------------------------------------------
339 #elif defined(ARM_STM32)
344 RCC_ClocksTypeDef RCC_ClocksStatus
;
345 RCC_GetClocksFreq(&RCC_ClocksStatus
);
346 return RCC_ClocksStatus
.SYSCLK_Frequency
;
352 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure
;
353 NVIC_InitTypeDef NVIC_InitStructure
;
354 RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2
, ENABLE
);
356 TIM_TimeBaseStructure
.TIM_ClockDivision
= TIM_CKD_DIV1
;
357 TIM_TimeBaseStructure
.TIM_CounterMode
= TIM_CounterMode_Up
;
358 TIM_TimeBaseStructure
.TIM_Period
= 7;
359 TIM_TimeBaseStructure
.TIM_Prescaler
= ((F_CPU
/ F_INTERRUPTS
)/8) - 1;
360 TIM_TimeBaseInit(TIM2
, &TIM_TimeBaseStructure
);
362 TIM_ITConfig(TIM2
, TIM_IT_Update
, ENABLE
);
364 NVIC_InitStructure
.NVIC_IRQChannel
= TIM2_IRQn
;
365 NVIC_InitStructure
.NVIC_IRQChannelCmd
= ENABLE
;
366 NVIC_InitStructure
.NVIC_IRQChannelPreemptionPriority
= 0x0F;
367 NVIC_InitStructure
.NVIC_IRQChannelSubPriority
= 0x0F;
368 NVIC_Init(&NVIC_InitStructure
);
370 TIM_Cmd(TIM2
, ENABLE
);
374 TIM2_IRQHandler(void) // Timer2 Interrupt Handler
376 TIM_ClearITPendingBit(TIM2
, TIM_IT_Update
);
377 (void) irmp_ISR(); // call irmp ISR
378 // call other timer interrupt routines...
386 irmp_init(); // initialize irmp
387 timer2_init(); // initialize timer2
391 if (irmp_get_data (&irmp_data
))
393 // ir signal decoded, do something here...
394 // irmp_data.protocol is the protocol, see irmp.h
395 // irmp_data.address is the address/manufacturer code of ir sender
396 // irmp_data.command is the command code
397 // irmp_protocol_names[irmp_data.protocol] is the protocol name (if enabled, see irmpconfig.h)