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Version 2.9.7: added port to to ESP8266 and TEENSY, added PANASONIC protocol, added...
[irmp.git] / irsnd.c
1 /*---------------------------------------------------------------------------------------------------------------------------------------------------
2 * @file irsnd.c
3 *
4 * Copyright (c) 2010-2015 Frank Meyer - frank(at)fli4l.de
5 *
6 * Supported AVR mikrocontrollers:
7 *
8 * ATtiny87, ATtiny167
9 * ATtiny45, ATtiny85
10 * ATtiny44 ATtiny84
11 * ATmega8, ATmega16, ATmega32
12 * ATmega162
13 * ATmega164, ATmega324, ATmega644, ATmega644P, ATmega1284, ATmega1284P
14 * ATmega88, ATmega88P, ATmega168, ATmega168P, ATmega328P
15 *
16 * $Id: irsnd.c,v 1.96 2015/11/17 13:51:45 fm Exp $
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *---------------------------------------------------------------------------------------------------------------------------------------------------
23 */
24
25 #include "irsnd.h"
26
27 #ifndef F_CPU
28 # error F_CPU unkown
29 #endif
30
31 /*---------------------------------------------------------------------------------------------------------------------------------------------------
32 * ATtiny pin definition of OC0A / OC0B
33 * ATmega pin definition of OC2 / OC2A / OC2B / OC0 / OC0A / OC0B
34 *---------------------------------------------------------------------------------------------------------------------------------------------------
35 */
36 #if defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) // ATtiny44/84 uses OC0A = PB2 or OC0B = PA7
37 # if IRSND_OCx == IRSND_OC0A // OC0A
38 # define IRSND_PORT_LETTER B
39 # define IRSND_BIT_NUMBER 2
40 # elif IRSND_OCx == IRSND_OC0B // OC0B
41 # define IRSND_PORT_LETTER A
42 # define IRSND_BIT_NUMBER 7
43 # else
44 # error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h
45 # endif // IRSND_OCx
46
47 #elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45/85 uses OC0A = PB0 or OC0B = PB1
48 # if IRSND_OCx == IRSND_OC0A // OC0A
49 # define IRSND_PORT_LETTER B
50 # define IRSND_BIT_NUMBER 0
51 # elif IRSND_OCx == IRSND_OC0B // OC0B
52 # define IRSND_PORT_LETTER B
53 # define IRSND_BIT_NUMBER 1
54 # else
55 # error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h
56 # endif // IRSND_OCx
57
58 #elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) // ATtiny87/167 uses OC0A = PA2
59 # if IRSND_OCx == IRSND_OC0A // OC0A
60 # define IRSND_PORT_LETTER A
61 # define IRSND_BIT_NUMBER 2
62 # else
63 # error Wrong value for IRSND_OCx, choose IRSND_OC0A in irsndconfig.h
64 # endif // IRSND_OCx
65
66 #elif defined (__AVR_ATmega8__) // ATmega8 uses only OC2 = PB3
67 # if IRSND_OCx == IRSND_OC2 // OC0A
68 # define IRSND_PORT_LETTER B
69 # define IRSND_BIT_NUMBER 3
70 # else
71 # error Wrong value for IRSND_OCx, choose IRSND_OC2 in irsndconfig.h
72 # endif // IRSND_OCx
73 #elif defined (__AVR_ATmega16__) || defined (__AVR_ATmega32__) // ATmega16|32 uses OC2 = PD7
74 # if IRSND_OCx == IRSND_OC2 // OC2
75 # define IRSND_PORT_LETTER D
76 # define IRSND_BIT_NUMBER 7
77 # else
78 # error Wrong value for IRSND_OCx, choose IRSND_OC2 in irsndconfig.h
79 # endif // IRSND_OCx
80
81 #elif defined (__AVR_ATmega162__) // ATmega162 uses OC2 = PB1 or OC0 = PB0
82 # if IRSND_OCx == IRSND_OC2 // OC2
83 # define IRSND_PORT_LETTER B
84 # define IRSND_BIT_NUMBER 1
85 # elif IRSND_OCx == IRSND_OC0 // OC0
86 # define IRSND_PORT_LETTER B
87 # define IRSND_BIT_NUMBER 0
88 # else
89 # error Wrong value for IRSND_OCx, choose IRSND_OC2 or IRSND_OC0 in irsndconfig.h
90 # endif // IRSND_OCx
91
92 #elif defined (__AVR_ATmega164__) \
93 || defined (__AVR_ATmega324__) \
94 || defined (__AVR_ATmega644__) \
95 || defined (__AVR_ATmega644P__) \
96 || defined (__AVR_ATmega1284__) \
97 || defined (__AVR_ATmega1284P__) // ATmega164|324|644|644P|1284 uses OC2A = PD7 or OC2B = PD6 or OC0A = PB3 or OC0B = PB4
98 # if IRSND_OCx == IRSND_OC2A // OC2A
99 # define IRSND_PORT_LETTER D
100 # define IRSND_BIT_NUMBER 7
101 # elif IRSND_OCx == IRSND_OC2B // OC2B
102 # define IRSND_PORT_LETTER D
103 # define IRSND_BIT_NUMBER 6
104 # elif IRSND_OCx == IRSND_OC0A // OC0A
105 # define IRSND_PORT_LETTER B
106 # define IRSND_BIT_NUMBER 3
107 # elif IRSND_OCx == IRSND_OC0B // OC0B
108 # define IRSND_PORT_LETTER B
109 # define IRSND_BIT_NUMBER 4
110 # else
111 # error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h
112 # endif // IRSND_OCx
113
114 #elif defined (__AVR_ATmega48__) \
115 || defined (__AVR_ATmega88__) \
116 || defined (__AVR_ATmega88P__) \
117 || defined (__AVR_ATmega168__) \
118 || defined (__AVR_ATmega168P__) \
119 || defined (__AVR_ATmega328P__) // ATmega48|88|168|168|328 uses OC2A = PB3 or OC2B = PD3 or OC0A = PD6 or OC0B = PD5
120 # if IRSND_OCx == IRSND_OC2A // OC2A
121 # define IRSND_PORT_LETTER B
122 # define IRSND_BIT_NUMBER 3
123 # elif IRSND_OCx == IRSND_OC2B // OC2B
124 # define IRSND_PORT_LETTER D
125 # define IRSND_BIT_NUMBER 3
126 # elif IRSND_OCx == IRSND_OC0A // OC0A
127 # define IRSND_PORT_LETTER D
128 # define IRSND_BIT_NUMBER 6
129 # elif IRSND_OCx == IRSND_OC0B // OC0B
130 # define IRSND_PORT_LETTER D
131 # define IRSND_BIT_NUMBER 5
132 # else
133 # error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h
134 # endif // IRSND_OCx
135
136 #elif defined (__AVR_ATmega8515__) // ATmega8515 uses OC0 = PB0 or OC1A = PD5 or OC1B = PE2
137 # if IRSND_OCx == IRSND_OC0
138 # define IRSND_PORT_LETTER B
139 # define IRSND_BIT_NUMBER 0
140 # elif IRSND_OCx == IRSND_OC1A
141 # define IRSND_PORT_LETTER D
142 # define IRSND_BIT_NUMBER 5
143 # elif IRSND_OCx == IRSND_OC1B
144 # define IRSND_PORT_LETTER E
145 # define IRSND_BIT_NUMBER 2
146 # endif // IRSND_OCx
147
148 #elif defined (__AVR_XMEGA__) // ATxmega
149 # if IRSND_OCx == IRSND_XMEGA_OC0A
150 # define IRSND_BIT_NUMBER 0
151 # elif IRSND_OCx == IRSND_XMEGA_OC0B
152 # define IRSND_BIT_NUMBER 1
153 # elif IRSND_OCx == IRSND_XMEGA_OC0C
154 # define IRSND_BIT_NUMBER 2
155 # elif IRSND_OCx == IRSND_XMEGA_OC0D
156 # define IRSND_BIT_NUMBER 3
157 # elif IRSND_OCx == IRSND_XMEGA_OC1A
158 # define IRSND_BIT_NUMBER 4
159 # elif IRSND_OCx == IRSND_XMEGA_OC1B
160 # define IRSND_BIT_NUMBER 5
161 # else
162 # error Wrong value for IRSND_OCx, choose IRSND_XMEGA_OC0A, IRSND_XMEGA_OC0B, IRSND_XMEGA_OC0C, IRSND_XMEGA_OC0D, IRSND_XMEGA_OC1A, or IRSND_XMEGA_OC1B in irsndconfig.h
163 # endif // IRSND_OCx
164
165 #elif defined (PIC_C18) //Microchip C18 compiler
166 //Nothing here to do here -> See irsndconfig.h
167 #elif defined (ARM_STM32) //STM32
168 //Nothing here to do here -> See irsndconfig.h
169 #elif defined (TEENSY_ARM_CORTEX_M4) // Teensy3
170 # if !digitalPinHasPWM(IRSND_PIN)
171 # error need pin with PWM output.
172 # endif
173 #else
174 # if !defined (unix) && !defined (WIN32)
175 # error mikrocontroller not defined, please fill in definitions here.
176 # endif // unix, WIN32
177 #endif // __AVR...
178
179 #if defined(__AVR_XMEGA__)
180 # define _CONCAT(a,b) a##b
181 # define CONCAT(a,b) _CONCAT(a,b)
182 # define IRSND_PORT IRSND_PORT_PRE.OUT
183 # define IRSND_DDR IRSND_PORT_PRE.DIR
184 # define IRSND_PIN IRSND_PORT_PRE.IN
185 # define IRSND_BIT IRSND_BIT_NUMBER
186 #elif defined(ATMEL_AVR)
187 # define _CONCAT(a,b) a##b
188 # define CONCAT(a,b) _CONCAT(a,b)
189 # define IRSND_PORT CONCAT(PORT, IRSND_PORT_LETTER)
190 # define IRSND_DDR CONCAT(DDR, IRSND_PORT_LETTER)
191 # define IRSND_BIT IRSND_BIT_NUMBER
192 #endif
193
194 #if IRSND_SUPPORT_NIKON_PROTOCOL == 1
195 typedef uint16_t IRSND_PAUSE_LEN;
196 #else
197 typedef uint8_t IRSND_PAUSE_LEN;
198 #endif
199
200 /*---------------------------------------------------------------------------------------------------------------------------------------------------
201 * IR timings
202 *---------------------------------------------------------------------------------------------------------------------------------------------------
203 */
204 #define SIRCS_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PULSE_TIME + 0.5)
205 #define SIRCS_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PAUSE_TIME + 0.5)
206 #define SIRCS_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_1_PULSE_TIME + 0.5)
207 #define SIRCS_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_0_PULSE_TIME + 0.5)
208 #define SIRCS_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_PAUSE_TIME + 0.5)
209 #define SIRCS_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
210 #define SIRCS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
211
212 #define NEC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PULSE_TIME + 0.5)
213 #define NEC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PAUSE_TIME + 0.5)
214 #define NEC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_REPEAT_START_BIT_PAUSE_TIME + 0.5)
215 #define NEC_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_PULSE_TIME + 0.5)
216 #define NEC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_1_PAUSE_TIME + 0.5)
217 #define NEC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_0_PAUSE_TIME + 0.5)
218 #define NEC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NEC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
219
220 #define SAMSUNG_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PULSE_TIME + 0.5)
221 #define SAMSUNG_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PAUSE_TIME + 0.5)
222 #define SAMSUNG_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_PULSE_TIME + 0.5)
223 #define SAMSUNG_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_1_PAUSE_TIME + 0.5)
224 #define SAMSUNG_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_0_PAUSE_TIME + 0.5)
225 #define SAMSUNG_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
226
227 #define SAMSUNG32_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
228 #define SAMSUNG32_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
229
230 #define SAMSUNG48_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG48_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
231 #define SAMSUNG48_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG48_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
232
233 #define MATSUSHITA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PULSE_TIME + 0.5)
234 #define MATSUSHITA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PAUSE_TIME + 0.5)
235 #define MATSUSHITA_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_PULSE_TIME + 0.5)
236 #define MATSUSHITA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_1_PAUSE_TIME + 0.5)
237 #define MATSUSHITA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_0_PAUSE_TIME + 0.5)
238 #define MATSUSHITA_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * MATSUSHITA_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
239
240 #define KASEIKYO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PULSE_TIME + 0.5)
241 #define KASEIKYO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PAUSE_TIME + 0.5)
242 #define KASEIKYO_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_PULSE_TIME + 0.5)
243 #define KASEIKYO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_1_PAUSE_TIME + 0.5)
244 #define KASEIKYO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_0_PAUSE_TIME + 0.5)
245 #define KASEIKYO_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
246 #define KASEIKYO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
247
248 #define PANASONIC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_START_BIT_PULSE_TIME + 0.5)
249 #define PANASONIC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_START_BIT_PAUSE_TIME + 0.5)
250 #define PANASONIC_PULSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_PULSE_TIME + 0.5)
251 #define PANASONIC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_1_PAUSE_TIME + 0.5)
252 #define PANASONIC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_0_PAUSE_TIME + 0.5)
253 #define PANASONIC_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PANASONIC_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
254 #define PANASONIC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PANASONIC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
255
256 #define RECS80_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PULSE_TIME + 0.5)
257 #define RECS80_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PAUSE_TIME + 0.5)
258 #define RECS80_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_PULSE_TIME + 0.5)
259 #define RECS80_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_1_PAUSE_TIME + 0.5)
260 #define RECS80_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_0_PAUSE_TIME + 0.5)
261 #define RECS80_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
262
263 #define RC5_START_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)
264 #define RC5_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)
265 #define RC5_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC5_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
266
267 #define RC6_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PULSE_TIME + 0.5)
268 #define RC6_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PAUSE_TIME + 0.5)
269 #define RC6_BIT_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_TIME + 0.5)
270 #define RC6_BIT_2_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_2_TIME + 0.5)
271 #define RC6_BIT_3_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_3_TIME + 0.5)
272 #define RC6_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC6_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
273
274 #define DENON_PULSE_LEN (uint8_t)(F_INTERRUPTS * DENON_PULSE_TIME + 0.5)
275 #define DENON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_1_PAUSE_TIME + 0.5)
276 #define DENON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_0_PAUSE_TIME + 0.5)
277 #define DENON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
278 #define DENON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
279
280 #define THOMSON_PULSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_PULSE_TIME + 0.5)
281 #define THOMSON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_1_PAUSE_TIME + 0.5)
282 #define THOMSON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_0_PAUSE_TIME + 0.5)
283 #define THOMSON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
284 #define THOMSON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
285
286 #define RECS80EXT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PULSE_TIME + 0.5)
287 #define RECS80EXT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PAUSE_TIME + 0.5)
288 #define RECS80EXT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_PULSE_TIME + 0.5)
289 #define RECS80EXT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_1_PAUSE_TIME + 0.5)
290 #define RECS80EXT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_0_PAUSE_TIME + 0.5)
291 #define RECS80EXT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80EXT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
292
293 #define TELEFUNKEN_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_START_BIT_PULSE_TIME + 0.5)
294 #define TELEFUNKEN_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_START_BIT_PAUSE_TIME + 0.5)
295 #define TELEFUNKEN_PULSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_PULSE_TIME + 0.5)
296 #define TELEFUNKEN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_1_PAUSE_TIME + 0.5)
297 #define TELEFUNKEN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_0_PAUSE_TIME + 0.5)
298 #define TELEFUNKEN_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * TELEFUNKEN_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
299 #define TELEFUNKEN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * TELEFUNKEN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
300
301 #define BOSE_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_START_BIT_PULSE_TIME + 0.5)
302 #define BOSE_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_START_BIT_PAUSE_TIME + 0.5)
303 #define BOSE_PULSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_PULSE_TIME + 0.5)
304 #define BOSE_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_1_PAUSE_TIME + 0.5)
305 #define BOSE_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_0_PAUSE_TIME + 0.5)
306 #define BOSE_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BOSE_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
307 #define BOSE_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BOSE_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
308
309 #define NUBERT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PULSE_TIME + 0.5)
310 #define NUBERT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PAUSE_TIME + 0.5)
311 #define NUBERT_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PULSE_TIME + 0.5)
312 #define NUBERT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PAUSE_TIME + 0.5)
313 #define NUBERT_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PULSE_TIME + 0.5)
314 #define NUBERT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PAUSE_TIME + 0.5)
315 #define NUBERT_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
316 #define NUBERT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
317
318 #define FAN_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_START_BIT_PULSE_TIME + 0.5)
319 #define FAN_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_START_BIT_PAUSE_TIME + 0.5)
320 #define FAN_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_1_PULSE_TIME + 0.5)
321 #define FAN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_1_PAUSE_TIME + 0.5)
322 #define FAN_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_0_PULSE_TIME + 0.5)
323 #define FAN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_0_PAUSE_TIME + 0.5)
324 #define FAN_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FAN_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
325 #define FAN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FAN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
326
327 #define SPEAKER_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_START_BIT_PULSE_TIME + 0.5)
328 #define SPEAKER_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_START_BIT_PAUSE_TIME + 0.5)
329 #define SPEAKER_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_1_PULSE_TIME + 0.5)
330 #define SPEAKER_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_1_PAUSE_TIME + 0.5)
331 #define SPEAKER_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_0_PULSE_TIME + 0.5)
332 #define SPEAKER_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_0_PAUSE_TIME + 0.5)
333 #define SPEAKER_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SPEAKER_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
334 #define SPEAKER_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SPEAKER_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
335
336 #define BANG_OLUFSEN_START_BIT1_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PULSE_TIME + 0.5)
337 #define BANG_OLUFSEN_START_BIT1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PAUSE_TIME + 0.5)
338 #define BANG_OLUFSEN_START_BIT2_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PULSE_TIME + 0.5)
339 #define BANG_OLUFSEN_START_BIT2_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PAUSE_TIME + 0.5)
340 #define BANG_OLUFSEN_START_BIT3_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PULSE_TIME + 0.5)
341 #define BANG_OLUFSEN_START_BIT3_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PAUSE_TIME + 0.5)
342 #define BANG_OLUFSEN_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_PULSE_TIME + 0.5)
343 #define BANG_OLUFSEN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_1_PAUSE_TIME + 0.5)
344 #define BANG_OLUFSEN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_0_PAUSE_TIME + 0.5)
345 #define BANG_OLUFSEN_R_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_R_PAUSE_TIME + 0.5)
346 #define BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_TRAILER_BIT_PAUSE_TIME + 0.5)
347 #define BANG_OLUFSEN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BANG_OLUFSEN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
348
349 #define GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_PRE_PAUSE_TIME + 0.5)
350 #define GRUNDIG_NOKIA_IR60_BIT_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_BIT_TIME + 0.5)
351 #define GRUNDIG_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
352 #define NOKIA_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NOKIA_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
353 #define GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
354
355 #define IR60_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * IR60_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
356
357 #define SIEMENS_START_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME + 0.5)
358 #define SIEMENS_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)
359 #define SIEMENS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
360
361 #define RUWIDO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME + 0.5)
362 #define RUWIDO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PAUSE_TIME + 0.5)
363 #define RUWIDO_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)
364 #define RUWIDO_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PAUSE_TIME + 0.5)
365 #define RUWIDO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
366
367 #ifdef PIC_C18 // PIC C18
368 # define IRSND_FREQ_TYPE uint8_t
369 # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
370 # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
371 # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
372 # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
373 # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
374 # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
375 # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
376 #elif defined (ARM_STM32) // STM32
377 # define IRSND_FREQ_TYPE uint32_t
378 # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)
379 # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)
380 # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)
381 # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)
382 # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)
383 # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)
384 # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)
385 #elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY
386 # define IRSND_FREQ_TYPE float
387 # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)
388 # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)
389 # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)
390 # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)
391 # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)
392 # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)
393 # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)
394 #else // AVR
395 # if F_CPU >= 16000000L
396 # define AVR_PRESCALER 8
397 # else
398 # define AVR_PRESCALER 1
399 # endif
400 # define IRSND_FREQ_TYPE uint8_t
401 # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / AVR_PRESCALER / 2) - 1)
402 # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / AVR_PRESCALER / 2) - 1)
403 # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / AVR_PRESCALER / 2) - 1)
404 # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / AVR_PRESCALER / 2) - 1)
405 # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / AVR_PRESCALER / 2) - 1)
406 # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / AVR_PRESCALER / 2) - 1)
407 # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / AVR_PRESCALER / 2) - 1)
408 #endif
409
410 #define FDC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PULSE_TIME + 0.5)
411 #define FDC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PAUSE_TIME + 0.5)
412 #define FDC_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_PULSE_TIME + 0.5)
413 #define FDC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_1_PAUSE_TIME + 0.5)
414 #define FDC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_0_PAUSE_TIME + 0.5)
415 #define FDC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FDC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
416
417 #define RCCAR_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PULSE_TIME + 0.5)
418 #define RCCAR_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PAUSE_TIME + 0.5)
419 #define RCCAR_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_PULSE_TIME + 0.5)
420 #define RCCAR_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_1_PAUSE_TIME + 0.5)
421 #define RCCAR_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_0_PAUSE_TIME + 0.5)
422 #define RCCAR_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RCCAR_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
423
424 #define JVC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PULSE_TIME + 0.5)
425 #define JVC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PAUSE_TIME + 0.5)
426 #define JVC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_REPEAT_START_BIT_PAUSE_TIME + 0.5)
427 #define JVC_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_PULSE_TIME + 0.5)
428 #define JVC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_1_PAUSE_TIME + 0.5)
429 #define JVC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_0_PAUSE_TIME + 0.5)
430 #define JVC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * JVC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
431
432 #define NIKON_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_START_BIT_PULSE_TIME + 0.5)
433 #define NIKON_START_BIT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_START_BIT_PAUSE_TIME + 0.5)
434 #define NIKON_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_REPEAT_START_BIT_PAUSE_TIME + 0.5)
435 #define NIKON_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_PULSE_TIME + 0.5)
436 #define NIKON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_1_PAUSE_TIME + 0.5)
437 #define NIKON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_0_PAUSE_TIME + 0.5)
438 #define NIKON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
439
440 #define LEGO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PULSE_TIME + 0.5)
441 #define LEGO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PAUSE_TIME + 0.5)
442 #define LEGO_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_REPEAT_START_BIT_PAUSE_TIME + 0.5)
443 #define LEGO_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_PULSE_TIME + 0.5)
444 #define LEGO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_1_PAUSE_TIME + 0.5)
445 #define LEGO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_0_PAUSE_TIME + 0.5)
446 #define LEGO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * LEGO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
447
448 #define A1TVBOX_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_START_BIT_PULSE_TIME + 0.5)
449 #define A1TVBOX_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_START_BIT_PAUSE_TIME + 0.5)
450 #define A1TVBOX_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_BIT_PULSE_TIME + 0.5)
451 #define A1TVBOX_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_BIT_PAUSE_TIME + 0.5)
452 #define A1TVBOX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * A1TVBOX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
453 #define A1TVBOX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * A1TVBOX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
454
455 #define ROOMBA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_START_BIT_PULSE_TIME + 0.5)
456 #define ROOMBA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_START_BIT_PAUSE_TIME + 0.5)
457 #define ROOMBA_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_1_PULSE_TIME + 0.5)
458 #define ROOMBA_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_0_PULSE_TIME + 0.5)
459 #define ROOMBA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_1_PAUSE_TIME + 0.5)
460 #define ROOMBA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_0_PAUSE_TIME + 0.5)
461 #define ROOMBA_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * ROOMBA_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
462
463 #define PENTAX_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_START_BIT_PULSE_TIME + 0.5)
464 #define PENTAX_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_START_BIT_PAUSE_TIME + 0.5)
465 #define PENTAX_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_REPEAT_START_BIT_PAUSE_TIME + 0.5)
466 #define PENTAX_PULSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_PULSE_TIME + 0.5)
467 #define PENTAX_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_1_PAUSE_TIME + 0.5)
468 #define PENTAX_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_0_PAUSE_TIME + 0.5)
469 #define PENTAX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PENTAX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
470
471 #define ACP24_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_START_BIT_PULSE_TIME + 0.5)
472 #define ACP24_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_START_BIT_PAUSE_TIME + 0.5)
473 #define ACP24_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_REPEAT_START_BIT_PAUSE_TIME + 0.5)
474 #define ACP24_PULSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_PULSE_TIME + 0.5)
475 #define ACP24_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_1_PAUSE_TIME + 0.5)
476 #define ACP24_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_0_PAUSE_TIME + 0.5)
477 #define ACP24_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * ACP24_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
478
479 static volatile uint8_t irsnd_busy = 0;
480 static volatile uint8_t irsnd_protocol = 0;
481 static volatile uint8_t irsnd_buffer[9] = {0};
482 static volatile uint8_t irsnd_repeat = 0;
483 static volatile uint8_t irsnd_is_on = FALSE;
484
485 #if IRSND_USE_CALLBACK == 1
486 static void (*irsnd_callback_ptr) (uint8_t);
487 #endif // IRSND_USE_CALLBACK == 1
488
489 /*---------------------------------------------------------------------------------------------------------------------------------------------------
490 * Switch PWM on
491 *---------------------------------------------------------------------------------------------------------------------------------------------------
492 */
493 static void
494 irsnd_on (void)
495 {
496 if (! irsnd_is_on)
497 {
498 #ifndef ANALYZE
499 # if defined(PIC_C18) // PIC C18
500 PWMon();
501 // IRSND_PIN = 0; // output mode -> enable PWM outout pin (0=PWM on, 1=PWM off)
502
503 # elif defined (ARM_STM32) // STM32
504 TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCMode_PWM1); // enable PWM as OC-mode
505 TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())
506 TIM_Cmd(IRSND_TIMER, ENABLE); // enable counter
507
508 # elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY
509 analogWrite(IRSND_PIN, 33 * 255 / 100); // pwm 33%
510
511 # elif defined (__AVR_XMEGA__)
512 # if (IRSND_OCx == IRSND_XMEGA_OC0A) // use OC0A
513 XMEGA_Timer.CTRLB |= (1<<TC0_CCAEN_bp); // Compare A
514 # elif (IRSND_OCx == IRSND_XMEGA_OC0B) // use OC0B
515 XMEGA_Timer.CTRLB |= (1<<TC0_CCBEN_bp); // Compare B
516 # elif IRSND_OCx == IRSND_XMEGA_OC0C // use OC0C
517 XMEGA_Timer.CTRLB |= (1<<TC0_CCCEN_bp); // Compare C
518 # elif IRSND_OCx == IRSND_XMEGA_OC0D // use OC0D
519 XMEGA_Timer.CTRLB |= (1<<TC0_CCDEN_bp); // Compare D
520 # elif IRSND_OCx == IRSND_XMEGA_OC1A // use OC1A
521 XMEGA_Timer.CTRLB |= (1<<TC1_CCAEN_bp); // Compare A
522 # elif IRSND_OCx == IRSND_XMEGA_OC1B // use OC1B
523 XMEGA_Timer.CTRLB |= (1<<TC1_CCBEN_bp); // Compare B
524 # else
525 # error wrong value of IRSND_OCx
526 # endif // IRSND_OCx
527
528 # else // AVR
529 # if IRSND_OCx == IRSND_OC2 // use OC2
530 TCCR2 |= (1<<COM20)|(1<<WGM21); // toggle OC2 on compare match, clear Timer 2 at compare match OCR2
531 # elif IRSND_OCx == IRSND_OC2A // use OC2A
532 TCCR2A |= (1<<COM2A0)|(1<<WGM21); // toggle OC2A on compare match, clear Timer 2 at compare match OCR2A
533 # elif IRSND_OCx == IRSND_OC2B // use OC2B
534 TCCR2A |= (1<<COM2B0)|(1<<WGM21); // toggle OC2B on compare match, clear Timer 2 at compare match OCR2A (yes: A, not B!)
535 # elif IRSND_OCx == IRSND_OC0 // use OC0
536 TCCR0 |= (1<<COM00)|(1<<WGM01); // toggle OC0 on compare match, clear Timer 0 at compare match OCR0
537 # elif IRSND_OCx == IRSND_OC0A // use OC0A
538 TCCR0A |= (1<<COM0A0)|(1<<WGM01); // toggle OC0A on compare match, clear Timer 0 at compare match OCR0A
539 # elif IRSND_OCx == IRSND_OC0B // use OC0B
540 TCCR0A |= (1<<COM0B0)|(1<<WGM01); // toggle OC0B on compare match, clear Timer 0 at compare match OCR0A (yes: A, not B!)
541 # else
542 # error wrong value of IRSND_OCx
543 # endif // IRSND_OCx
544 # endif // C18
545 #endif // ANALYZE
546
547 #if IRSND_USE_CALLBACK == 1
548 if (irsnd_callback_ptr)
549 {
550 (*irsnd_callback_ptr) (TRUE);
551 }
552 #endif // IRSND_USE_CALLBACK == 1
553
554 irsnd_is_on = TRUE;
555 }
556 }
557
558 /*---------------------------------------------------------------------------------------------------------------------------------------------------
559 * Switch PWM off
560 * @details Switches PWM off
561 *---------------------------------------------------------------------------------------------------------------------------------------------------
562 */
563 static void
564 irsnd_off (void)
565 {
566 if (irsnd_is_on)
567 {
568 #ifndef ANALYZE
569
570 # if defined(PIC_C18) // PIC C18
571 PWMoff();
572 // IRSND_PIN = 1; //input mode -> disbale PWM output pin (0=PWM on, 1=PWM off)
573
574 # elif defined (ARM_STM32) // STM32
575 TIM_Cmd(IRSND_TIMER, DISABLE); // disable counter
576 TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_ForcedAction_InActive); // force output inactive
577 TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())
578 TIM_SetCounter(IRSND_TIMER, 0); // reset counter value
579
580 # elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY
581 analogWrite(IRSND_PIN, 0); // pwm off, LOW level
582
583 # elif defined (__AVR_XMEGA__)
584 # if (IRSND_OCx == IRSND_XMEGA_OC0A) // use OC0A
585 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCAEN_bp); // Compare A disconnected
586 # elif (IRSND_OCx == IRSND_XMEGA_OC0B) // use OC0B
587 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCBEN_bp); // Compare B disconnected
588 # elif IRSND_OCx == IRSND_XMEGA_OC0C // use OC0C
589 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCCEN_bp); // Compare C disconnected
590 # elif IRSND_OCx == IRSND_XMEGA_OC0D // use OC0D
591 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCDEN_bp); // Compare D disconnected
592 # elif IRSND_OCx == IRSND_XMEGA_OC1A // use OC1A
593 XMEGA_Timer.CTRLB &= ~(1<<TC1_CCAEN_bp); // Compare A disconnected
594 # elif IRSND_OCx == IRSND_XMEGA_OC1B // use OC1B
595 XMEGA_Timer.CTRLB &= ~(1<<TC1_CCBEN_bp); // Compare B disconnected
596 # else
597 # error wrong value of IRSND_OCx
598 # endif // IRSND_OCx
599
600 # else //AVR
601
602 # if IRSND_OCx == IRSND_OC2 // use OC2
603 TCCR2 &= ~(1<<COM20); // normal port operation, OC2 disconnected.
604 # elif IRSND_OCx == IRSND_OC2A // use OC2A
605 TCCR2A &= ~(1<<COM2A0); // normal port operation, OC2A disconnected.
606 # elif IRSND_OCx == IRSND_OC2B // use OC2B
607 TCCR2A &= ~(1<<COM2B0); // normal port operation, OC2B disconnected.
608 # elif IRSND_OCx == IRSND_OC0 // use OC0
609 TCCR0 &= ~(1<<COM00); // normal port operation, OC0 disconnected.
610 # elif IRSND_OCx == IRSND_OC0A // use OC0A
611 TCCR0A &= ~(1<<COM0A0); // normal port operation, OC0A disconnected.
612 # elif IRSND_OCx == IRSND_OC0B // use OC0B
613 TCCR0A &= ~(1<<COM0B0); // normal port operation, OC0B disconnected.
614 # else
615 # error wrong value of IRSND_OCx
616 # endif // IRSND_OCx
617 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low
618 # endif //C18
619 #endif // ANALYZE
620
621 #if IRSND_USE_CALLBACK == 1
622 if (irsnd_callback_ptr)
623 {
624 (*irsnd_callback_ptr) (FALSE);
625 }
626 #endif // IRSND_USE_CALLBACK == 1
627
628 irsnd_is_on = FALSE;
629 }
630 }
631
632 /*---------------------------------------------------------------------------------------------------------------------------------------------------
633 * Set PWM frequency
634 * @details sets pwm frequency
635 *---------------------------------------------------------------------------------------------------------------------------------------------------
636 */
637 #if defined(__12F1840)
638 extern void pwm_init(uint16_t freq);
639 #include <stdio.h>
640 #endif
641
642 static void
643 irsnd_set_freq (IRSND_FREQ_TYPE freq)
644 {
645 #ifndef ANALYZE
646 # if defined(PIC_C18) // PIC C18 or XC8
647 # if defined(__12F1840) // XC8
648 TRISA2=0;
649 PR2=freq;
650 CCP1M0=1;
651 CCP1M1=1;
652 CCP1M2=1;
653 CCP1M3=1;
654 DC1B0=1;
655 DC1B1=0;
656 CCPR1L = 0b01101001;
657 TMR2IF = 0;
658 TMR2ON=1;
659 CCP1CON &=(~0b0011); // p 197 "active high"
660 # else // PIC C18
661 OpenPWM(freq);
662 SetDCPWM( (uint16_t) (freq * 2) + 1); // freq*2 = Duty cycles 50%
663 # endif
664 PWMoff();
665 # elif defined (ARM_STM32) // STM32
666 static uint32_t TimeBaseFreq = 0;
667
668 if (TimeBaseFreq == 0)
669 {
670 RCC_ClocksTypeDef RCC_ClocksStructure;
671 /* Get system clocks and store timer clock in variable */
672 RCC_GetClocksFreq(&RCC_ClocksStructure);
673 # if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))
674 if (RCC_ClocksStructure.PCLK1_Frequency == RCC_ClocksStructure.HCLK_Frequency)
675 {
676 TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency;
677 }
678 else
679 {
680 TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency * 2;
681 }
682 # else
683 if (RCC_ClocksStructure.PCLK2_Frequency == RCC_ClocksStructure.HCLK_Frequency)
684 {
685 TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency;
686 }
687 else
688 {
689 TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency * 2;
690 }
691 # endif
692 }
693
694 freq = TimeBaseFreq/freq;
695
696 /* Set frequency */
697 TIM_SetAutoreload(IRSND_TIMER, freq - 1);
698 /* Set duty cycle */
699 TIM_SetCompare1(IRSND_TIMER, (freq + 1) / 2);
700
701 # elif defined (TEENSY_ARM_CORTEX_M4)
702 analogWriteResolution(8); // 8 bit
703 analogWriteFrequency(IRSND_PIN, freq);
704 analogWrite(IRSND_PIN, 0); // pwm off, LOW level
705
706 # elif defined (__AVR_XMEGA__)
707 XMEGA_Timer.CCA = freq;
708
709 # else // AVR
710
711 # if IRSND_OCx == IRSND_OC2
712 OCR2 = freq; // use register OCR2 for OC2
713 # elif IRSND_OCx == IRSND_OC2A // use OC2A
714 OCR2A = freq; // use register OCR2A for OC2A and OC2B!
715 # elif IRSND_OCx == IRSND_OC2B // use OC2B
716 OCR2A = freq; // use register OCR2A for OC2A and OC2B!
717 # elif IRSND_OCx == IRSND_OC0 // use OC0
718 OCR0 = freq; // use register OCR2 for OC2
719 # elif IRSND_OCx == IRSND_OC0A // use OC0A
720 OCR0A = freq; // use register OCR0A for OC0A and OC0B!
721 # elif IRSND_OCx == IRSND_OC0B // use OC0B
722 OCR0A = freq; // use register OCR0A for OC0A and OC0B!
723 # else
724 # error wrong value of IRSND_OCx
725 # endif
726 # endif //PIC_C18
727 #endif // ANALYZE
728 }
729
730 /*---------------------------------------------------------------------------------------------------------------------------------------------------
731 * Initialize the PWM
732 * @details Configures 0CR0A, 0CR0B and 0CR2B as PWM channels
733 *---------------------------------------------------------------------------------------------------------------------------------------------------
734 */
735 void
736 irsnd_init (void)
737 {
738 #ifndef ANALYZE
739 # if defined(PIC_C18) // PIC C18 or XC8 compiler
740 # if ! defined(__12F1840) // only C18:
741 OpenTimer;
742 # endif
743 irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency
744 IRSND_PIN = 0; // set IO to outout
745 PWMoff();
746 # elif defined (ARM_STM32) // STM32
747 GPIO_InitTypeDef GPIO_InitStructure;
748 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
749 TIM_OCInitTypeDef TIM_OCInitStructure;
750
751 /* GPIOx clock enable */
752 # if defined (ARM_STM32L1XX)
753 RCC_AHBPeriphClockCmd(IRSND_PORT_RCC, ENABLE);
754 # elif defined (ARM_STM32F10X)
755 RCC_APB2PeriphClockCmd(IRSND_PORT_RCC, ENABLE);
756 // RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); // only in case of remapping, not necessary for default port-timer mapping
757 # elif defined (ARM_STM32F4XX)
758 RCC_AHB1PeriphClockCmd(IRSND_PORT_RCC, ENABLE);
759 # endif
760
761 /* GPIO Configuration */
762 GPIO_InitStructure.GPIO_Pin = IRSND_BIT;
763 # if defined (ARM_STM32L1XX) || defined (ARM_STM32F4XX)
764 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
765 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
766 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
767 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
768 GPIO_Init(IRSND_PORT, &GPIO_InitStructure);
769 GPIO_PinAFConfig(IRSND_PORT, (uint8_t)IRSND_BIT_NUMBER, IRSND_GPIO_AF);
770 # elif defined (ARM_STM32F10X)
771 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
772 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
773 GPIO_Init(IRSND_PORT, &GPIO_InitStructure);
774 // GPIO_PinRemapConfig(GPIO_*Remap*_TIM[IRSND_TIMER_NUMBER], ENABLE); // only in case of remapping, not necessary for default port-timer mapping
775 # endif
776
777 /* TIMx clock enable */
778 # if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))
779 RCC_APB1PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);
780 # else
781 RCC_APB2PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);
782 # endif
783
784 /* Time base configuration */
785 TIM_TimeBaseStructure.TIM_Period = -1; // set dummy value (don't set to 0), will be initialized later
786 TIM_TimeBaseStructure.TIM_Prescaler = 0;
787 TIM_TimeBaseStructure.TIM_ClockDivision = 0;
788 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
789 TIM_TimeBaseInit(IRSND_TIMER, &TIM_TimeBaseStructure);
790
791 /* PWM1 Mode configuration */
792 TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
793 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
794 TIM_OCInitStructure.TIM_Pulse = 0; // will be initialized later
795 TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
796 TIM_OC1Init(IRSND_TIMER, &TIM_OCInitStructure);
797
798 /* Preload configuration */
799 TIM_ARRPreloadConfig(IRSND_TIMER, ENABLE);
800 TIM_OC1PreloadConfig(IRSND_TIMER, TIM_OCPreload_Enable);
801
802 irsnd_set_freq (IRSND_FREQ_36_KHZ); // set default frequency
803
804 # elif defined (TEENSY_ARM_CORTEX_M4)
805 if (!digitalPinHasPWM(IRSND_PIN))
806 {
807 return;
808 }
809
810 # elif defined (__AVR_XMEGA__)
811 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low
812 IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output
813
814 XMEGA_Timer.PER = 0xFFFF; //Topwert
815 XMEGA_Timer.CTRLB |= TC_WGMODE_FRQ_gc; //Modus: Frequenz entspricht CTC
816
817 # if AVR_PRESCALER == 8
818 XMEGA_Timer.CTRLA |= TC_CLKSEL_DIV8_gc; // start Timer prescaler = 8
819 # else
820 XMEGA_Timer.CTRLA |= TC_CLKSEL_DIV1_gc; // start Timer prescaler = 1
821 # endif
822
823 # else // AVR
824 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low
825 IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output
826
827 # if IRSND_OCx == IRSND_OC2 // use OC2
828 TCCR2 = (1<<WGM21); // CTC mode
829 # if AVR_PRESCALER == 8
830 TCCR2 |= (1<<CS21); // start Timer 2, prescaler = 8
831 # else
832 TCCR2 |= (1<<CS20); // start Timer 2, prescaler = 1
833 # endif
834 # elif IRSND_OCx == IRSND_OC2A || IRSND_OCx == IRSND_OC2B // use OC2A or OC2B
835 TCCR2A = (1<<WGM21); // CTC mode
836 # if AVR_PRESCALER == 8
837 TCCR2B = (1<<CS21); // start Timer 2, prescaler = 8
838 # else
839 TCCR2B = (1<<CS20); // start Timer 2, prescaler = 1
840 # endif
841 # elif IRSND_OCx == IRSND_OC0 // use OC0
842 TCCR0 = (1<<WGM01); // CTC mode
843 # if AVR_PRESCALER == 8
844 TCCR0 |= (1<<CS01); // start Timer 0, prescaler = 8
845 # else
846 TCCR0 |= (1<<CS00); // start Timer 0, prescaler = 1
847 # endif
848 # elif IRSND_OCx == IRSND_OC0A || IRSND_OCx == IRSND_OC0B // use OC0A or OC0B
849 TCCR0A = (1<<WGM01); // CTC mode
850 # if AVR_PRESCALER == 8
851 TCCR0B = (1<<CS01); // start Timer 0, prescaler = 8
852 # else
853 TCCR0B = (1<<CS00); // start Timer 0, prescaler = 1
854 # endif
855 # else
856 # error wrong value of IRSND_OCx
857 # endif
858 irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency
859 # endif //PIC_C18
860 #endif // ANALYZE
861 }
862
863 #if IRSND_USE_CALLBACK == 1
864 void
865 irsnd_set_callback_ptr (void (*cb)(uint8_t))
866 {
867 irsnd_callback_ptr = cb;
868 }
869 #endif // IRSND_USE_CALLBACK == 1
870
871 uint8_t
872 irsnd_is_busy (void)
873 {
874 return irsnd_busy;
875 }
876
877 static uint16_t
878 bitsrevervse (uint16_t x, uint8_t len)
879 {
880 uint16_t xx = 0;
881
882 while(len)
883 {
884 xx <<= 1;
885 if (x & 1)
886 {
887 xx |= 1;
888 }
889 x >>= 1;
890 len--;
891 }
892 return xx;
893 }
894
895
896 #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1
897 static uint8_t sircs_additional_bitlen;
898 #endif // IRSND_SUPPORT_SIRCS_PROTOCOL == 1
899
900 uint8_t
901 irsnd_send_data (IRMP_DATA * irmp_data_p, uint8_t do_wait)
902 {
903 #if IRSND_SUPPORT_RECS80_PROTOCOL == 1
904 static uint8_t toggle_bit_recs80;
905 #endif
906 #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1
907 static uint8_t toggle_bit_recs80ext;
908 #endif
909 #if IRSND_SUPPORT_RC5_PROTOCOL == 1
910 static uint8_t toggle_bit_rc5;
911 #endif
912 #if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1
913 static uint8_t toggle_bit_rc6;
914 #endif
915 #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1
916 static uint8_t toggle_bit_thomson;
917 #endif
918 uint16_t address;
919 uint16_t command;
920
921 if (do_wait)
922 {
923 while (irsnd_busy)
924 {
925 // do nothing;
926 }
927 }
928 else if (irsnd_busy)
929 {
930 return (FALSE);
931 }
932
933 irsnd_protocol = irmp_data_p->protocol;
934 irsnd_repeat = irmp_data_p->flags & IRSND_REPETITION_MASK;
935
936 switch (irsnd_protocol)
937 {
938 #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1
939 case IRMP_SIRCS_PROTOCOL:
940 {
941 // uint8_t sircs_additional_command_len;
942 uint8_t sircs_additional_address_len;
943
944 sircs_additional_bitlen = (irmp_data_p->address & 0xFF00) >> 8; // additional bitlen
945
946 if (sircs_additional_bitlen > 15 - SIRCS_MINIMUM_DATA_LEN)
947 {
948 // sircs_additional_command_len = 15 - SIRCS_MINIMUM_DATA_LEN;
949 sircs_additional_address_len = sircs_additional_bitlen - (15 - SIRCS_MINIMUM_DATA_LEN);
950 }
951 else
952 {
953 // sircs_additional_command_len = sircs_additional_bitlen;
954 sircs_additional_address_len = 0;
955 }
956
957 command = bitsrevervse (irmp_data_p->command, 15);
958
959 irsnd_buffer[0] = (command & 0x7F80) >> 7; // CCCCCCCC
960 irsnd_buffer[1] = (command & 0x007F) << 1; // CCCC****
961
962 if (sircs_additional_address_len > 0)
963 {
964 address = bitsrevervse (irmp_data_p->address, 5);
965 irsnd_buffer[1] |= (address & 0x0010) >> 4;
966 irsnd_buffer[2] = (address & 0x000F) << 4;
967 }
968 irsnd_busy = TRUE;
969 break;
970 }
971 #endif
972 #if IRSND_SUPPORT_NEC_PROTOCOL == 1
973 case IRMP_APPLE_PROTOCOL:
974 {
975 command = irmp_data_p->command | (irmp_data_p->address << 8); // store address as ID in upper byte of command
976 address = 0x87EE; // set fixed NEC-lookalike address (customer ID of apple)
977
978 address = bitsrevervse (address, NEC_ADDRESS_LEN);
979 command = bitsrevervse (command, NEC_COMMAND_LEN);
980
981 irsnd_protocol = IRMP_NEC_PROTOCOL; // APPLE protocol is NEC with id instead of inverted command
982
983 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
984 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
985 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC
986 irsnd_buffer[3] = 0x8B; // 10001011 (id)
987 irsnd_busy = TRUE;
988 break;
989 }
990 case IRMP_NEC_PROTOCOL:
991 {
992 address = bitsrevervse (irmp_data_p->address, NEC_ADDRESS_LEN);
993 command = bitsrevervse (irmp_data_p->command, NEC_COMMAND_LEN);
994
995 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
996 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
997 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC
998 irsnd_buffer[3] = ~((command & 0xFF00) >> 8); // cccccccc
999 irsnd_busy = TRUE;
1000 break;
1001 }
1002 #endif
1003 #if IRSND_SUPPORT_NEC16_PROTOCOL == 1
1004 case IRMP_NEC16_PROTOCOL:
1005 {
1006 address = bitsrevervse (irmp_data_p->address, NEC16_ADDRESS_LEN);
1007 command = bitsrevervse (irmp_data_p->command, NEC16_COMMAND_LEN);
1008
1009 irsnd_buffer[0] = (address & 0x00FF); // AAAAAAAA
1010 irsnd_buffer[1] = (command & 0x00FF); // CCCCCCCC
1011 irsnd_busy = TRUE;
1012 break;
1013 }
1014 #endif
1015 #if IRSND_SUPPORT_NEC42_PROTOCOL == 1
1016 case IRMP_NEC42_PROTOCOL:
1017 {
1018 address = bitsrevervse (irmp_data_p->address, NEC42_ADDRESS_LEN);
1019 command = bitsrevervse (irmp_data_p->command, NEC42_COMMAND_LEN);
1020
1021 irsnd_buffer[0] = ( (address & 0x1FE0) >> 5); // AAAAAAAA
1022 irsnd_buffer[1] = ( (address & 0x001F) << 3) | ((~address & 0x1C00) >> 10); // AAAAAaaa
1023 irsnd_buffer[2] = ((~address & 0x03FC) >> 2); // aaaaaaaa
1024 irsnd_buffer[3] = ((~address & 0x0003) << 6) | ( (command & 0x00FC) >> 2); // aaCCCCCC
1025 irsnd_buffer[4] = ( (command & 0x0003) << 6) | ((~command & 0x00FC) >> 2); // CCcccccc
1026 irsnd_buffer[5] = ((~command & 0x0003) << 6); // cc
1027 irsnd_busy = TRUE;
1028 break;
1029 }
1030 #endif
1031 #if IRSND_SUPPORT_LGAIR_PROTOCOL == 1
1032 case IRMP_LGAIR_PROTOCOL:
1033 {
1034 address = irmp_data_p->address;
1035 command = irmp_data_p->command;
1036
1037 irsnd_buffer[0] = ( (address & 0x00FF)); // AAAAAAAA
1038 irsnd_buffer[1] = ( (command & 0xFF00) >> 8); // CCCCCCCC
1039 irsnd_buffer[2] = ( (command & 0x00FF)); // CCCCCCCC
1040 irsnd_buffer[3] = (( ((command & 0xF000) >> 12) + // checksum
1041 ((command & 0x0F00) >> 8) +
1042 ((command & 0x00F0) >>4 ) +
1043 ((command & 0x000F))) & 0x000F) << 4;
1044 irsnd_busy = TRUE;
1045 break;
1046 }
1047 #endif
1048 #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1
1049 case IRMP_SAMSUNG_PROTOCOL:
1050 {
1051 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);
1052 command = bitsrevervse (irmp_data_p->command, SAMSUNG_COMMAND_LEN);
1053
1054 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1055 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1056 irsnd_buffer[2] = (command & 0x00F0) | ((command & 0xF000) >> 12); // IIIICCCC
1057 irsnd_buffer[3] = ((command & 0x0F00) >> 4) | ((~(command & 0xF000) >> 12) & 0x0F); // CCCCcccc
1058 irsnd_buffer[4] = (~(command & 0x0F00) >> 4) & 0xF0; // cccc0000
1059 irsnd_busy = TRUE;
1060 break;
1061 }
1062 case IRMP_SAMSUNG32_PROTOCOL:
1063 {
1064 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);
1065 command = bitsrevervse (irmp_data_p->command, SAMSUNG32_COMMAND_LEN);
1066
1067 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1068 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1069 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC
1070 irsnd_buffer[3] = (command & 0x00FF); // CCCCCCCC
1071 irsnd_busy = TRUE;
1072 break;
1073 }
1074 #endif
1075 #if IRSND_SUPPORT_SAMSUNG48_PROTOCOL == 1
1076 case IRMP_SAMSUNG48_PROTOCOL:
1077 {
1078 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);
1079 command = bitsrevervse (irmp_data_p->command, 16);
1080
1081 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1082 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1083 irsnd_buffer[2] = ((command & 0xFF00) >> 8); // CCCCCCCC
1084 irsnd_buffer[3] = ~((command & 0xFF00) >> 8); // cccccccc
1085 irsnd_buffer[4] = (command & 0x00FF); // CCCCCCCC
1086 irsnd_buffer[5] = ~(command & 0x00FF); // cccccccc
1087 irsnd_busy = TRUE;
1088 break;
1089 }
1090 #endif
1091 #if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1
1092 case IRMP_MATSUSHITA_PROTOCOL:
1093 {
1094 address = bitsrevervse (irmp_data_p->address, MATSUSHITA_ADDRESS_LEN);
1095 command = bitsrevervse (irmp_data_p->command, MATSUSHITA_COMMAND_LEN);
1096
1097 irsnd_buffer[0] = (command & 0x0FF0) >> 4; // CCCCCCCC
1098 irsnd_buffer[1] = ((command & 0x000F) << 4) | ((address & 0x0F00) >> 8); // CCCCAAAA
1099 irsnd_buffer[2] = (address & 0x00FF); // AAAAAAAA
1100 irsnd_busy = TRUE;
1101 break;
1102 }
1103 #endif
1104 #if IRSND_SUPPORT_TECHNICS_PROTOCOL == 1
1105 case IRMP_TECHNICS_PROTOCOL:
1106 {
1107 command = bitsrevervse (irmp_data_p->command, TECHNICS_COMMAND_LEN);
1108
1109 irsnd_buffer[0] = (command & 0x07FC) >> 3; // CCCCCCCC
1110 irsnd_buffer[1] = ((command & 0x0007) << 5) | ((~command & 0x07C0) >> 6); // CCCccccc
1111 irsnd_buffer[2] = (~command & 0x003F) << 2; // cccccc
1112 irsnd_busy = TRUE;
1113 break;
1114 }
1115 #endif
1116 #if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1
1117 case IRMP_KASEIKYO_PROTOCOL:
1118 {
1119 uint8_t xor_value;
1120 uint16_t genre2;
1121
1122 address = bitsrevervse (irmp_data_p->address, KASEIKYO_ADDRESS_LEN);
1123 command = bitsrevervse (irmp_data_p->command, KASEIKYO_COMMAND_LEN + 4);
1124 genre2 = bitsrevervse ((irmp_data_p->flags & ~IRSND_REPETITION_MASK) >> 4, 4);
1125
1126 xor_value = ((address & 0x000F) ^ ((address & 0x00F0) >> 4) ^ ((address & 0x0F00) >> 8) ^ ((address & 0xF000) >> 12)) & 0x0F;
1127
1128 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1129 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1130 irsnd_buffer[2] = xor_value << 4 | (command & 0x000F); // XXXXCCCC
1131 irsnd_buffer[3] = (genre2 << 4) | (command & 0xF000) >> 12; // ggggCCCC
1132 irsnd_buffer[4] = (command & 0x0FF0) >> 4; // CCCCCCCC
1133
1134 xor_value = irsnd_buffer[2] ^ irsnd_buffer[3] ^ irsnd_buffer[4];
1135
1136 irsnd_buffer[5] = xor_value;
1137 irsnd_busy = TRUE;
1138 break;
1139 }
1140 #endif
1141 #if IRSND_SUPPORT_PANASONIC_PROTOCOL == 1
1142 case IRMP_PANASONIC_PROTOCOL:
1143 {
1144 address = bitsrevervse (irmp_data_p->address, PANASONIC_ADDRESS_LEN);
1145 command = bitsrevervse (irmp_data_p->command, PANASONIC_COMMAND_LEN);
1146
1147 irsnd_buffer[0] = 0x40; // 01000000
1148 irsnd_buffer[1] = 0x04; // 00000100
1149 irsnd_buffer[2] = 0x01; // 00000001
1150 irsnd_buffer[3] = (address & 0xFF00) >> 8; // AAAAAAAA
1151 irsnd_buffer[4] = (address & 0x00FF); // AAAAAAAA
1152 irsnd_buffer[5] = (command & 0xFF00) >> 8; // CCCCCCCC
1153 irsnd_buffer[6] = (command & 0x00FF); // CCCCCCCC
1154
1155 irsnd_busy = TRUE;
1156 break;
1157 }
1158 #endif
1159 #if IRSND_SUPPORT_RECS80_PROTOCOL == 1
1160 case IRMP_RECS80_PROTOCOL:
1161 {
1162 toggle_bit_recs80 = toggle_bit_recs80 ? 0x00 : 0x40;
1163
1164 irsnd_buffer[0] = 0x80 | toggle_bit_recs80 | ((irmp_data_p->address & 0x0007) << 3) |
1165 ((irmp_data_p->command & 0x0038) >> 3); // STAAACCC
1166 irsnd_buffer[1] = (irmp_data_p->command & 0x07) << 5; // CCC00000
1167 irsnd_busy = TRUE;
1168 break;
1169 }
1170 #endif
1171 #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1
1172 case IRMP_RECS80EXT_PROTOCOL:
1173 {
1174 toggle_bit_recs80ext = toggle_bit_recs80ext ? 0x00 : 0x40;
1175
1176 irsnd_buffer[0] = 0x80 | toggle_bit_recs80ext | ((irmp_data_p->address & 0x000F) << 2) |
1177 ((irmp_data_p->command & 0x0030) >> 4); // STAAAACC
1178 irsnd_buffer[1] = (irmp_data_p->command & 0x0F) << 4; // CCCC0000
1179 irsnd_busy = TRUE;
1180 break;
1181 }
1182 #endif
1183 #if IRSND_SUPPORT_RC5_PROTOCOL == 1
1184 case IRMP_RC5_PROTOCOL:
1185 {
1186 toggle_bit_rc5 = toggle_bit_rc5 ? 0x00 : 0x40;
1187
1188 irsnd_buffer[0] = ((irmp_data_p->command & 0x40) ? 0x00 : 0x80) | toggle_bit_rc5 |
1189 ((irmp_data_p->address & 0x001F) << 1) | ((irmp_data_p->command & 0x20) >> 5); // CTAAAAAC
1190 irsnd_buffer[1] = (irmp_data_p->command & 0x1F) << 3; // CCCCC000
1191 irsnd_busy = TRUE;
1192 break;
1193 }
1194 #endif
1195 #if IRSND_SUPPORT_RC6_PROTOCOL == 1
1196 case IRMP_RC6_PROTOCOL:
1197 {
1198 toggle_bit_rc6 = toggle_bit_rc6 ? 0x00 : 0x08;
1199
1200 irsnd_buffer[0] = 0x80 | toggle_bit_rc6 | ((irmp_data_p->address & 0x00E0) >> 5); // 1MMMTAAA, MMM = 000
1201 irsnd_buffer[1] = ((irmp_data_p->address & 0x001F) << 3) | ((irmp_data_p->command & 0xE0) >> 5); // AAAAACCC
1202 irsnd_buffer[2] = (irmp_data_p->command & 0x1F) << 3; // CCCCC
1203 irsnd_busy = TRUE;
1204 break;
1205 }
1206 #endif
1207 #if IRSND_SUPPORT_RC6A_PROTOCOL == 1
1208 case IRMP_RC6A_PROTOCOL:
1209 {
1210 toggle_bit_rc6 = toggle_bit_rc6 ? 0x00 : 0x08;
1211
1212 irsnd_buffer[0] = 0x80 | 0x60 | ((irmp_data_p->address & 0x3000) >> 12); // 1MMMT0AA, MMM = 110
1213 irsnd_buffer[1] = ((irmp_data_p->address & 0x0FFF) >> 4) ; // AAAAAAAA
1214 irsnd_buffer[2] = ((irmp_data_p->address & 0x000F) << 4) | ((irmp_data_p->command & 0xF000) >> 12) | toggle_bit_rc6; // AAAACCCC
1215 irsnd_buffer[3] = (irmp_data_p->command & 0x0FF0) >> 4; // CCCCCCCC
1216 irsnd_buffer[4] = (irmp_data_p->command & 0x000F) << 4; // CCCC
1217 irsnd_busy = TRUE;
1218 break;
1219 }
1220 #endif
1221 #if IRSND_SUPPORT_DENON_PROTOCOL == 1
1222 case IRMP_DENON_PROTOCOL:
1223 {
1224 irsnd_buffer[0] = ((irmp_data_p->address & 0x1F) << 3) | ((irmp_data_p->command & 0x0380) >> 7); // AAAAACCC (1st frame)
1225 irsnd_buffer[1] = (irmp_data_p->command & 0x7F) << 1; // CCCCCCC
1226 irsnd_buffer[2] = ((irmp_data_p->address & 0x1F) << 3) | (((~irmp_data_p->command) & 0x0380) >> 7); // AAAAAccc (2nd frame)
1227 irsnd_buffer[3] = (~(irmp_data_p->command) & 0x7F) << 1; // ccccccc
1228 irsnd_busy = TRUE;
1229 break;
1230 }
1231 #endif
1232 #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1
1233 case IRMP_THOMSON_PROTOCOL:
1234 {
1235 toggle_bit_thomson = toggle_bit_thomson ? 0x00 : 0x08;
1236
1237 irsnd_buffer[0] = ((irmp_data_p->address & 0x0F) << 4) | toggle_bit_thomson | ((irmp_data_p->command & 0x0070) >> 4); // AAAATCCC (1st frame)
1238 irsnd_buffer[1] = (irmp_data_p->command & 0x0F) << 4; // CCCC
1239 irsnd_busy = TRUE;
1240 break;
1241 }
1242 #endif
1243 #if IRSND_SUPPORT_BOSE_PROTOCOL == 1
1244 case IRMP_BOSE_PROTOCOL:
1245 {
1246 command = bitsrevervse (irmp_data_p->command, BOSE_COMMAND_LEN);
1247
1248 irsnd_buffer[0] = (command & 0xFF00) >> 8; // CCCCCCCC
1249 irsnd_buffer[1] = ~((command & 0xFF00) >> 8); // cccccccc
1250 irsnd_busy = TRUE;
1251 break;
1252 }
1253 #endif
1254 #if IRSND_SUPPORT_NUBERT_PROTOCOL == 1
1255 case IRMP_NUBERT_PROTOCOL:
1256 {
1257 irsnd_buffer[0] = irmp_data_p->command >> 2; // CCCCCCCC
1258 irsnd_buffer[1] = (irmp_data_p->command & 0x0003) << 6; // CC000000
1259 irsnd_busy = TRUE;
1260 break;
1261 }
1262 #endif
1263 #if IRSND_SUPPORT_FAN_PROTOCOL == 1
1264 case IRMP_FAN_PROTOCOL:
1265 {
1266 irsnd_buffer[0] = irmp_data_p->command >> 3; // CCCCCCCC
1267 irsnd_buffer[1] = (irmp_data_p->command & 0x0007) << 5; // CCC00000
1268 irsnd_busy = TRUE;
1269 break;
1270 }
1271 #endif
1272 #if IRSND_SUPPORT_SPEAKER_PROTOCOL == 1
1273 case IRMP_SPEAKER_PROTOCOL:
1274 {
1275 irsnd_buffer[0] = irmp_data_p->command >> 2; // CCCCCCCC
1276 irsnd_buffer[1] = (irmp_data_p->command & 0x0003) << 6; // CC000000
1277 irsnd_busy = TRUE;
1278 break;
1279 }
1280 #endif
1281 #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1
1282 case IRMP_BANG_OLUFSEN_PROTOCOL:
1283 {
1284 irsnd_buffer[0] = irmp_data_p->command >> 11; // SXSCCCCC
1285 irsnd_buffer[1] = irmp_data_p->command >> 3; // CCCCCCCC
1286 irsnd_buffer[2] = (irmp_data_p->command & 0x0007) << 5; // CCC00000
1287 irsnd_busy = TRUE;
1288 break;
1289 }
1290 #endif
1291 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1
1292 case IRMP_GRUNDIG_PROTOCOL:
1293 {
1294 command = bitsrevervse (irmp_data_p->command, TELEFUNKEN_COMMAND_LEN);
1295
1296 irsnd_buffer[0] = 0xFF; // S1111111 (1st frame)
1297 irsnd_buffer[1] = 0xC0; // 11
1298 irsnd_buffer[2] = 0x80 | (command >> 2); // SCCCCCCC (2nd frame)
1299 irsnd_buffer[3] = (command << 6) & 0xC0; // CC
1300
1301 irsnd_busy = TRUE;
1302 break;
1303 }
1304 #endif
1305 #if IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1
1306 case IRMP_TELEFUNKEN_PROTOCOL:
1307 {
1308 irsnd_buffer[0] = irmp_data_p->command >> 7; // CCCCCCCC
1309 irsnd_buffer[1] = (irmp_data_p->command << 1) & 0xff; // CCCCCCC
1310
1311 irsnd_busy = TRUE;
1312 break;
1313 }
1314 #endif
1315 #if IRSND_SUPPORT_IR60_PROTOCOL == 1
1316 case IRMP_IR60_PROTOCOL:
1317 {
1318 command = (bitsrevervse (0x7d, IR60_COMMAND_LEN) << 7) | bitsrevervse (irmp_data_p->command, IR60_COMMAND_LEN);
1319 #if 0
1320 irsnd_buffer[0] = command >> 6 | 0x01; // 1011111S (start instruction frame)
1321 irsnd_buffer[1] = (command & 0x7F) << 1; // CCCCCCC_ (2nd frame)
1322 #else
1323 irsnd_buffer[0] = ((command & 0x7F) << 1) | 0x01; // CCCCCCCS (1st frame)
1324 irsnd_buffer[1] = command >> 6; // 1011111_ (start instruction frame)
1325 #endif
1326
1327 irsnd_busy = TRUE;
1328 break;
1329 }
1330 #endif
1331 #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1
1332 case IRMP_NOKIA_PROTOCOL:
1333 {
1334 address = bitsrevervse (irmp_data_p->address, NOKIA_ADDRESS_LEN);
1335 command = bitsrevervse (irmp_data_p->command, NOKIA_COMMAND_LEN);
1336
1337 irsnd_buffer[0] = 0xBF; // S0111111 (1st + 3rd frame)
1338 irsnd_buffer[1] = 0xFF; // 11111111
1339 irsnd_buffer[2] = 0x80; // 1
1340 irsnd_buffer[3] = 0x80 | command >> 1; // SCCCCCCC (2nd frame)
1341 irsnd_buffer[4] = (command << 7) | (address >> 1); // CAAAAAAA
1342 irsnd_buffer[5] = (address << 7); // A
1343
1344 irsnd_busy = TRUE;
1345 break;
1346 }
1347 #endif
1348 #if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1
1349 case IRMP_SIEMENS_PROTOCOL:
1350 {
1351 irsnd_buffer[0] = ((irmp_data_p->address & 0x07FF) >> 3); // AAAAAAAA
1352 irsnd_buffer[1] = ((irmp_data_p->address & 0x0007) << 5) | ((irmp_data_p->command >> 5) & 0x1F); // AAACCCCC
1353 irsnd_buffer[2] = ((irmp_data_p->command & 0x001F) << 3) | ((~irmp_data_p->command & 0x01) << 2); // CCCCCc
1354
1355 irsnd_busy = TRUE;
1356 break;
1357 }
1358 #endif
1359 #if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1
1360 case IRMP_RUWIDO_PROTOCOL:
1361 {
1362 irsnd_buffer[0] = ((irmp_data_p->address & 0x01FF) >> 1); // AAAAAAAA
1363 irsnd_buffer[1] = ((irmp_data_p->address & 0x0001) << 7) | ((irmp_data_p->command & 0x7F)); // ACCCCCCC
1364 irsnd_buffer[2] = ((~irmp_data_p->command & 0x01) << 7); // c
1365 irsnd_busy = TRUE;
1366 break;
1367 }
1368 #endif
1369 #if IRSND_SUPPORT_FDC_PROTOCOL == 1
1370 case IRMP_FDC_PROTOCOL:
1371 {
1372 address = bitsrevervse (irmp_data_p->address, FDC_ADDRESS_LEN);
1373 command = bitsrevervse (irmp_data_p->command, FDC_COMMAND_LEN);
1374
1375 irsnd_buffer[0] = (address & 0xFF); // AAAAAAAA
1376 irsnd_buffer[1] = 0; // 00000000
1377 irsnd_buffer[2] = 0; // 0000RRRR
1378 irsnd_buffer[3] = (command & 0xFF); // CCCCCCCC
1379 irsnd_buffer[4] = ~(command & 0xFF); // cccccccc
1380 irsnd_busy = TRUE;
1381 break;
1382 }
1383 #endif
1384 #if IRSND_SUPPORT_RCCAR_PROTOCOL == 1
1385 case IRMP_RCCAR_PROTOCOL:
1386 {
1387 address = bitsrevervse (irmp_data_p->address, 2); // A0 A1
1388 command = bitsrevervse (irmp_data_p->command, RCCAR_COMMAND_LEN - 2); // D0 D1 D2 D3 D4 D5 D6 D7 C0 C1 V
1389
1390 irsnd_buffer[0] = ((command & 0x06) << 5) | ((address & 0x0003) << 4) | ((command & 0x0780) >> 7); // C0 C1 A0 A1 D0 D1 D2 D3
1391 irsnd_buffer[1] = ((command & 0x78) << 1) | ((command & 0x0001) << 3); // D4 D5 D6 D7 V 0 0 0
1392
1393 irsnd_busy = TRUE;
1394 break;
1395 }
1396 #endif
1397 #if IRSND_SUPPORT_JVC_PROTOCOL == 1
1398 case IRMP_JVC_PROTOCOL:
1399 {
1400 address = bitsrevervse (irmp_data_p->address, JVC_ADDRESS_LEN);
1401 command = bitsrevervse (irmp_data_p->command, JVC_COMMAND_LEN);
1402
1403 irsnd_buffer[0] = ((address & 0x000F) << 4) | (command & 0x0F00) >> 8; // AAAACCCC
1404 irsnd_buffer[1] = (command & 0x00FF); // CCCCCCCC
1405
1406 irsnd_busy = TRUE;
1407 break;
1408 }
1409 #endif
1410 #if IRSND_SUPPORT_NIKON_PROTOCOL == 1
1411 case IRMP_NIKON_PROTOCOL:
1412 {
1413 irsnd_buffer[0] = (irmp_data_p->command & 0x0003) << 6; // CC
1414 irsnd_busy = TRUE;
1415 break;
1416 }
1417 #endif
1418 #if IRSND_SUPPORT_LEGO_PROTOCOL == 1
1419 case IRMP_LEGO_PROTOCOL:
1420 {
1421 uint8_t crc = 0x0F ^ ((irmp_data_p->command & 0x0F00) >> 8) ^ ((irmp_data_p->command & 0x00F0) >> 4) ^ (irmp_data_p->command & 0x000F);
1422
1423 irsnd_buffer[0] = (irmp_data_p->command & 0x0FF0) >> 4; // CCCCCCCC
1424 irsnd_buffer[1] = ((irmp_data_p->command & 0x000F) << 4) | crc; // CCCCcccc
1425 irsnd_busy = TRUE;
1426 break;
1427 }
1428 #endif
1429 #if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1
1430 case IRMP_A1TVBOX_PROTOCOL:
1431 {
1432 irsnd_buffer[0] = 0x80 | (irmp_data_p->address >> 2); // 10AAAAAA
1433 irsnd_buffer[1] = (irmp_data_p->address << 6) | (irmp_data_p->command >> 2); // AACCCCCC
1434 irsnd_buffer[2] = (irmp_data_p->command << 6); // CC
1435
1436 irsnd_busy = TRUE;
1437 break;
1438 }
1439 #endif
1440 #if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1
1441 case IRMP_ROOMBA_PROTOCOL:
1442 {
1443 irsnd_buffer[0] = (irmp_data_p->command & 0x7F) << 1; // CCCCCCC.
1444 irsnd_busy = TRUE;
1445 break;
1446 }
1447 #endif
1448 #if IRSND_SUPPORT_PENTAX_PROTOCOL == 1
1449 case IRMP_PENTAX_PROTOCOL:
1450 {
1451 irsnd_buffer[0] = (irmp_data_p->command & 0x3F) << 2; // CCCCCC..
1452 irsnd_busy = TRUE;
1453 break;
1454 }
1455 #endif
1456 #if IRSND_SUPPORT_ACP24_PROTOCOL == 1
1457 # define ACP_SET_BIT(acp24_bitno, c, irmp_bitno) \
1458 do \
1459 { \
1460 if ((c) & (1<<(irmp_bitno))) \
1461 { \
1462 irsnd_buffer[((acp24_bitno)>>3)] |= 1 << (((7 - (acp24_bitno)) & 0x07)); \
1463 } \
1464 } while (0)
1465
1466 case IRMP_ACP24_PROTOCOL:
1467 {
1468 uint16_t cmd = irmp_data_p->command;
1469 uint8_t i;
1470
1471 address = bitsrevervse (irmp_data_p->address, ACP24_ADDRESS_LEN);
1472
1473 for (i = 0; i < 8; i++)
1474 {
1475 irsnd_buffer[i] = 0x00; // CCCCCCCC
1476 }
1477
1478 // ACP24-Frame:
1479 // 1 2 3 4 5 6
1480 // 0123456789012345678901234567890123456789012345678901234567890123456789
1481 // N VVMMM ? ??? t vmA x y TTTT
1482 //
1483 // irmp_data_p->command:
1484 //
1485 // 5432109876543210
1486 // NAVVvMMMmtxyTTTT
1487
1488 ACP_SET_BIT( 0, cmd, 15);
1489 ACP_SET_BIT(24, cmd, 14);
1490 ACP_SET_BIT( 2, cmd, 13);
1491 ACP_SET_BIT( 3, cmd, 12);
1492 ACP_SET_BIT(22, cmd, 11);
1493 ACP_SET_BIT( 4, cmd, 10);
1494 ACP_SET_BIT( 5, cmd, 9);
1495 ACP_SET_BIT( 6, cmd, 8);
1496 ACP_SET_BIT(23, cmd, 7);
1497 ACP_SET_BIT(20, cmd, 6);
1498 ACP_SET_BIT(26, cmd, 5);
1499 ACP_SET_BIT(44, cmd, 4);
1500 ACP_SET_BIT(66, cmd, 3);
1501 ACP_SET_BIT(67, cmd, 2);
1502 ACP_SET_BIT(68, cmd, 1);
1503 ACP_SET_BIT(69, cmd, 0);
1504
1505 irsnd_busy = TRUE;
1506 break;
1507 }
1508 #endif
1509
1510 default:
1511 {
1512 break;
1513 }
1514 }
1515
1516 return irsnd_busy;
1517 }
1518
1519 void
1520 irsnd_stop (void)
1521 {
1522 irsnd_repeat = 0;
1523 }
1524
1525 /*---------------------------------------------------------------------------------------------------------------------------------------------------
1526 * ISR routine
1527 * @details ISR routine, called 10000 times per second
1528 *---------------------------------------------------------------------------------------------------------------------------------------------------
1529 */
1530 uint8_t
1531 irsnd_ISR (void)
1532 {
1533 static uint8_t send_trailer = FALSE;
1534 static uint8_t current_bit = 0xFF;
1535 static uint8_t pulse_counter = 0;
1536 static IRSND_PAUSE_LEN pause_counter = 0;
1537 static uint8_t startbit_pulse_len = 0;
1538 static IRSND_PAUSE_LEN startbit_pause_len = 0;
1539 static uint8_t pulse_1_len = 0;
1540 static uint8_t pause_1_len = 0;
1541 static uint8_t pulse_0_len = 0;
1542 static uint8_t pause_0_len = 0;
1543 static uint8_t has_stop_bit = 0;
1544 static uint8_t new_frame = TRUE;
1545 static uint8_t complete_data_len = 0;
1546 static uint8_t n_repeat_frames = 0; // number of repetition frames
1547 static uint8_t n_auto_repetitions = 0; // number of auto_repetitions
1548 static uint8_t auto_repetition_counter = 0; // auto_repetition counter
1549 static uint16_t auto_repetition_pause_len = 0; // pause before auto_repetition, uint16_t!
1550 static uint16_t auto_repetition_pause_counter = 0; // pause before auto_repetition, uint16_t!
1551 static uint8_t repeat_counter = 0; // repeat counter
1552 static uint16_t repeat_frame_pause_len = 0; // pause before repeat, uint16_t!
1553 static uint16_t packet_repeat_pause_counter = 0; // pause before repeat, uint16_t!
1554 #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1
1555 static uint8_t last_bit_value;
1556 #endif
1557 static uint8_t pulse_len = 0xFF;
1558 static IRSND_PAUSE_LEN pause_len = 0xFF;
1559
1560 if (irsnd_busy)
1561 {
1562 if (current_bit == 0xFF && new_frame) // start of transmission...
1563 {
1564 if (auto_repetition_counter > 0)
1565 {
1566 auto_repetition_pause_counter++;
1567
1568 if (auto_repetition_pause_counter >= auto_repetition_pause_len)
1569 {
1570 auto_repetition_pause_counter = 0;
1571
1572 #if IRSND_SUPPORT_DENON_PROTOCOL == 1
1573 if (irsnd_protocol == IRMP_DENON_PROTOCOL) // n'th denon frame
1574 {
1575 current_bit = 16;
1576 complete_data_len = 2 * DENON_COMPLETE_DATA_LEN + 1;
1577 }
1578 else
1579 #endif
1580 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1
1581 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL) // n'th grundig frame
1582 {
1583 current_bit = 15;
1584 complete_data_len = 16 + GRUNDIG_COMPLETE_DATA_LEN;
1585 }
1586 else
1587 #endif
1588 #if IRSND_SUPPORT_IR60_PROTOCOL == 1
1589 if (irsnd_protocol == IRMP_IR60_PROTOCOL) // n'th IR60 frame
1590 {
1591 current_bit = 7;
1592 complete_data_len = 2 * IR60_COMPLETE_DATA_LEN + 1;
1593 }
1594 else
1595 #endif
1596 #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1
1597 if (irsnd_protocol == IRMP_NOKIA_PROTOCOL) // n'th nokia frame
1598 {
1599 if (auto_repetition_counter + 1 < n_auto_repetitions)
1600 {
1601 current_bit = 23;
1602 complete_data_len = 24 + NOKIA_COMPLETE_DATA_LEN;
1603 }
1604 else // nokia stop frame
1605 {
1606 current_bit = 0xFF;
1607 complete_data_len = NOKIA_COMPLETE_DATA_LEN;
1608 }
1609 }
1610 else
1611 #endif
1612 {
1613 ;
1614 }
1615 }
1616 else
1617 {
1618 #ifdef ANALYZE
1619 if (irsnd_is_on)
1620 {
1621 putchar ('0');
1622 }
1623 else
1624 {
1625 putchar ('1');
1626 }
1627 #endif
1628 return irsnd_busy;
1629 }
1630 }
1631 else if (packet_repeat_pause_counter < repeat_frame_pause_len)
1632 {
1633 packet_repeat_pause_counter++;
1634 #ifdef ANALYZE
1635 if (irsnd_is_on)
1636 {
1637 putchar ('0');
1638 }
1639 else
1640 {
1641 putchar ('1');
1642 }
1643 #endif
1644 return irsnd_busy;
1645 }
1646 else
1647 {
1648 if (send_trailer)
1649 {
1650 irsnd_busy = FALSE;
1651 send_trailer = FALSE;
1652 return irsnd_busy;
1653 }
1654
1655 n_repeat_frames = irsnd_repeat;
1656
1657 if (n_repeat_frames == IRSND_ENDLESS_REPETITION)
1658 {
1659 n_repeat_frames = 255;
1660 }
1661
1662 packet_repeat_pause_counter = 0;
1663 pulse_counter = 0;
1664 pause_counter = 0;
1665
1666 switch (irsnd_protocol)
1667 {
1668 #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1
1669 case IRMP_SIRCS_PROTOCOL:
1670 {
1671 startbit_pulse_len = SIRCS_START_BIT_PULSE_LEN;
1672 startbit_pause_len = SIRCS_START_BIT_PAUSE_LEN - 1;
1673 pulse_1_len = SIRCS_1_PULSE_LEN;
1674 pause_1_len = SIRCS_PAUSE_LEN - 1;
1675 pulse_0_len = SIRCS_0_PULSE_LEN;
1676 pause_0_len = SIRCS_PAUSE_LEN - 1;
1677 has_stop_bit = SIRCS_STOP_BIT;
1678 complete_data_len = SIRCS_MINIMUM_DATA_LEN + sircs_additional_bitlen;
1679 n_auto_repetitions = (repeat_counter == 0) ? SIRCS_FRAMES : 1; // 3 frames auto repetition if first frame
1680 auto_repetition_pause_len = SIRCS_AUTO_REPETITION_PAUSE_LEN; // 25ms pause
1681 repeat_frame_pause_len = SIRCS_FRAME_REPEAT_PAUSE_LEN;
1682 irsnd_set_freq (IRSND_FREQ_40_KHZ);
1683 break;
1684 }
1685 #endif
1686 #if IRSND_SUPPORT_NEC_PROTOCOL == 1
1687 case IRMP_NEC_PROTOCOL:
1688 {
1689 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;
1690
1691 if (repeat_counter > 0)
1692 {
1693 startbit_pause_len = NEC_REPEAT_START_BIT_PAUSE_LEN - 1;
1694 complete_data_len = 0;
1695 }
1696 else
1697 {
1698 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;
1699 complete_data_len = NEC_COMPLETE_DATA_LEN;
1700 }
1701
1702 pulse_1_len = NEC_PULSE_LEN;
1703 pause_1_len = NEC_1_PAUSE_LEN - 1;
1704 pulse_0_len = NEC_PULSE_LEN;
1705 pause_0_len = NEC_0_PAUSE_LEN - 1;
1706 has_stop_bit = NEC_STOP_BIT;
1707 n_auto_repetitions = 1; // 1 frame
1708 auto_repetition_pause_len = 0;
1709 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;
1710 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1711 break;
1712 }
1713 #endif
1714 #if IRSND_SUPPORT_NEC16_PROTOCOL == 1
1715 case IRMP_NEC16_PROTOCOL:
1716 {
1717 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;
1718 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;
1719 pulse_1_len = NEC_PULSE_LEN;
1720 pause_1_len = NEC_1_PAUSE_LEN - 1;
1721 pulse_0_len = NEC_PULSE_LEN;
1722 pause_0_len = NEC_0_PAUSE_LEN - 1;
1723 has_stop_bit = NEC_STOP_BIT;
1724 complete_data_len = NEC16_COMPLETE_DATA_LEN + 1; // 1 more: sync bit
1725 n_auto_repetitions = 1; // 1 frame
1726 auto_repetition_pause_len = 0;
1727 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;
1728 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1729 break;
1730 }
1731 #endif
1732 #if IRSND_SUPPORT_NEC42_PROTOCOL == 1
1733 case IRMP_NEC42_PROTOCOL:
1734 {
1735 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;
1736 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;
1737 pulse_1_len = NEC_PULSE_LEN;
1738 pause_1_len = NEC_1_PAUSE_LEN - 1;
1739 pulse_0_len = NEC_PULSE_LEN;
1740 pause_0_len = NEC_0_PAUSE_LEN - 1;
1741 has_stop_bit = NEC_STOP_BIT;
1742 complete_data_len = NEC42_COMPLETE_DATA_LEN;
1743 n_auto_repetitions = 1; // 1 frame
1744 auto_repetition_pause_len = 0;
1745 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;
1746 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1747 break;
1748 }
1749 #endif
1750 #if IRSND_SUPPORT_LGAIR_PROTOCOL == 1
1751 case IRMP_LGAIR_PROTOCOL:
1752 {
1753 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;
1754 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;
1755 pulse_1_len = NEC_PULSE_LEN;
1756 pause_1_len = NEC_1_PAUSE_LEN - 1;
1757 pulse_0_len = NEC_PULSE_LEN;
1758 pause_0_len = NEC_0_PAUSE_LEN - 1;
1759 has_stop_bit = NEC_STOP_BIT;
1760 complete_data_len = LGAIR_COMPLETE_DATA_LEN;
1761 n_auto_repetitions = 1; // 1 frame
1762 auto_repetition_pause_len = 0;
1763 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;
1764 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1765 break;
1766 }
1767 #endif
1768 #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1
1769 case IRMP_SAMSUNG_PROTOCOL:
1770 {
1771 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;
1772 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;
1773 pulse_1_len = SAMSUNG_PULSE_LEN;
1774 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;
1775 pulse_0_len = SAMSUNG_PULSE_LEN;
1776 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;
1777 has_stop_bit = SAMSUNG_STOP_BIT;
1778 complete_data_len = SAMSUNG_COMPLETE_DATA_LEN;
1779 n_auto_repetitions = 1; // 1 frame
1780 auto_repetition_pause_len = 0;
1781 repeat_frame_pause_len = SAMSUNG_FRAME_REPEAT_PAUSE_LEN;
1782 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1783 break;
1784 }
1785
1786 case IRMP_SAMSUNG32_PROTOCOL:
1787 {
1788 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;
1789 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;
1790 pulse_1_len = SAMSUNG_PULSE_LEN;
1791 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;
1792 pulse_0_len = SAMSUNG_PULSE_LEN;
1793 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;
1794 has_stop_bit = SAMSUNG_STOP_BIT;
1795 complete_data_len = SAMSUNG32_COMPLETE_DATA_LEN;
1796 n_auto_repetitions = SAMSUNG32_FRAMES; // 1 frame
1797 auto_repetition_pause_len = SAMSUNG32_AUTO_REPETITION_PAUSE_LEN; // 47 ms pause
1798 repeat_frame_pause_len = SAMSUNG32_FRAME_REPEAT_PAUSE_LEN;
1799 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1800 break;
1801 }
1802 #endif
1803 #if IRSND_SUPPORT_SAMSUNG48_PROTOCOL == 1
1804 case IRMP_SAMSUNG48_PROTOCOL:
1805 {
1806 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;
1807 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;
1808 pulse_1_len = SAMSUNG_PULSE_LEN;
1809 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;
1810 pulse_0_len = SAMSUNG_PULSE_LEN;
1811 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;
1812 has_stop_bit = SAMSUNG_STOP_BIT;
1813 complete_data_len = SAMSUNG48_COMPLETE_DATA_LEN;
1814 n_auto_repetitions = SAMSUNG48_FRAMES; // 1 frame
1815 auto_repetition_pause_len = SAMSUNG48_AUTO_REPETITION_PAUSE_LEN; // 47 ms pause
1816 repeat_frame_pause_len = SAMSUNG48_FRAME_REPEAT_PAUSE_LEN;
1817 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1818 break;
1819 }
1820 #endif
1821 #if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1
1822 case IRMP_MATSUSHITA_PROTOCOL:
1823 {
1824 startbit_pulse_len = MATSUSHITA_START_BIT_PULSE_LEN;
1825 startbit_pause_len = MATSUSHITA_START_BIT_PAUSE_LEN - 1;
1826 pulse_1_len = MATSUSHITA_PULSE_LEN;
1827 pause_1_len = MATSUSHITA_1_PAUSE_LEN - 1;
1828 pulse_0_len = MATSUSHITA_PULSE_LEN;
1829 pause_0_len = MATSUSHITA_0_PAUSE_LEN - 1;
1830 has_stop_bit = MATSUSHITA_STOP_BIT;
1831 complete_data_len = MATSUSHITA_COMPLETE_DATA_LEN;
1832 n_auto_repetitions = 1; // 1 frame
1833 auto_repetition_pause_len = 0;
1834 repeat_frame_pause_len = MATSUSHITA_FRAME_REPEAT_PAUSE_LEN;
1835 irsnd_set_freq (IRSND_FREQ_36_KHZ);
1836 break;
1837 }
1838 #endif
1839 #if IRSND_SUPPORT_TECHNICS_PROTOCOL == 1
1840 case IRMP_TECHNICS_PROTOCOL:
1841 {
1842 startbit_pulse_len = MATSUSHITA_START_BIT_PULSE_LEN;
1843 startbit_pause_len = MATSUSHITA_START_BIT_PAUSE_LEN - 1;
1844 pulse_1_len = MATSUSHITA_PULSE_LEN;
1845 pause_1_len = MATSUSHITA_1_PAUSE_LEN - 1;
1846 pulse_0_len = MATSUSHITA_PULSE_LEN;
1847 pause_0_len = MATSUSHITA_0_PAUSE_LEN - 1;
1848 has_stop_bit = MATSUSHITA_STOP_BIT;
1849 complete_data_len = TECHNICS_COMPLETE_DATA_LEN; // here TECHNICS
1850 n_auto_repetitions = 1; // 1 frame
1851 auto_repetition_pause_len = 0;
1852 repeat_frame_pause_len = MATSUSHITA_FRAME_REPEAT_PAUSE_LEN;
1853 irsnd_set_freq (IRSND_FREQ_36_KHZ);
1854 break;
1855 }
1856 #endif
1857 #if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1
1858 case IRMP_KASEIKYO_PROTOCOL:
1859 {
1860 startbit_pulse_len = KASEIKYO_START_BIT_PULSE_LEN;
1861 startbit_pause_len = KASEIKYO_START_BIT_PAUSE_LEN - 1;
1862 pulse_1_len = KASEIKYO_PULSE_LEN;
1863 pause_1_len = KASEIKYO_1_PAUSE_LEN - 1;
1864 pulse_0_len = KASEIKYO_PULSE_LEN;
1865 pause_0_len = KASEIKYO_0_PAUSE_LEN - 1;
1866 has_stop_bit = KASEIKYO_STOP_BIT;
1867 complete_data_len = KASEIKYO_COMPLETE_DATA_LEN;
1868 n_auto_repetitions = (repeat_counter == 0) ? KASEIKYO_FRAMES : 1; // 2 frames auto repetition if first frame
1869 auto_repetition_pause_len = KASEIKYO_AUTO_REPETITION_PAUSE_LEN; // 75 ms pause
1870 repeat_frame_pause_len = KASEIKYO_FRAME_REPEAT_PAUSE_LEN;
1871 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1872 break;
1873 }
1874 #endif
1875 #if IRSND_SUPPORT_PANASONIC_PROTOCOL == 1
1876 case IRMP_PANASONIC_PROTOCOL:
1877 {
1878 startbit_pulse_len = PANASONIC_START_BIT_PULSE_LEN;
1879 startbit_pause_len = PANASONIC_START_BIT_PAUSE_LEN - 1;
1880 pulse_1_len = PANASONIC_PULSE_LEN;
1881 pause_1_len = PANASONIC_1_PAUSE_LEN - 1;
1882 pulse_0_len = PANASONIC_PULSE_LEN;
1883 pause_0_len = PANASONIC_0_PAUSE_LEN - 1;
1884 has_stop_bit = PANASONIC_STOP_BIT;
1885 complete_data_len = PANASONIC_COMPLETE_DATA_LEN;
1886 n_auto_repetitions = PANASONIC_FRAMES; // 1 frame
1887 auto_repetition_pause_len = PANASONIC_AUTO_REPETITION_PAUSE_LEN; // 40 ms pause
1888 repeat_frame_pause_len = PANASONIC_FRAME_REPEAT_PAUSE_LEN;
1889 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1890 break;
1891 }
1892 #endif
1893 #if IRSND_SUPPORT_RECS80_PROTOCOL == 1
1894 case IRMP_RECS80_PROTOCOL:
1895 {
1896 startbit_pulse_len = RECS80_START_BIT_PULSE_LEN;
1897 startbit_pause_len = RECS80_START_BIT_PAUSE_LEN - 1;
1898 pulse_1_len = RECS80_PULSE_LEN;
1899 pause_1_len = RECS80_1_PAUSE_LEN - 1;
1900 pulse_0_len = RECS80_PULSE_LEN;
1901 pause_0_len = RECS80_0_PAUSE_LEN - 1;
1902 has_stop_bit = RECS80_STOP_BIT;
1903 complete_data_len = RECS80_COMPLETE_DATA_LEN;
1904 n_auto_repetitions = 1; // 1 frame
1905 auto_repetition_pause_len = 0;
1906 repeat_frame_pause_len = RECS80_FRAME_REPEAT_PAUSE_LEN;
1907 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1908 break;
1909 }
1910 #endif
1911 #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1
1912 case IRMP_RECS80EXT_PROTOCOL:
1913 {
1914 startbit_pulse_len = RECS80EXT_START_BIT_PULSE_LEN;
1915 startbit_pause_len = RECS80EXT_START_BIT_PAUSE_LEN - 1;
1916 pulse_1_len = RECS80EXT_PULSE_LEN;
1917 pause_1_len = RECS80EXT_1_PAUSE_LEN - 1;
1918 pulse_0_len = RECS80EXT_PULSE_LEN;
1919 pause_0_len = RECS80EXT_0_PAUSE_LEN - 1;
1920 has_stop_bit = RECS80EXT_STOP_BIT;
1921 complete_data_len = RECS80EXT_COMPLETE_DATA_LEN;
1922 n_auto_repetitions = 1; // 1 frame
1923 auto_repetition_pause_len = 0;
1924 repeat_frame_pause_len = RECS80EXT_FRAME_REPEAT_PAUSE_LEN;
1925 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1926 break;
1927 }
1928 #endif
1929 #if IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1
1930 case IRMP_TELEFUNKEN_PROTOCOL:
1931 {
1932 startbit_pulse_len = TELEFUNKEN_START_BIT_PULSE_LEN;
1933 startbit_pause_len = TELEFUNKEN_START_BIT_PAUSE_LEN - 1;
1934 pulse_1_len = TELEFUNKEN_PULSE_LEN;
1935 pause_1_len = TELEFUNKEN_1_PAUSE_LEN - 1;
1936 pulse_0_len = TELEFUNKEN_PULSE_LEN;
1937 pause_0_len = TELEFUNKEN_0_PAUSE_LEN - 1;
1938 has_stop_bit = TELEFUNKEN_STOP_BIT;
1939 complete_data_len = TELEFUNKEN_COMPLETE_DATA_LEN;
1940 n_auto_repetitions = 1; // 1 frames
1941 auto_repetition_pause_len = 0; // TELEFUNKEN_AUTO_REPETITION_PAUSE_LEN; // xx ms pause
1942 repeat_frame_pause_len = TELEFUNKEN_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause
1943 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1944 break;
1945 }
1946 #endif
1947 #if IRSND_SUPPORT_RC5_PROTOCOL == 1
1948 case IRMP_RC5_PROTOCOL:
1949 {
1950 startbit_pulse_len = RC5_BIT_LEN;
1951 startbit_pause_len = RC5_BIT_LEN;
1952 pulse_len = RC5_BIT_LEN;
1953 pause_len = RC5_BIT_LEN;
1954 has_stop_bit = RC5_STOP_BIT;
1955 complete_data_len = RC5_COMPLETE_DATA_LEN;
1956 n_auto_repetitions = 1; // 1 frame
1957 auto_repetition_pause_len = 0;
1958 repeat_frame_pause_len = RC5_FRAME_REPEAT_PAUSE_LEN;
1959 irsnd_set_freq (IRSND_FREQ_36_KHZ);
1960 break;
1961 }
1962 #endif
1963 #if IRSND_SUPPORT_RC6_PROTOCOL == 1
1964 case IRMP_RC6_PROTOCOL:
1965 {
1966 startbit_pulse_len = RC6_START_BIT_PULSE_LEN;
1967 startbit_pause_len = RC6_START_BIT_PAUSE_LEN - 1;
1968 pulse_len = RC6_BIT_LEN;
1969 pause_len = RC6_BIT_LEN;
1970 has_stop_bit = RC6_STOP_BIT;
1971 complete_data_len = RC6_COMPLETE_DATA_LEN_SHORT;
1972 n_auto_repetitions = 1; // 1 frame
1973 auto_repetition_pause_len = 0;
1974 repeat_frame_pause_len = RC6_FRAME_REPEAT_PAUSE_LEN;
1975 irsnd_set_freq (IRSND_FREQ_36_KHZ);
1976 break;
1977 }
1978 #endif
1979 #if IRSND_SUPPORT_RC6A_PROTOCOL == 1
1980 case IRMP_RC6A_PROTOCOL:
1981 {
1982 startbit_pulse_len = RC6_START_BIT_PULSE_LEN;
1983 startbit_pause_len = RC6_START_BIT_PAUSE_LEN - 1;
1984 pulse_len = RC6_BIT_LEN;
1985 pause_len = RC6_BIT_LEN;
1986 has_stop_bit = RC6_STOP_BIT;
1987 complete_data_len = RC6_COMPLETE_DATA_LEN_LONG;
1988 n_auto_repetitions = 1; // 1 frame
1989 auto_repetition_pause_len = 0;
1990 repeat_frame_pause_len = RC6_FRAME_REPEAT_PAUSE_LEN;
1991 irsnd_set_freq (IRSND_FREQ_36_KHZ);
1992 break;
1993 }
1994 #endif
1995 #if IRSND_SUPPORT_DENON_PROTOCOL == 1
1996 case IRMP_DENON_PROTOCOL:
1997 {
1998 startbit_pulse_len = 0x00;
1999 startbit_pause_len = 0x00;
2000 pulse_1_len = DENON_PULSE_LEN;
2001 pause_1_len = DENON_1_PAUSE_LEN - 1;
2002 pulse_0_len = DENON_PULSE_LEN;
2003 pause_0_len = DENON_0_PAUSE_LEN - 1;
2004 has_stop_bit = DENON_STOP_BIT;
2005 complete_data_len = DENON_COMPLETE_DATA_LEN;
2006 n_auto_repetitions = DENON_FRAMES; // 2 frames, 2nd with inverted command
2007 auto_repetition_pause_len = DENON_AUTO_REPETITION_PAUSE_LEN; // 65 ms pause after 1st frame
2008 repeat_frame_pause_len = DENON_FRAME_REPEAT_PAUSE_LEN;
2009 irsnd_set_freq (IRSND_FREQ_36_KHZ); // in theory 32kHz, in practice 36kHz is better
2010 break;
2011 }
2012 #endif
2013 #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1
2014 case IRMP_THOMSON_PROTOCOL:
2015 {
2016 startbit_pulse_len = 0x00;
2017 startbit_pause_len = 0x00;
2018 pulse_1_len = THOMSON_PULSE_LEN;
2019 pause_1_len = THOMSON_1_PAUSE_LEN - 1;
2020 pulse_0_len = THOMSON_PULSE_LEN;
2021 pause_0_len = THOMSON_0_PAUSE_LEN - 1;
2022 has_stop_bit = THOMSON_STOP_BIT;
2023 complete_data_len = THOMSON_COMPLETE_DATA_LEN;
2024 n_auto_repetitions = THOMSON_FRAMES; // only 1 frame
2025 auto_repetition_pause_len = THOMSON_AUTO_REPETITION_PAUSE_LEN;
2026 repeat_frame_pause_len = THOMSON_FRAME_REPEAT_PAUSE_LEN;
2027 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2028 break;
2029 }
2030 #endif
2031 #if IRSND_SUPPORT_BOSE_PROTOCOL == 1
2032 case IRMP_BOSE_PROTOCOL:
2033 {
2034 startbit_pulse_len = BOSE_START_BIT_PULSE_LEN;
2035 startbit_pause_len = BOSE_START_BIT_PAUSE_LEN - 1;
2036 pulse_1_len = BOSE_PULSE_LEN;
2037 pause_1_len = BOSE_1_PAUSE_LEN - 1;
2038 pulse_0_len = BOSE_PULSE_LEN;
2039 pause_0_len = BOSE_0_PAUSE_LEN - 1;
2040 has_stop_bit = BOSE_STOP_BIT;
2041 complete_data_len = BOSE_COMPLETE_DATA_LEN;
2042 n_auto_repetitions = BOSE_FRAMES; // 1 frame
2043 auto_repetition_pause_len = BOSE_AUTO_REPETITION_PAUSE_LEN; // 40 ms pause
2044 repeat_frame_pause_len = BOSE_FRAME_REPEAT_PAUSE_LEN;
2045 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2046 break;
2047 }
2048 #endif
2049 #if IRSND_SUPPORT_NUBERT_PROTOCOL == 1
2050 case IRMP_NUBERT_PROTOCOL:
2051 {
2052 startbit_pulse_len = NUBERT_START_BIT_PULSE_LEN;
2053 startbit_pause_len = NUBERT_START_BIT_PAUSE_LEN - 1;
2054 pulse_1_len = NUBERT_1_PULSE_LEN;
2055 pause_1_len = NUBERT_1_PAUSE_LEN - 1;
2056 pulse_0_len = NUBERT_0_PULSE_LEN;
2057 pause_0_len = NUBERT_0_PAUSE_LEN - 1;
2058 has_stop_bit = NUBERT_STOP_BIT;
2059 complete_data_len = NUBERT_COMPLETE_DATA_LEN;
2060 n_auto_repetitions = NUBERT_FRAMES; // 2 frames
2061 auto_repetition_pause_len = NUBERT_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause
2062 repeat_frame_pause_len = NUBERT_FRAME_REPEAT_PAUSE_LEN;
2063 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2064 break;
2065 }
2066 #endif
2067 #if IRSND_SUPPORT_FAN_PROTOCOL == 1
2068 case IRMP_FAN_PROTOCOL:
2069 {
2070 startbit_pulse_len = FAN_START_BIT_PULSE_LEN;
2071 startbit_pause_len = FAN_START_BIT_PAUSE_LEN - 1;
2072 pulse_1_len = FAN_1_PULSE_LEN;
2073 pause_1_len = FAN_1_PAUSE_LEN - 1;
2074 pulse_0_len = FAN_0_PULSE_LEN;
2075 pause_0_len = FAN_0_PAUSE_LEN - 1;
2076 has_stop_bit = FAN_STOP_BIT;
2077 complete_data_len = FAN_COMPLETE_DATA_LEN;
2078 n_auto_repetitions = FAN_FRAMES; // only 1 frame
2079 auto_repetition_pause_len = FAN_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause
2080 repeat_frame_pause_len = FAN_FRAME_REPEAT_PAUSE_LEN;
2081 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2082 break;
2083 }
2084 #endif
2085 #if IRSND_SUPPORT_SPEAKER_PROTOCOL == 1
2086 case IRMP_SPEAKER_PROTOCOL:
2087 {
2088 startbit_pulse_len = SPEAKER_START_BIT_PULSE_LEN;
2089 startbit_pause_len = SPEAKER_START_BIT_PAUSE_LEN - 1;
2090 pulse_1_len = SPEAKER_1_PULSE_LEN;
2091 pause_1_len = SPEAKER_1_PAUSE_LEN - 1;
2092 pulse_0_len = SPEAKER_0_PULSE_LEN;
2093 pause_0_len = SPEAKER_0_PAUSE_LEN - 1;
2094 has_stop_bit = SPEAKER_STOP_BIT;
2095 complete_data_len = SPEAKER_COMPLETE_DATA_LEN;
2096 n_auto_repetitions = SPEAKER_FRAMES; // 2 frames
2097 auto_repetition_pause_len = SPEAKER_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause
2098 repeat_frame_pause_len = SPEAKER_FRAME_REPEAT_PAUSE_LEN;
2099 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2100 break;
2101 }
2102 #endif
2103 #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1
2104 case IRMP_BANG_OLUFSEN_PROTOCOL:
2105 {
2106 startbit_pulse_len = BANG_OLUFSEN_START_BIT1_PULSE_LEN;
2107 startbit_pause_len = BANG_OLUFSEN_START_BIT1_PAUSE_LEN - 1;
2108 pulse_1_len = BANG_OLUFSEN_PULSE_LEN;
2109 pause_1_len = BANG_OLUFSEN_1_PAUSE_LEN - 1;
2110 pulse_0_len = BANG_OLUFSEN_PULSE_LEN;
2111 pause_0_len = BANG_OLUFSEN_0_PAUSE_LEN - 1;
2112 has_stop_bit = BANG_OLUFSEN_STOP_BIT;
2113 complete_data_len = BANG_OLUFSEN_COMPLETE_DATA_LEN;
2114 n_auto_repetitions = 1; // 1 frame
2115 auto_repetition_pause_len = 0;
2116 repeat_frame_pause_len = BANG_OLUFSEN_FRAME_REPEAT_PAUSE_LEN;
2117 last_bit_value = 0;
2118 irsnd_set_freq (IRSND_FREQ_455_KHZ);
2119 break;
2120 }
2121 #endif
2122 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1
2123 case IRMP_GRUNDIG_PROTOCOL:
2124 {
2125 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2126 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;
2127 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2128 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2129 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;
2130 complete_data_len = GRUNDIG_COMPLETE_DATA_LEN;
2131 n_auto_repetitions = GRUNDIG_FRAMES; // 2 frames
2132 auto_repetition_pause_len = GRUNDIG_AUTO_REPETITION_PAUSE_LEN; // 20m sec pause
2133 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause
2134 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2135 break;
2136 }
2137 #endif
2138 #if IRSND_SUPPORT_IR60_PROTOCOL == 1
2139 case IRMP_IR60_PROTOCOL:
2140 {
2141 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2142 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;
2143 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2144 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2145 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;
2146 complete_data_len = IR60_COMPLETE_DATA_LEN;
2147 n_auto_repetitions = IR60_FRAMES; // 2 frames
2148 auto_repetition_pause_len = IR60_AUTO_REPETITION_PAUSE_LEN; // 20m sec pause
2149 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause
2150 irsnd_set_freq (IRSND_FREQ_30_KHZ);
2151 break;
2152 }
2153 #endif
2154 #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1
2155 case IRMP_NOKIA_PROTOCOL:
2156 {
2157 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2158 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;
2159 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2160 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2161 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;
2162 complete_data_len = NOKIA_COMPLETE_DATA_LEN;
2163 n_auto_repetitions = NOKIA_FRAMES; // 2 frames
2164 auto_repetition_pause_len = NOKIA_AUTO_REPETITION_PAUSE_LEN; // 20 msec pause
2165 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause
2166 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2167 break;
2168 }
2169 #endif
2170 #if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1
2171 case IRMP_SIEMENS_PROTOCOL:
2172 {
2173 startbit_pulse_len = SIEMENS_BIT_LEN;
2174 startbit_pause_len = SIEMENS_BIT_LEN;
2175 pulse_len = SIEMENS_BIT_LEN;
2176 pause_len = SIEMENS_BIT_LEN;
2177 has_stop_bit = SIEMENS_OR_RUWIDO_STOP_BIT;
2178 complete_data_len = SIEMENS_COMPLETE_DATA_LEN;
2179 n_auto_repetitions = 1; // 1 frame
2180 auto_repetition_pause_len = 0;
2181 repeat_frame_pause_len = SIEMENS_FRAME_REPEAT_PAUSE_LEN;
2182 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2183 break;
2184 }
2185 #endif
2186 #if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1
2187 case IRMP_RUWIDO_PROTOCOL:
2188 {
2189 startbit_pulse_len = RUWIDO_START_BIT_PULSE_LEN;
2190 startbit_pause_len = RUWIDO_START_BIT_PAUSE_LEN;
2191 pulse_len = RUWIDO_BIT_PULSE_LEN;
2192 pause_len = RUWIDO_BIT_PAUSE_LEN;
2193 has_stop_bit = SIEMENS_OR_RUWIDO_STOP_BIT;
2194 complete_data_len = RUWIDO_COMPLETE_DATA_LEN;
2195 n_auto_repetitions = 1; // 1 frame
2196 auto_repetition_pause_len = 0;
2197 repeat_frame_pause_len = RUWIDO_FRAME_REPEAT_PAUSE_LEN;
2198 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2199 break;
2200 }
2201 #endif
2202 #if IRSND_SUPPORT_FDC_PROTOCOL == 1
2203 case IRMP_FDC_PROTOCOL:
2204 {
2205 startbit_pulse_len = FDC_START_BIT_PULSE_LEN;
2206 startbit_pause_len = FDC_START_BIT_PAUSE_LEN - 1;
2207 complete_data_len = FDC_COMPLETE_DATA_LEN;
2208 pulse_1_len = FDC_PULSE_LEN;
2209 pause_1_len = FDC_1_PAUSE_LEN - 1;
2210 pulse_0_len = FDC_PULSE_LEN;
2211 pause_0_len = FDC_0_PAUSE_LEN - 1;
2212 has_stop_bit = FDC_STOP_BIT;
2213 n_auto_repetitions = 1; // 1 frame
2214 auto_repetition_pause_len = 0;
2215 repeat_frame_pause_len = FDC_FRAME_REPEAT_PAUSE_LEN;
2216 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2217 break;
2218 }
2219 #endif
2220 #if IRSND_SUPPORT_RCCAR_PROTOCOL == 1
2221 case IRMP_RCCAR_PROTOCOL:
2222 {
2223 startbit_pulse_len = RCCAR_START_BIT_PULSE_LEN;
2224 startbit_pause_len = RCCAR_START_BIT_PAUSE_LEN - 1;
2225 complete_data_len = RCCAR_COMPLETE_DATA_LEN;
2226 pulse_1_len = RCCAR_PULSE_LEN;
2227 pause_1_len = RCCAR_1_PAUSE_LEN - 1;
2228 pulse_0_len = RCCAR_PULSE_LEN;
2229 pause_0_len = RCCAR_0_PAUSE_LEN - 1;
2230 has_stop_bit = RCCAR_STOP_BIT;
2231 n_auto_repetitions = 1; // 1 frame
2232 auto_repetition_pause_len = 0;
2233 repeat_frame_pause_len = RCCAR_FRAME_REPEAT_PAUSE_LEN;
2234 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2235 break;
2236 }
2237 #endif
2238 #if IRSND_SUPPORT_JVC_PROTOCOL == 1
2239 case IRMP_JVC_PROTOCOL:
2240 {
2241 if (repeat_counter != 0) // skip start bit if repetition frame
2242 {
2243 current_bit = 0;
2244 }
2245
2246 startbit_pulse_len = JVC_START_BIT_PULSE_LEN;
2247 startbit_pause_len = JVC_START_BIT_PAUSE_LEN - 1;
2248 complete_data_len = JVC_COMPLETE_DATA_LEN;
2249 pulse_1_len = JVC_PULSE_LEN;
2250 pause_1_len = JVC_1_PAUSE_LEN - 1;
2251 pulse_0_len = JVC_PULSE_LEN;
2252 pause_0_len = JVC_0_PAUSE_LEN - 1;
2253 has_stop_bit = JVC_STOP_BIT;
2254 n_auto_repetitions = 1; // 1 frame
2255 auto_repetition_pause_len = 0;
2256 repeat_frame_pause_len = JVC_FRAME_REPEAT_PAUSE_LEN;
2257 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2258 break;
2259 }
2260 #endif
2261 #if IRSND_SUPPORT_NIKON_PROTOCOL == 1
2262 case IRMP_NIKON_PROTOCOL:
2263 {
2264 startbit_pulse_len = NIKON_START_BIT_PULSE_LEN;
2265 startbit_pause_len = NIKON_START_BIT_PAUSE_LEN;
2266 complete_data_len = NIKON_COMPLETE_DATA_LEN;
2267 pulse_1_len = NIKON_PULSE_LEN;
2268 pause_1_len = NIKON_1_PAUSE_LEN - 1;
2269 pulse_0_len = NIKON_PULSE_LEN;
2270 pause_0_len = NIKON_0_PAUSE_LEN - 1;
2271 has_stop_bit = NIKON_STOP_BIT;
2272 n_auto_repetitions = 1; // 1 frame
2273 auto_repetition_pause_len = 0;
2274 repeat_frame_pause_len = NIKON_FRAME_REPEAT_PAUSE_LEN;
2275 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2276 break;
2277 }
2278 #endif
2279 #if IRSND_SUPPORT_LEGO_PROTOCOL == 1
2280 case IRMP_LEGO_PROTOCOL:
2281 {
2282 startbit_pulse_len = LEGO_START_BIT_PULSE_LEN;
2283 startbit_pause_len = LEGO_START_BIT_PAUSE_LEN - 1;
2284 complete_data_len = LEGO_COMPLETE_DATA_LEN;
2285 pulse_1_len = LEGO_PULSE_LEN;
2286 pause_1_len = LEGO_1_PAUSE_LEN - 1;
2287 pulse_0_len = LEGO_PULSE_LEN;
2288 pause_0_len = LEGO_0_PAUSE_LEN - 1;
2289 has_stop_bit = LEGO_STOP_BIT;
2290 n_auto_repetitions = 1; // 1 frame
2291 auto_repetition_pause_len = 0;
2292 repeat_frame_pause_len = LEGO_FRAME_REPEAT_PAUSE_LEN;
2293 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2294 break;
2295 }
2296 #endif
2297 #if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1
2298 case IRMP_A1TVBOX_PROTOCOL:
2299 {
2300 startbit_pulse_len = A1TVBOX_BIT_PULSE_LEN; // don't use A1TVBOX_START_BIT_PULSE_LEN
2301 startbit_pause_len = A1TVBOX_BIT_PAUSE_LEN; // don't use A1TVBOX_START_BIT_PAUSE_LEN
2302 pulse_len = A1TVBOX_BIT_PULSE_LEN;
2303 pause_len = A1TVBOX_BIT_PAUSE_LEN;
2304 has_stop_bit = A1TVBOX_STOP_BIT;
2305 complete_data_len = A1TVBOX_COMPLETE_DATA_LEN + 1; // we send stop bit as data
2306 n_auto_repetitions = 1; // 1 frame
2307 auto_repetition_pause_len = 0;
2308 repeat_frame_pause_len = A1TVBOX_FRAME_REPEAT_PAUSE_LEN;
2309 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2310 break;
2311 }
2312 #endif
2313 #if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1
2314 case IRMP_ROOMBA_PROTOCOL:
2315 {
2316 startbit_pulse_len = ROOMBA_START_BIT_PULSE_LEN;
2317 startbit_pause_len = ROOMBA_START_BIT_PAUSE_LEN;
2318 pulse_1_len = ROOMBA_1_PULSE_LEN;
2319 pause_1_len = ROOMBA_1_PAUSE_LEN - 1;
2320 pulse_0_len = ROOMBA_0_PULSE_LEN;
2321 pause_0_len = ROOMBA_0_PAUSE_LEN - 1;
2322 has_stop_bit = ROOMBA_STOP_BIT;
2323 complete_data_len = ROOMBA_COMPLETE_DATA_LEN;
2324 n_auto_repetitions = ROOMBA_FRAMES; // 8 frames
2325 auto_repetition_pause_len = ROOMBA_FRAME_REPEAT_PAUSE_LEN;
2326 repeat_frame_pause_len = ROOMBA_FRAME_REPEAT_PAUSE_LEN;
2327 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2328 break;
2329 }
2330 #endif
2331 #if IRSND_SUPPORT_PENTAX_PROTOCOL == 1
2332 case IRMP_PENTAX_PROTOCOL:
2333 {
2334 startbit_pulse_len = PENTAX_START_BIT_PULSE_LEN;
2335 startbit_pause_len = PENTAX_START_BIT_PAUSE_LEN;
2336 complete_data_len = PENTAX_COMPLETE_DATA_LEN;
2337 pulse_1_len = PENTAX_PULSE_LEN;
2338 pause_1_len = PENTAX_1_PAUSE_LEN - 1;
2339 pulse_0_len = PENTAX_PULSE_LEN;
2340 pause_0_len = PENTAX_0_PAUSE_LEN - 1;
2341 has_stop_bit = PENTAX_STOP_BIT;
2342 n_auto_repetitions = 1; // 1 frame
2343 auto_repetition_pause_len = 0;
2344 repeat_frame_pause_len = PENTAX_FRAME_REPEAT_PAUSE_LEN;
2345 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2346 break;
2347 }
2348 #endif
2349 #if IRSND_SUPPORT_ACP24_PROTOCOL == 1
2350 case IRMP_ACP24_PROTOCOL:
2351 {
2352 startbit_pulse_len = ACP24_START_BIT_PULSE_LEN;
2353 startbit_pause_len = ACP24_START_BIT_PAUSE_LEN - 1;
2354 complete_data_len = ACP24_COMPLETE_DATA_LEN;
2355 pulse_1_len = ACP24_PULSE_LEN;
2356 pause_1_len = ACP24_1_PAUSE_LEN - 1;
2357 pulse_0_len = ACP24_PULSE_LEN;
2358 pause_0_len = ACP24_0_PAUSE_LEN - 1;
2359 has_stop_bit = ACP24_STOP_BIT;
2360 n_auto_repetitions = 1; // 1 frame
2361 auto_repetition_pause_len = 0;
2362 repeat_frame_pause_len = ACP24_FRAME_REPEAT_PAUSE_LEN;
2363 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2364 break;
2365 }
2366 #endif
2367 default:
2368 {
2369 irsnd_busy = FALSE;
2370 break;
2371 }
2372 }
2373 }
2374 }
2375
2376 if (irsnd_busy)
2377 {
2378 new_frame = FALSE;
2379
2380 switch (irsnd_protocol)
2381 {
2382 #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1
2383 case IRMP_SIRCS_PROTOCOL:
2384 #endif
2385 #if IRSND_SUPPORT_NEC_PROTOCOL == 1
2386 case IRMP_NEC_PROTOCOL:
2387 #endif
2388 #if IRSND_SUPPORT_NEC16_PROTOCOL == 1
2389 case IRMP_NEC16_PROTOCOL:
2390 #endif
2391 #if IRSND_SUPPORT_NEC42_PROTOCOL == 1
2392 case IRMP_NEC42_PROTOCOL:
2393 #endif
2394 #if IRSND_SUPPORT_LGAIR_PROTOCOL == 1
2395 case IRMP_LGAIR_PROTOCOL:
2396 #endif
2397 #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1
2398 case IRMP_SAMSUNG_PROTOCOL:
2399 case IRMP_SAMSUNG32_PROTOCOL:
2400 #endif
2401 #if IRSND_SUPPORT_SAMSUNG48_PROTOCOL == 1
2402 case IRMP_SAMSUNG48_PROTOCOL:
2403 #endif
2404 #if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1
2405 case IRMP_MATSUSHITA_PROTOCOL:
2406 #endif
2407 #if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1
2408 case IRMP_TECHNICS_PROTOCOL:
2409 #endif
2410 #if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1
2411 case IRMP_KASEIKYO_PROTOCOL:
2412 #endif
2413 #if IRSND_SUPPORT_PANASONIC_PROTOCOL == 1
2414 case IRMP_PANASONIC_PROTOCOL:
2415 #endif
2416 #if IRSND_SUPPORT_RECS80_PROTOCOL == 1
2417 case IRMP_RECS80_PROTOCOL:
2418 #endif
2419 #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1
2420 case IRMP_RECS80EXT_PROTOCOL:
2421 #endif
2422 #if IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1
2423 case IRMP_TELEFUNKEN_PROTOCOL:
2424 #endif
2425 #if IRSND_SUPPORT_DENON_PROTOCOL == 1
2426 case IRMP_DENON_PROTOCOL:
2427 #endif
2428 #if IRSND_SUPPORT_BOSE_PROTOCOL == 1
2429 case IRMP_BOSE_PROTOCOL:
2430 #endif
2431 #if IRSND_SUPPORT_NUBERT_PROTOCOL == 1
2432 case IRMP_NUBERT_PROTOCOL:
2433 #endif
2434 #if IRSND_SUPPORT_FAN_PROTOCOL == 1
2435 case IRMP_FAN_PROTOCOL:
2436 #endif
2437 #if IRSND_SUPPORT_SPEAKER_PROTOCOL == 1
2438 case IRMP_SPEAKER_PROTOCOL:
2439 #endif
2440 #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1
2441 case IRMP_BANG_OLUFSEN_PROTOCOL:
2442 #endif
2443 #if IRSND_SUPPORT_FDC_PROTOCOL == 1
2444 case IRMP_FDC_PROTOCOL:
2445 #endif
2446 #if IRSND_SUPPORT_RCCAR_PROTOCOL == 1
2447 case IRMP_RCCAR_PROTOCOL:
2448 #endif
2449 #if IRSND_SUPPORT_JVC_PROTOCOL == 1
2450 case IRMP_JVC_PROTOCOL:
2451 #endif
2452 #if IRSND_SUPPORT_NIKON_PROTOCOL == 1
2453 case IRMP_NIKON_PROTOCOL:
2454 #endif
2455 #if IRSND_SUPPORT_LEGO_PROTOCOL == 1
2456 case IRMP_LEGO_PROTOCOL:
2457 #endif
2458 #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1
2459 case IRMP_THOMSON_PROTOCOL:
2460 #endif
2461 #if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1
2462 case IRMP_ROOMBA_PROTOCOL:
2463 #endif
2464 #if IRSND_SUPPORT_PENTAX_PROTOCOL == 1
2465 case IRMP_PENTAX_PROTOCOL:
2466 #endif
2467 #if IRSND_SUPPORT_ACP24_PROTOCOL == 1
2468 case IRMP_ACP24_PROTOCOL:
2469 #endif
2470
2471 #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1 || IRSND_SUPPORT_NEC_PROTOCOL == 1 || IRSND_SUPPORT_NEC16_PROTOCOL == 1 || IRSND_SUPPORT_NEC42_PROTOCOL == 1 || \
2472 IRSND_SUPPORT_LGAIR_PROTOCOL == 1 || IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1 || IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1 || IRSND_SUPPORT_TECHNICS_PROTOCOL == 1 || \
2473 IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1 || IRSND_SUPPORT_RECS80_PROTOCOL == 1 || IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1 || IRSND_SUPPORT_DENON_PROTOCOL == 1 || \
2474 IRSND_SUPPORT_NUBERT_PROTOCOL == 1 || IRSND_SUPPORT_FAN_PROTOCOL == 1 || IRSND_SUPPORT_SPEAKER_PROTOCOL == 1 || IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1 || \
2475 IRSND_SUPPORT_FDC_PROTOCOL == 1 || IRSND_SUPPORT_RCCAR_PROTOCOL == 1 || IRSND_SUPPORT_JVC_PROTOCOL == 1 || IRSND_SUPPORT_NIKON_PROTOCOL == 1 || \
2476 IRSND_SUPPORT_LEGO_PROTOCOL == 1 || IRSND_SUPPORT_THOMSON_PROTOCOL == 1 || IRSND_SUPPORT_ROOMBA_PROTOCOL == 1 || IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1 || \
2477 IRSND_SUPPORT_PENTAX_PROTOCOL == 1 || IRSND_SUPPORT_ACP24_PROTOCOL == 1 || IRSND_SUPPORT_PANASONIC_PROTOCOL == 1
2478 {
2479 if (pulse_counter == 0)
2480 {
2481 if (current_bit == 0xFF) // send start bit
2482 {
2483 pulse_len = startbit_pulse_len;
2484 pause_len = startbit_pause_len;
2485 }
2486 else if (current_bit < complete_data_len) // send n'th bit
2487 {
2488 #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1
2489 if (irsnd_protocol == IRMP_SAMSUNG_PROTOCOL)
2490 {
2491 if (current_bit < SAMSUNG_ADDRESS_LEN) // send address bits
2492 {
2493 pulse_len = SAMSUNG_PULSE_LEN;
2494 pause_len = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ?
2495 (SAMSUNG_1_PAUSE_LEN - 1) : (SAMSUNG_0_PAUSE_LEN - 1);
2496 }
2497 else if (current_bit == SAMSUNG_ADDRESS_LEN) // send SYNC bit (16th bit)
2498 {
2499 pulse_len = SAMSUNG_PULSE_LEN;
2500 pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;
2501 }
2502 else if (current_bit < SAMSUNG_COMPLETE_DATA_LEN) // send n'th bit
2503 {
2504 uint8_t cur_bit = current_bit - 1; // sync skipped, offset = -1 !
2505
2506 pulse_len = SAMSUNG_PULSE_LEN;
2507 pause_len = (irsnd_buffer[cur_bit >> 3] & (1<<(7-(cur_bit & 7)))) ?
2508 (SAMSUNG_1_PAUSE_LEN - 1) : (SAMSUNG_0_PAUSE_LEN - 1);
2509 }
2510 }
2511 else
2512 #endif
2513
2514 #if IRSND_SUPPORT_NEC16_PROTOCOL == 1
2515 if (irsnd_protocol == IRMP_NEC16_PROTOCOL)
2516 {
2517 if (current_bit < NEC16_ADDRESS_LEN) // send address bits
2518 {
2519 pulse_len = NEC_PULSE_LEN;
2520 pause_len = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ?
2521 (NEC_1_PAUSE_LEN - 1) : (NEC_0_PAUSE_LEN - 1);
2522 }
2523 else if (current_bit == NEC16_ADDRESS_LEN) // send SYNC bit (8th bit)
2524 {
2525 pulse_len = NEC_PULSE_LEN;
2526 pause_len = NEC_START_BIT_PAUSE_LEN - 1;
2527 }
2528 else if (current_bit < NEC16_COMPLETE_DATA_LEN + 1) // send n'th bit
2529 {
2530 uint8_t cur_bit = current_bit - 1; // sync skipped, offset = -1 !
2531
2532 pulse_len = NEC_PULSE_LEN;
2533 pause_len = (irsnd_buffer[cur_bit >> 3] & (1<<(7-(cur_bit & 7)))) ?
2534 (NEC_1_PAUSE_LEN - 1) : (NEC_0_PAUSE_LEN - 1);
2535 }
2536 }
2537 else
2538 #endif
2539
2540 #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1
2541 if (irsnd_protocol == IRMP_BANG_OLUFSEN_PROTOCOL)
2542 {
2543 if (current_bit == 0) // send 2nd start bit
2544 {
2545 pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;
2546 pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN - 1;
2547 }
2548 else if (current_bit == 1) // send 3rd start bit
2549 {
2550 pulse_len = BANG_OLUFSEN_START_BIT3_PULSE_LEN;
2551 pause_len = BANG_OLUFSEN_START_BIT3_PAUSE_LEN - 1;
2552 }
2553 else if (current_bit == 2) // send 4th start bit
2554 {
2555 pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;
2556 pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN - 1;
2557 }
2558 else if (current_bit == 19) // send trailer bit
2559 {
2560 pulse_len = BANG_OLUFSEN_PULSE_LEN;
2561 pause_len = BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN - 1;
2562 }
2563 else if (current_bit < BANG_OLUFSEN_COMPLETE_DATA_LEN) // send n'th bit
2564 {
2565 uint8_t cur_bit_value = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ? 1 : 0;
2566 pulse_len = BANG_OLUFSEN_PULSE_LEN;
2567
2568 if (cur_bit_value == last_bit_value)
2569 {
2570 pause_len = BANG_OLUFSEN_R_PAUSE_LEN - 1;
2571 }
2572 else
2573 {
2574 pause_len = cur_bit_value ? (BANG_OLUFSEN_1_PAUSE_LEN - 1) : (BANG_OLUFSEN_0_PAUSE_LEN - 1);
2575 last_bit_value = cur_bit_value;
2576 }
2577 }
2578 }
2579 else
2580 #endif
2581 if (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7))))
2582 {
2583 pulse_len = pulse_1_len;
2584 pause_len = pause_1_len;
2585 }
2586 else
2587 {
2588 pulse_len = pulse_0_len;
2589 pause_len = pause_0_len;
2590 }
2591 }
2592 else if (has_stop_bit) // send stop bit
2593 {
2594 pulse_len = pulse_0_len;
2595
2596 if (auto_repetition_counter < n_auto_repetitions)
2597 {
2598 pause_len = pause_0_len;
2599 }
2600 else
2601 {
2602 pause_len = 255; // last frame: pause of 255
2603 }
2604 }
2605 }
2606
2607 if (pulse_counter < pulse_len)
2608 {
2609 if (pulse_counter == 0)
2610 {
2611 irsnd_on ();
2612 }
2613 pulse_counter++;
2614 }
2615 else if (pause_counter < pause_len)
2616 {
2617 if (pause_counter == 0)
2618 {
2619 irsnd_off ();
2620 }
2621 pause_counter++;
2622 }
2623 else
2624 {
2625 current_bit++;
2626
2627 if (current_bit >= complete_data_len + has_stop_bit)
2628 {
2629 current_bit = 0xFF;
2630 auto_repetition_counter++;
2631
2632 if (auto_repetition_counter == n_auto_repetitions)
2633 {
2634 irsnd_busy = FALSE;
2635 auto_repetition_counter = 0;
2636 }
2637 new_frame = TRUE;
2638 }
2639
2640 pulse_counter = 0;
2641 pause_counter = 0;
2642 }
2643 break;
2644 }
2645 #endif
2646
2647 #if IRSND_SUPPORT_RC5_PROTOCOL == 1
2648 case IRMP_RC5_PROTOCOL:
2649 #endif
2650 #if IRSND_SUPPORT_RC6_PROTOCOL == 1
2651 case IRMP_RC6_PROTOCOL:
2652 #endif
2653 #if IRSND_SUPPORT_RC6A_PROTOCOL == 1
2654 case IRMP_RC6A_PROTOCOL:
2655 #endif
2656 #if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1
2657 case IRMP_SIEMENS_PROTOCOL:
2658 #endif
2659 #if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1
2660 case IRMP_RUWIDO_PROTOCOL:
2661 #endif
2662 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1
2663 case IRMP_GRUNDIG_PROTOCOL:
2664 #endif
2665 #if IRSND_SUPPORT_IR60_PROTOCOL == 1
2666 case IRMP_IR60_PROTOCOL:
2667 #endif
2668 #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1
2669 case IRMP_NOKIA_PROTOCOL:
2670 #endif
2671 #if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1
2672 case IRMP_A1TVBOX_PROTOCOL:
2673 #endif
2674
2675 #if IRSND_SUPPORT_RC5_PROTOCOL == 1 || \
2676 IRSND_SUPPORT_RC6_PROTOCOL == 1 || \
2677 IRSND_SUPPORT_RC6A_PROTOCOL == 1 || \
2678 IRSND_SUPPORT_RUWIDO_PROTOCOL == 1 || \
2679 IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 || \
2680 IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || \
2681 IRSND_SUPPORT_IR60_PROTOCOL == 1 || \
2682 IRSND_SUPPORT_NOKIA_PROTOCOL == 1 || \
2683 IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1
2684 {
2685 if (pulse_counter == pulse_len && pause_counter == pause_len)
2686 {
2687 current_bit++;
2688
2689 if (current_bit >= complete_data_len)
2690 {
2691 current_bit = 0xFF;
2692
2693 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1
2694 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL || irsnd_protocol == IRMP_IR60_PROTOCOL || irsnd_protocol == IRMP_NOKIA_PROTOCOL)
2695 {
2696 auto_repetition_counter++;
2697
2698 if (repeat_counter > 0)
2699 { // set 117 msec pause time
2700 auto_repetition_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN;
2701 }
2702
2703 if (repeat_counter < n_repeat_frames) // tricky: repeat n info frames per auto repetition before sending last stop frame
2704 {
2705 n_auto_repetitions++; // increment number of auto repetitions
2706 repeat_counter++;
2707 }
2708 else if (auto_repetition_counter == n_auto_repetitions)
2709 {
2710 irsnd_busy = FALSE;
2711 auto_repetition_counter = 0;
2712 }
2713 }
2714 else
2715 #endif
2716 {
2717 irsnd_busy = FALSE;
2718 }
2719
2720 new_frame = TRUE;
2721 irsnd_off ();
2722 }
2723
2724 pulse_counter = 0;
2725 pause_counter = 0;
2726 }
2727
2728 if (! new_frame)
2729 {
2730 uint8_t first_pulse;
2731
2732 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1
2733 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL || irsnd_protocol == IRMP_IR60_PROTOCOL || irsnd_protocol == IRMP_NOKIA_PROTOCOL)
2734 {
2735 if (current_bit == 0xFF || // start bit of start-frame
2736 (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL && current_bit == 15) || // start bit of info-frame (Grundig)
2737 (irsnd_protocol == IRMP_IR60_PROTOCOL && current_bit == 7) || // start bit of data frame (IR60)
2738 (irsnd_protocol == IRMP_NOKIA_PROTOCOL && (current_bit == 23 || current_bit == 47))) // start bit of info- or stop-frame (Nokia)
2739 {
2740 pulse_len = startbit_pulse_len;
2741 pause_len = startbit_pause_len;
2742 first_pulse = TRUE;
2743 }
2744 else // send n'th bit
2745 {
2746 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2747 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2748 first_pulse = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ? TRUE : FALSE;
2749 }
2750 }
2751 else // if (irsnd_protocol == IRMP_RC5_PROTOCOL || irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL ||
2752 // irsnd_protocol == IRMP_SIEMENS_PROTOCOL || irsnd_protocol == IRMP_RUWIDO_PROTOCOL)
2753 #endif
2754 {
2755 if (current_bit == 0xFF) // 1 start bit
2756 {
2757 #if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1
2758 if (irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL)
2759 {
2760 pulse_len = startbit_pulse_len;
2761 pause_len = startbit_pause_len;
2762 }
2763 else
2764 #endif
2765 #if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1
2766 if (irsnd_protocol == IRMP_A1TVBOX_PROTOCOL)
2767 {
2768 current_bit = 0;
2769 }
2770 else
2771 #endif
2772 {
2773 ;
2774 }
2775
2776 first_pulse = TRUE;
2777 }
2778 else // send n'th bit
2779 {
2780 #if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1
2781 if (irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL)
2782 {
2783 pulse_len = RC6_BIT_LEN;
2784 pause_len = RC6_BIT_LEN;
2785
2786 if (irsnd_protocol == IRMP_RC6_PROTOCOL)
2787 {
2788 if (current_bit == 4) // toggle bit (double len)
2789 {
2790 pulse_len = RC6_BIT_2_LEN; // = 2 * RC_BIT_LEN
2791 pause_len = RC6_BIT_2_LEN; // = 2 * RC_BIT_LEN
2792 }
2793 }
2794 else // if (irsnd_protocol == IRMP_RC6A_PROTOCOL)
2795 {
2796 if (current_bit == 4) // toggle bit (double len)
2797 {
2798 pulse_len = RC6_BIT_3_LEN; // = 3 * RC6_BIT_LEN
2799 pause_len = RC6_BIT_2_LEN; // = 2 * RC6_BIT_LEN
2800 }
2801 else if (current_bit == 5) // toggle bit (double len)
2802 {
2803 pause_len = RC6_BIT_2_LEN; // = 2 * RC6_BIT_LEN
2804 }
2805 }
2806 }
2807 #endif
2808 first_pulse = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ? TRUE : FALSE;
2809 }
2810
2811 if (irsnd_protocol == IRMP_RC5_PROTOCOL)
2812 {
2813 first_pulse = first_pulse ? FALSE : TRUE;
2814 }
2815 }
2816
2817 if (first_pulse)
2818 {
2819 // printf ("first_pulse: current_bit: %d %d < %d %d < %d\n", current_bit, pause_counter, pause_len, pulse_counter, pulse_len);
2820
2821 if (pulse_counter < pulse_len)
2822 {
2823 if (pulse_counter == 0)
2824 {
2825 irsnd_on ();
2826 }
2827 pulse_counter++;
2828 }
2829 else // if (pause_counter < pause_len)
2830 {
2831 if (pause_counter == 0)
2832 {
2833 irsnd_off ();
2834 }
2835 pause_counter++;
2836 }
2837 }
2838 else
2839 {
2840 // printf ("first_pause: current_bit: %d %d < %d %d < %d\n", current_bit, pause_counter, pause_len, pulse_counter, pulse_len);
2841
2842 if (pause_counter < pause_len)
2843 {
2844 if (pause_counter == 0)
2845 {
2846 irsnd_off ();
2847 }
2848 pause_counter++;
2849 }
2850 else // if (pulse_counter < pulse_len)
2851 {
2852 if (pulse_counter == 0)
2853 {
2854 irsnd_on ();
2855 }
2856 pulse_counter++;
2857 }
2858 }
2859 }
2860 break;
2861 }
2862 #endif // IRSND_SUPPORT_RC5_PROTOCOL == 1 || IRSND_SUPPORT_RC6_PROTOCOL == 1 || || IRSND_SUPPORT_RC6A_PROTOCOL == 1 || IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 ||
2863 // IRSND_SUPPORT_RUWIDO_PROTOCOL == 1 || IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1
2864
2865 default:
2866 {
2867 irsnd_busy = FALSE;
2868 break;
2869 }
2870 }
2871 }
2872
2873 if (! irsnd_busy)
2874 {
2875 if (repeat_counter < n_repeat_frames)
2876 {
2877 #if IRSND_SUPPORT_FDC_PROTOCOL == 1
2878 if (irsnd_protocol == IRMP_FDC_PROTOCOL)
2879 {
2880 irsnd_buffer[2] |= 0x0F;
2881 }
2882 #endif
2883 repeat_counter++;
2884 irsnd_busy = TRUE;
2885 }
2886 else
2887 {
2888 irsnd_busy = TRUE; //Rainer
2889 send_trailer = TRUE;
2890 n_repeat_frames = 0;
2891 repeat_counter = 0;
2892 }
2893 }
2894 }
2895
2896 #ifdef ANALYZE
2897 if (irsnd_is_on)
2898 {
2899 putchar ('0');
2900 }
2901 else
2902 {
2903 putchar ('1');
2904 }
2905 #endif
2906
2907 return irsnd_busy;
2908 }
2909
2910 #ifdef ANALYZE
2911
2912 // main function - for unix/linux + windows only!
2913 // AVR: see main.c!
2914 // Compile it under linux with:
2915 // cc irsnd.c -o irsnd
2916 //
2917 // usage: ./irsnd protocol hex-address hex-command >filename
2918
2919 int
2920 main (int argc, char ** argv)
2921 {
2922 int protocol;
2923 int address;
2924 int command;
2925 IRMP_DATA irmp_data;
2926
2927 if (argc != 4 && argc != 5)
2928 {
2929 fprintf (stderr, "usage: %s protocol hex-address hex-command [repeat] > filename\n", argv[0]);
2930 return 1;
2931 }
2932
2933 if (sscanf (argv[1], "%d", &protocol) == 1 &&
2934 sscanf (argv[2], "%x", &address) == 1 &&
2935 sscanf (argv[3], "%x", &command) == 1)
2936 {
2937 irmp_data.protocol = protocol;
2938 irmp_data.address = address;
2939 irmp_data.command = command;
2940
2941 if (argc == 5)
2942 {
2943 irmp_data.flags = atoi (argv[4]);
2944 }
2945 else
2946 {
2947 irmp_data.flags = 0;
2948 }
2949
2950 irsnd_init ();
2951
2952 (void) irsnd_send_data (&irmp_data, TRUE);
2953
2954 while (irsnd_busy)
2955 {
2956 irsnd_ISR ();
2957 }
2958
2959 putchar ('\n');
2960
2961 #if 1 // enable here to send twice
2962 (void) irsnd_send_data (&irmp_data, TRUE);
2963
2964 while (irsnd_busy)
2965 {
2966 irsnd_ISR ();
2967 }
2968
2969 putchar ('\n');
2970 #endif
2971 }
2972 else
2973 {
2974 fprintf (stderr, "%s: wrong arguments\n", argv[0]);
2975 return 1;
2976 }
2977 return 0;
2978 }
2979
2980 #endif // ANALYZE
Clone of IRMP - Infrared Muliti Protocol Decoder (https://www.mikrocontroller.net/articles/IRMP)