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Version 3.0.7 - added SAMSUNGAH protocol, improved some code for ESP8266
[irmp.git] / irsnd.c
1 /*---------------------------------------------------------------------------------------------------------------------------------------------------
2 * @file irsnd.c
3 *
4 * Copyright (c) 2010-2016 Frank Meyer - frank(at)fli4l.de
5 *
6 * Supported AVR mikrocontrollers:
7 *
8 * ATtiny87, ATtiny167
9 * ATtiny45, ATtiny85
10 * ATtiny44 ATtiny84
11 * ATtiny2313 ATtiny4313
12 * ATmega8, ATmega16, ATmega32
13 * ATmega162
14 * ATmega164, ATmega324, ATmega644, ATmega644P, ATmega1284, ATmega1284P
15 * ATmega88, ATmega88P, ATmega168, ATmega168P, ATmega328P
16 *
17 * $Id: irsnd.c,v 1.103 2017/02/17 09:13:06 fm Exp $
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
23 *---------------------------------------------------------------------------------------------------------------------------------------------------
24 */
25
26 #include "irsnd.h"
27
28 #ifndef F_CPU
29 # error F_CPU unkown
30 #endif
31
32 /*---------------------------------------------------------------------------------------------------------------------------------------------------
33 * ATtiny pin definition of OC0A / OC0B
34 * ATmega pin definition of OC2 / OC2A / OC2B / OC0 / OC0A / OC0B
35 *---------------------------------------------------------------------------------------------------------------------------------------------------
36 */
37 #if defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) // ATtiny44/84 uses OC0A = PB2 or OC0B = PA7
38 # if IRSND_OCx == IRSND_OC0A // OC0A
39 # define IRSND_PORT_LETTER B
40 # define IRSND_BIT_NUMBER 2
41 # elif IRSND_OCx == IRSND_OC0B // OC0B
42 # define IRSND_PORT_LETTER A
43 # define IRSND_BIT_NUMBER 7
44 # else
45 # error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h
46 # endif // IRSND_OCx
47
48 #elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45/85 uses OC0A = PB0 or OC0B = PB1
49 # if IRSND_OCx == IRSND_OC0A // OC0A
50 # define IRSND_PORT_LETTER B
51 # define IRSND_BIT_NUMBER 0
52 # elif IRSND_OCx == IRSND_OC0B // OC0B
53 # define IRSND_PORT_LETTER B
54 # define IRSND_BIT_NUMBER 1
55 # else
56 # error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h
57 # endif // IRSND_OCx
58
59 #elif defined (__AVR_ATtiny2313__) || defined (__AVR_ATtiny4313__) // ATtiny2313/4313 uses OC0A = PB2 or OC0B = PD5
60 # if IRSND_OCx == IRSND_OC0A // OC0A
61 # define IRSND_PORT_LETTER B
62 # define IRSND_BIT_NUMBER 2
63 # elif IRSND_OCx == IRSND_OC0B // OC0B
64 # define IRSND_PORT_LETTER D
65 # define IRSND_BIT_NUMBER 5
66 # else
67 # error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h
68 # endif // IRSND_OCx
69
70 #elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) // ATtiny87/167 uses OC0A = PA2
71 # if IRSND_OCx == IRSND_OC0A // OC0A
72 # define IRSND_PORT_LETTER A
73 # define IRSND_BIT_NUMBER 2
74 # else
75 # error Wrong value for IRSND_OCx, choose IRSND_OC0A in irsndconfig.h
76 # endif // IRSND_OCx
77
78 #elif defined (__AVR_ATmega8__) // ATmega8 uses only OC2 = PB3
79 # if IRSND_OCx == IRSND_OC2 // OC2
80 # define IRSND_PORT_LETTER B
81 # define IRSND_BIT_NUMBER 3
82 # else
83 # error Wrong value for IRSND_OCx, choose IRSND_OC2 in irsndconfig.h
84 # endif // IRSND_OCx
85 #elif defined (__AVR_ATmega16__) || defined (__AVR_ATmega32__) // ATmega16|32 uses OC0 = PB3 or OC2 = PD7
86 # if IRSND_OCx == IRSND_OC2 // OC2
87 # define IRSND_PORT_LETTER D
88 # define IRSND_BIT_NUMBER 7
89 # elif IRSND_OCx == IRSND_OC0 // OC0
90 # define IRSND_PORT_LETTER B
91 # define IRSND_BIT_NUMBER 3
92 # else
93 # error Wrong value for IRSND_OCx, choose IRSND_OC2 or IRSND_OC0 in irsndconfig.h
94 # endif // IRSND_OCx
95
96 #elif defined (__AVR_ATmega162__) // ATmega162 uses OC2 = PB1 or OC0 = PB0
97 # if IRSND_OCx == IRSND_OC2 // OC2
98 # define IRSND_PORT_LETTER B
99 # define IRSND_BIT_NUMBER 1
100 # elif IRSND_OCx == IRSND_OC0 // OC0
101 # define IRSND_PORT_LETTER B
102 # define IRSND_BIT_NUMBER 0
103 # else
104 # error Wrong value for IRSND_OCx, choose IRSND_OC2 or IRSND_OC0 in irsndconfig.h
105 # endif // IRSND_OCx
106
107 #elif defined (__AVR_ATmega164__) \
108 || defined (__AVR_ATmega324__) \
109 || defined (__AVR_ATmega644__) \
110 || defined (__AVR_ATmega644P__) \
111 || defined (__AVR_ATmega1284__) \
112 || defined (__AVR_ATmega1284P__) // ATmega164|324|644|644P|1284 uses OC2A = PD7 or OC2B = PD6 or OC0A = PB3 or OC0B = PB4
113 # if IRSND_OCx == IRSND_OC2A // OC2A
114 # define IRSND_PORT_LETTER D
115 # define IRSND_BIT_NUMBER 7
116 # elif IRSND_OCx == IRSND_OC2B // OC2B
117 # define IRSND_PORT_LETTER D
118 # define IRSND_BIT_NUMBER 6
119 # elif IRSND_OCx == IRSND_OC0A // OC0A
120 # define IRSND_PORT_LETTER B
121 # define IRSND_BIT_NUMBER 3
122 # elif IRSND_OCx == IRSND_OC0B // OC0B
123 # define IRSND_PORT_LETTER B
124 # define IRSND_BIT_NUMBER 4
125 # else
126 # error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h
127 # endif // IRSND_OCx
128
129 #elif defined (__AVR_ATmega48__) \
130 || defined (__AVR_ATmega88__) \
131 || defined (__AVR_ATmega88P__) \
132 || defined (__AVR_ATmega168__) \
133 || defined (__AVR_ATmega168P__) \
134 || defined (__AVR_ATmega328P__) // ATmega48|88|168|168|328 uses OC2A = PB3 or OC2B = PD3 or OC0A = PD6 or OC0B = PD5
135 # if IRSND_OCx == IRSND_OC2A // OC2A
136 # define IRSND_PORT_LETTER B
137 # define IRSND_BIT_NUMBER 3
138 # elif IRSND_OCx == IRSND_OC2B // OC2B
139 # define IRSND_PORT_LETTER D
140 # define IRSND_BIT_NUMBER 3
141 # elif IRSND_OCx == IRSND_OC0A // OC0A
142 # define IRSND_PORT_LETTER D
143 # define IRSND_BIT_NUMBER 6
144 # elif IRSND_OCx == IRSND_OC0B // OC0B
145 # define IRSND_PORT_LETTER D
146 # define IRSND_BIT_NUMBER 5
147 # else
148 # error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h
149 # endif // IRSND_OCx
150
151 #elif defined (__AVR_ATmega8515__) // ATmega8515 uses OC0 = PB0 or OC1A = PD5 or OC1B = PE2
152 # if IRSND_OCx == IRSND_OC0
153 # define IRSND_PORT_LETTER B
154 # define IRSND_BIT_NUMBER 0
155 # elif IRSND_OCx == IRSND_OC1A
156 # define IRSND_PORT_LETTER D
157 # define IRSND_BIT_NUMBER 5
158 # elif IRSND_OCx == IRSND_OC1B
159 # define IRSND_PORT_LETTER E
160 # define IRSND_BIT_NUMBER 2
161 # endif // IRSND_OCx
162
163 #elif defined (__AVR_XMEGA__) // ATxmega
164 # if IRSND_OCx == IRSND_XMEGA_OC0A
165 # define IRSND_BIT_NUMBER 0
166 # elif IRSND_OCx == IRSND_XMEGA_OC0B
167 # define IRSND_BIT_NUMBER 1
168 # elif IRSND_OCx == IRSND_XMEGA_OC0C
169 # define IRSND_BIT_NUMBER 2
170 # elif IRSND_OCx == IRSND_XMEGA_OC0D
171 # define IRSND_BIT_NUMBER 3
172 # elif IRSND_OCx == IRSND_XMEGA_OC1A
173 # define IRSND_BIT_NUMBER 4
174 # elif IRSND_OCx == IRSND_XMEGA_OC1B
175 # define IRSND_BIT_NUMBER 5
176 # else
177 # error Wrong value for IRSND_OCx, choose IRSND_XMEGA_OC0A, IRSND_XMEGA_OC0B, IRSND_XMEGA_OC0C, IRSND_XMEGA_OC0D, IRSND_XMEGA_OC1A, or IRSND_XMEGA_OC1B in irsndconfig.h
178 # endif // IRSND_OCx
179
180 #elif defined (PIC_C18) // Microchip C18 compiler
181 //Nothing here to do here -> See irsndconfig.h
182 #elif defined (ARM_STM32) // STM32
183 //Nothing here to do here -> See irsndconfig.h
184 #elif defined (__xtensa__) // ESP8266
185 //Nothing here to do here -> See irsndconfig.h
186
187 /*---------------------------------------------------------------------------------------------------------------------------------------------------
188 * Macro digitalPinHasPWM bothers PIC_C18 compiler, but why?
189 *
190 * #elif defined (TEENSY_ARM_CORTEX_M4) // Teensy3
191 * # if !digitalPinHasPWM(IRSND_PIN)
192 * # error need pin with PWM output.
193 * # endif
194 *---------------------------------------------------------------------------------------------------------------------------------------------------
195 */
196 #else
197 # if !defined (unix) && !defined (WIN32)
198 # error mikrocontroller not defined, please fill in definitions here.
199 # endif // unix, WIN32
200 #endif // __AVR...
201
202 #if defined(__AVR_XMEGA__)
203 # define _CONCAT(a,b) a##b
204 # define CONCAT(a,b) _CONCAT(a,b)
205 # define IRSND_PORT IRSND_PORT_PRE.OUT
206 # define IRSND_DDR IRSND_PORT_PRE.DIR
207 # define IRSND_PIN IRSND_PORT_PRE.IN
208 # define IRSND_BIT IRSND_BIT_NUMBER
209 #elif defined(ATMEL_AVR)
210 # define _CONCAT(a,b) a##b
211 # define CONCAT(a,b) _CONCAT(a,b)
212 # define IRSND_PORT CONCAT(PORT, IRSND_PORT_LETTER)
213 # define IRSND_DDR CONCAT(DDR, IRSND_PORT_LETTER)
214 # define IRSND_BIT IRSND_BIT_NUMBER
215 #endif
216
217 #if IRSND_SUPPORT_NIKON_PROTOCOL == 1
218 typedef uint16_t IRSND_PAUSE_LEN;
219 #else
220 typedef uint8_t IRSND_PAUSE_LEN;
221 #endif
222
223 /*---------------------------------------------------------------------------------------------------------------------------------------------------
224 * IR timings
225 *---------------------------------------------------------------------------------------------------------------------------------------------------
226 */
227 #define SIRCS_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PULSE_TIME + 0.5)
228 #define SIRCS_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_START_BIT_PAUSE_TIME + 0.5)
229 #define SIRCS_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_1_PULSE_TIME + 0.5)
230 #define SIRCS_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_0_PULSE_TIME + 0.5)
231 #define SIRCS_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIRCS_PAUSE_TIME + 0.5)
232 #define SIRCS_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
233 #define SIRCS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIRCS_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
234
235 #define NEC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PULSE_TIME + 0.5)
236 #define NEC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_START_BIT_PAUSE_TIME + 0.5)
237 #define NEC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_REPEAT_START_BIT_PAUSE_TIME + 0.5)
238 #define NEC_PULSE_LEN (uint8_t)(F_INTERRUPTS * NEC_PULSE_TIME + 0.5)
239 #define NEC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_1_PAUSE_TIME + 0.5)
240 #define NEC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NEC_0_PAUSE_TIME + 0.5)
241 #define NEC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NEC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
242
243 #define SAMSUNG_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PULSE_TIME + 0.5)
244 #define SAMSUNG_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_START_BIT_PAUSE_TIME + 0.5)
245 #define SAMSUNG_PULSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_PULSE_TIME + 0.5)
246 #define SAMSUNG_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_1_PAUSE_TIME + 0.5)
247 #define SAMSUNG_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SAMSUNG_0_PAUSE_TIME + 0.5)
248 #define SAMSUNG_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
249
250 #define SAMSUNG32_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
251 #define SAMSUNG32_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG32_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
252
253 #define SAMSUNG48_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG48_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
254 #define SAMSUNG48_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SAMSUNG48_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
255
256 #define MATSUSHITA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PULSE_TIME + 0.5)
257 #define MATSUSHITA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_START_BIT_PAUSE_TIME + 0.5)
258 #define MATSUSHITA_PULSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_PULSE_TIME + 0.5)
259 #define MATSUSHITA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_1_PAUSE_TIME + 0.5)
260 #define MATSUSHITA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MATSUSHITA_0_PAUSE_TIME + 0.5)
261 #define MATSUSHITA_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * MATSUSHITA_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
262
263 #define KASEIKYO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PULSE_TIME + 0.5)
264 #define KASEIKYO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_START_BIT_PAUSE_TIME + 0.5)
265 #define KASEIKYO_PULSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_PULSE_TIME + 0.5)
266 #define KASEIKYO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_1_PAUSE_TIME + 0.5)
267 #define KASEIKYO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * KASEIKYO_0_PAUSE_TIME + 0.5)
268 #define KASEIKYO_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
269 #define KASEIKYO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * KASEIKYO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
270
271 #define PANASONIC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_START_BIT_PULSE_TIME + 0.5)
272 #define PANASONIC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_START_BIT_PAUSE_TIME + 0.5)
273 #define PANASONIC_PULSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_PULSE_TIME + 0.5)
274 #define PANASONIC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_1_PAUSE_TIME + 0.5)
275 #define PANASONIC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PANASONIC_0_PAUSE_TIME + 0.5)
276 #define PANASONIC_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PANASONIC_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
277 #define PANASONIC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PANASONIC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
278
279 #define MITSU_HEAVY_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_START_BIT_PULSE_TIME + 0.5)
280 #define MITSU_HEAVY_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_START_BIT_PAUSE_TIME + 0.5)
281 #define MITSU_HEAVY_PULSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_PULSE_TIME + 0.5)
282 #define MITSU_HEAVY_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_1_PAUSE_TIME + 0.5)
283 #define MITSU_HEAVY_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * MITSU_HEAVY_0_PAUSE_TIME + 0.5)
284 #define MITSU_HEAVY_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * MITSU_HEAVY_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
285
286 #define RECS80_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PULSE_TIME + 0.5)
287 #define RECS80_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_START_BIT_PAUSE_TIME + 0.5)
288 #define RECS80_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_PULSE_TIME + 0.5)
289 #define RECS80_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_1_PAUSE_TIME + 0.5)
290 #define RECS80_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80_0_PAUSE_TIME + 0.5)
291 #define RECS80_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
292
293 #define RC5_START_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)
294 #define RC5_BIT_LEN (uint8_t)(F_INTERRUPTS * RC5_BIT_TIME + 0.5)
295 #define RC5_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC5_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
296
297 #define RC6_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PULSE_TIME + 0.5)
298 #define RC6_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RC6_START_BIT_PAUSE_TIME + 0.5)
299 #define RC6_BIT_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_TIME + 0.5)
300 #define RC6_BIT_2_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_2_TIME + 0.5)
301 #define RC6_BIT_3_LEN (uint8_t)(F_INTERRUPTS * RC6_BIT_3_TIME + 0.5)
302 #define RC6_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RC6_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
303
304 #define DENON_PULSE_LEN (uint8_t)(F_INTERRUPTS * DENON_PULSE_TIME + 0.5)
305 #define DENON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_1_PAUSE_TIME + 0.5)
306 #define DENON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * DENON_0_PAUSE_TIME + 0.5)
307 #define DENON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
308 #define DENON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * DENON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
309
310 #define THOMSON_PULSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_PULSE_TIME + 0.5)
311 #define THOMSON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_1_PAUSE_TIME + 0.5)
312 #define THOMSON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * THOMSON_0_PAUSE_TIME + 0.5)
313 #define THOMSON_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
314 #define THOMSON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * THOMSON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
315
316 #define RECS80EXT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PULSE_TIME + 0.5)
317 #define RECS80EXT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_START_BIT_PAUSE_TIME + 0.5)
318 #define RECS80EXT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_PULSE_TIME + 0.5)
319 #define RECS80EXT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_1_PAUSE_TIME + 0.5)
320 #define RECS80EXT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RECS80EXT_0_PAUSE_TIME + 0.5)
321 #define RECS80EXT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RECS80EXT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
322
323 #define TELEFUNKEN_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_START_BIT_PULSE_TIME + 0.5)
324 #define TELEFUNKEN_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_START_BIT_PAUSE_TIME + 0.5)
325 #define TELEFUNKEN_PULSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_PULSE_TIME + 0.5)
326 #define TELEFUNKEN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_1_PAUSE_TIME + 0.5)
327 #define TELEFUNKEN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * TELEFUNKEN_0_PAUSE_TIME + 0.5)
328 #define TELEFUNKEN_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * TELEFUNKEN_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
329 #define TELEFUNKEN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * TELEFUNKEN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
330
331 #define BOSE_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_START_BIT_PULSE_TIME + 0.5)
332 #define BOSE_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_START_BIT_PAUSE_TIME + 0.5)
333 #define BOSE_PULSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_PULSE_TIME + 0.5)
334 #define BOSE_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_1_PAUSE_TIME + 0.5)
335 #define BOSE_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BOSE_0_PAUSE_TIME + 0.5)
336 #define BOSE_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BOSE_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
337 #define BOSE_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BOSE_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
338
339 #define NUBERT_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PULSE_TIME + 0.5)
340 #define NUBERT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_START_BIT_PAUSE_TIME + 0.5)
341 #define NUBERT_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PULSE_TIME + 0.5)
342 #define NUBERT_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_1_PAUSE_TIME + 0.5)
343 #define NUBERT_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PULSE_TIME + 0.5)
344 #define NUBERT_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NUBERT_0_PAUSE_TIME + 0.5)
345 #define NUBERT_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
346 #define NUBERT_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NUBERT_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
347
348 #define FAN_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_START_BIT_PULSE_TIME + 0.5)
349 #define FAN_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_START_BIT_PAUSE_TIME + 0.5)
350 #define FAN_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_1_PULSE_TIME + 0.5)
351 #define FAN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_1_PAUSE_TIME + 0.5)
352 #define FAN_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * FAN_0_PULSE_TIME + 0.5)
353 #define FAN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FAN_0_PAUSE_TIME + 0.5)
354 #define FAN_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FAN_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
355 #define FAN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FAN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
356
357 #define SPEAKER_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_START_BIT_PULSE_TIME + 0.5)
358 #define SPEAKER_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_START_BIT_PAUSE_TIME + 0.5)
359 #define SPEAKER_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_1_PULSE_TIME + 0.5)
360 #define SPEAKER_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_1_PAUSE_TIME + 0.5)
361 #define SPEAKER_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_0_PULSE_TIME + 0.5)
362 #define SPEAKER_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SPEAKER_0_PAUSE_TIME + 0.5)
363 #define SPEAKER_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SPEAKER_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
364 #define SPEAKER_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SPEAKER_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
365
366 #define BANG_OLUFSEN_START_BIT1_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PULSE_TIME + 0.5)
367 #define BANG_OLUFSEN_START_BIT1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT1_PAUSE_TIME + 0.5)
368 #define BANG_OLUFSEN_START_BIT2_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PULSE_TIME + 0.5)
369 #define BANG_OLUFSEN_START_BIT2_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT2_PAUSE_TIME + 0.5)
370 #define BANG_OLUFSEN_START_BIT3_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PULSE_TIME + 0.5)
371 #define BANG_OLUFSEN_START_BIT3_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_START_BIT3_PAUSE_TIME + 0.5)
372 #define BANG_OLUFSEN_PULSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_PULSE_TIME + 0.5)
373 #define BANG_OLUFSEN_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_1_PAUSE_TIME + 0.5)
374 #define BANG_OLUFSEN_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_0_PAUSE_TIME + 0.5)
375 #define BANG_OLUFSEN_R_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_R_PAUSE_TIME + 0.5)
376 #define BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * BANG_OLUFSEN_TRAILER_BIT_PAUSE_TIME + 0.5)
377 #define BANG_OLUFSEN_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * BANG_OLUFSEN_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
378
379 #define GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_PRE_PAUSE_TIME + 0.5)
380 #define GRUNDIG_NOKIA_IR60_BIT_LEN (uint8_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_BIT_TIME + 0.5)
381 #define GRUNDIG_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
382 #define NOKIA_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NOKIA_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
383 #define GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
384
385 #define IR60_AUTO_REPETITION_PAUSE_LEN (uint16_t)(F_INTERRUPTS * IR60_AUTO_REPETITION_PAUSE_TIME + 0.5) // use uint16_t!
386
387 #define SIEMENS_START_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME + 0.5)
388 #define SIEMENS_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)
389 #define SIEMENS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
390
391 #define RUWIDO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME + 0.5)
392 #define RUWIDO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PAUSE_TIME + 0.5)
393 #define RUWIDO_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)
394 #define RUWIDO_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PAUSE_TIME + 0.5)
395 #define RUWIDO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
396
397 #ifdef PIC_C18 // PIC C18
398 # define IRSND_FREQ_TYPE uint8_t
399 # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
400 # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
401 # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
402 # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
403 # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
404 # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
405 # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / 2 / Pre_Scaler / PIC_Scaler) - 1)
406 #elif defined (ARM_STM32) // STM32
407 # define IRSND_FREQ_TYPE uint32_t
408 # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)
409 # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)
410 # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)
411 # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)
412 # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)
413 # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)
414 # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)
415 #elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY
416 # define IRSND_FREQ_TYPE float
417 # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)
418 # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)
419 # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)
420 # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)
421 # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)
422 # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)
423 # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)
424 #elif defined (__xtensa__) // ESP8266
425 # define IRSND_FREQ_TYPE float
426 # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) (30000)
427 # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) (32000)
428 # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) (36000)
429 # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) (38000)
430 # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) (40000)
431 # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)
432 # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)
433 #else // AVR
434 # if F_CPU >= 16000000L
435 # define AVR_PRESCALER 8
436 # else
437 # define AVR_PRESCALER 1
438 # endif
439 # define IRSND_FREQ_TYPE uint8_t
440 # define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / AVR_PRESCALER / 2) - 1)
441 # define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / AVR_PRESCALER / 2) - 1)
442 # define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / AVR_PRESCALER / 2) - 1)
443 # define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / AVR_PRESCALER / 2) - 1)
444 # define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / AVR_PRESCALER / 2) - 1)
445 # define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / AVR_PRESCALER / 2) - 1)
446 # define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / AVR_PRESCALER / 2) - 1)
447 #endif
448
449 #define FDC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PULSE_TIME + 0.5)
450 #define FDC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PAUSE_TIME + 0.5)
451 #define FDC_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_PULSE_TIME + 0.5)
452 #define FDC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_1_PAUSE_TIME + 0.5)
453 #define FDC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * FDC_0_PAUSE_TIME + 0.5)
454 #define FDC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * FDC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
455
456 #define RCCAR_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PULSE_TIME + 0.5)
457 #define RCCAR_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_START_BIT_PAUSE_TIME + 0.5)
458 #define RCCAR_PULSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_PULSE_TIME + 0.5)
459 #define RCCAR_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_1_PAUSE_TIME + 0.5)
460 #define RCCAR_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * RCCAR_0_PAUSE_TIME + 0.5)
461 #define RCCAR_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * RCCAR_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
462
463 #define JVC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PULSE_TIME + 0.5)
464 #define JVC_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_START_BIT_PAUSE_TIME + 0.5)
465 #define JVC_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_REPEAT_START_BIT_PAUSE_TIME + 0.5)
466 #define JVC_PULSE_LEN (uint8_t)(F_INTERRUPTS * JVC_PULSE_TIME + 0.5)
467 #define JVC_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_1_PAUSE_TIME + 0.5)
468 #define JVC_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * JVC_0_PAUSE_TIME + 0.5)
469 #define JVC_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * JVC_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
470
471 #define NIKON_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_START_BIT_PULSE_TIME + 0.5)
472 #define NIKON_START_BIT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_START_BIT_PAUSE_TIME + 0.5)
473 #define NIKON_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_REPEAT_START_BIT_PAUSE_TIME + 0.5)
474 #define NIKON_PULSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_PULSE_TIME + 0.5)
475 #define NIKON_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_1_PAUSE_TIME + 0.5)
476 #define NIKON_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * NIKON_0_PAUSE_TIME + 0.5)
477 #define NIKON_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * NIKON_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
478
479 #define LEGO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PULSE_TIME + 0.5)
480 #define LEGO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_START_BIT_PAUSE_TIME + 0.5)
481 #define LEGO_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_REPEAT_START_BIT_PAUSE_TIME + 0.5)
482 #define LEGO_PULSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_PULSE_TIME + 0.5)
483 #define LEGO_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_1_PAUSE_TIME + 0.5)
484 #define LEGO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_0_PAUSE_TIME + 0.5)
485 #define LEGO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * LEGO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
486
487 #define A1TVBOX_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_START_BIT_PULSE_TIME + 0.5)
488 #define A1TVBOX_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_START_BIT_PAUSE_TIME + 0.5)
489 #define A1TVBOX_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_BIT_PULSE_TIME + 0.5)
490 #define A1TVBOX_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_BIT_PAUSE_TIME + 0.5)
491 #define A1TVBOX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * A1TVBOX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
492 #define A1TVBOX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * A1TVBOX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
493
494 #define ROOMBA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_START_BIT_PULSE_TIME + 0.5)
495 #define ROOMBA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_START_BIT_PAUSE_TIME + 0.5)
496 #define ROOMBA_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_1_PULSE_TIME + 0.5)
497 #define ROOMBA_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_0_PULSE_TIME + 0.5)
498 #define ROOMBA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_1_PAUSE_TIME + 0.5)
499 #define ROOMBA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_0_PAUSE_TIME + 0.5)
500 #define ROOMBA_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * ROOMBA_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
501
502 #define PENTAX_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_START_BIT_PULSE_TIME + 0.5)
503 #define PENTAX_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_START_BIT_PAUSE_TIME + 0.5)
504 #define PENTAX_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_REPEAT_START_BIT_PAUSE_TIME + 0.5)
505 #define PENTAX_PULSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_PULSE_TIME + 0.5)
506 #define PENTAX_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_1_PAUSE_TIME + 0.5)
507 #define PENTAX_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * PENTAX_0_PAUSE_TIME + 0.5)
508 #define PENTAX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * PENTAX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
509
510 #define ACP24_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_START_BIT_PULSE_TIME + 0.5)
511 #define ACP24_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_START_BIT_PAUSE_TIME + 0.5)
512 #define ACP24_REPEAT_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_REPEAT_START_BIT_PAUSE_TIME + 0.5)
513 #define ACP24_PULSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_PULSE_TIME + 0.5)
514 #define ACP24_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_1_PAUSE_TIME + 0.5)
515 #define ACP24_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ACP24_0_PAUSE_TIME + 0.5)
516 #define ACP24_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * ACP24_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!
517
518 static volatile uint8_t irsnd_busy = 0;
519 static volatile uint8_t irsnd_protocol = 0;
520 static volatile uint8_t irsnd_buffer[11] = {0};
521 static volatile uint8_t irsnd_repeat = 0;
522 static volatile uint8_t irsnd_is_on = FALSE;
523
524 #if IRSND_USE_CALLBACK == 1
525 static void (*irsnd_callback_ptr) (uint8_t);
526 #endif // IRSND_USE_CALLBACK == 1
527
528 /*---------------------------------------------------------------------------------------------------------------------------------------------------
529 * Switch PWM on
530 *---------------------------------------------------------------------------------------------------------------------------------------------------
531 */
532 static void
533 irsnd_on (void)
534 {
535 if (! irsnd_is_on)
536 {
537 #ifndef ANALYZE
538 # if defined(PIC_C18) // PIC C18
539 PWMon();
540 // IRSND_PIN = 0; // output mode -> enable PWM outout pin (0=PWM on, 1=PWM off)
541
542 # elif defined (ARM_STM32) // STM32
543 TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCMode_PWM1); // enable PWM as OC-mode
544 TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())
545 TIM_Cmd(IRSND_TIMER, ENABLE); // enable counter
546
547 # elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY
548 analogWrite(IRSND_PIN, 33 * 255 / 100); // pwm 33%
549
550 # elif defined (__xtensa__) // ESP8266 (Arduino)
551 analogWrite(IRSND_PIN, 33 * 1023 / 100); // pwm 33%
552
553 # elif defined (__AVR_XMEGA__)
554 # if (IRSND_OCx == IRSND_XMEGA_OC0A) // use OC0A
555 XMEGA_Timer.CTRLB |= (1<<TC0_CCAEN_bp); // Compare A
556 # elif (IRSND_OCx == IRSND_XMEGA_OC0B) // use OC0B
557 XMEGA_Timer.CTRLB |= (1<<TC0_CCBEN_bp); // Compare B
558 # elif IRSND_OCx == IRSND_XMEGA_OC0C // use OC0C
559 XMEGA_Timer.CTRLB |= (1<<TC0_CCCEN_bp); // Compare C
560 # elif IRSND_OCx == IRSND_XMEGA_OC0D // use OC0D
561 XMEGA_Timer.CTRLB |= (1<<TC0_CCDEN_bp); // Compare D
562 # elif IRSND_OCx == IRSND_XMEGA_OC1A // use OC1A
563 XMEGA_Timer.CTRLB |= (1<<TC1_CCAEN_bp); // Compare A
564 # elif IRSND_OCx == IRSND_XMEGA_OC1B // use OC1B
565 XMEGA_Timer.CTRLB |= (1<<TC1_CCBEN_bp); // Compare B
566 # else
567 # error wrong value of IRSND_OCx
568 # endif // IRSND_OCx
569
570 # else // AVR
571 # if IRSND_OCx == IRSND_OC2 // use OC2
572 TCCR2 |= (1<<COM20)|(1<<WGM21); // toggle OC2 on compare match, clear Timer 2 at compare match OCR2
573 # elif IRSND_OCx == IRSND_OC2A // use OC2A
574 TCCR2A |= (1<<COM2A0)|(1<<WGM21); // toggle OC2A on compare match, clear Timer 2 at compare match OCR2A
575 # elif IRSND_OCx == IRSND_OC2B // use OC2B
576 TCCR2A |= (1<<COM2B0)|(1<<WGM21); // toggle OC2B on compare match, clear Timer 2 at compare match OCR2A (yes: A, not B!)
577 # elif IRSND_OCx == IRSND_OC0 // use OC0
578 TCCR0 |= (1<<COM00)|(1<<WGM01); // toggle OC0 on compare match, clear Timer 0 at compare match OCR0
579 # elif IRSND_OCx == IRSND_OC0A // use OC0A
580 TCCR0A |= (1<<COM0A0)|(1<<WGM01); // toggle OC0A on compare match, clear Timer 0 at compare match OCR0A
581 # elif IRSND_OCx == IRSND_OC0B // use OC0B
582 TCCR0A |= (1<<COM0B0)|(1<<WGM01); // toggle OC0B on compare match, clear Timer 0 at compare match OCR0A (yes: A, not B!)
583 # else
584 # error wrong value of IRSND_OCx
585 # endif // IRSND_OCx
586 # endif // C18
587 #endif // ANALYZE
588
589 #if IRSND_USE_CALLBACK == 1
590 if (irsnd_callback_ptr)
591 {
592 (*irsnd_callback_ptr) (TRUE);
593 }
594 #endif // IRSND_USE_CALLBACK == 1
595
596 irsnd_is_on = TRUE;
597 }
598 }
599
600 /*---------------------------------------------------------------------------------------------------------------------------------------------------
601 * Switch PWM off
602 * @details Switches PWM off
603 *---------------------------------------------------------------------------------------------------------------------------------------------------
604 */
605 static void
606 irsnd_off (void)
607 {
608 if (irsnd_is_on)
609 {
610 #ifndef ANALYZE
611
612 # if defined(PIC_C18) // PIC C18
613 PWMoff();
614 // IRSND_PIN = 1; //input mode -> disbale PWM output pin (0=PWM on, 1=PWM off)
615
616 # elif defined (ARM_STM32) // STM32
617 TIM_Cmd(IRSND_TIMER, DISABLE); // disable counter
618 TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_ForcedAction_InActive); // force output inactive
619 TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())
620 TIM_SetCounter(IRSND_TIMER, 0); // reset counter value
621
622 # elif defined (TEENSY_ARM_CORTEX_M4) // TEENSY
623 analogWrite(IRSND_PIN, 0); // pwm off, LOW level
624
625 # elif defined (__xtensa__) // ESP8266
626 analogWrite(IRSND_PIN, 0); // pwm off, LOW level
627
628 # elif defined (__AVR_XMEGA__)
629 # if (IRSND_OCx == IRSND_XMEGA_OC0A) // use OC0A
630 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCAEN_bp); // Compare A disconnected
631 # elif (IRSND_OCx == IRSND_XMEGA_OC0B) // use OC0B
632 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCBEN_bp); // Compare B disconnected
633 # elif IRSND_OCx == IRSND_XMEGA_OC0C // use OC0C
634 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCCEN_bp); // Compare C disconnected
635 # elif IRSND_OCx == IRSND_XMEGA_OC0D // use OC0D
636 XMEGA_Timer.CTRLB &= ~(1<<TC0_CCDEN_bp); // Compare D disconnected
637 # elif IRSND_OCx == IRSND_XMEGA_OC1A // use OC1A
638 XMEGA_Timer.CTRLB &= ~(1<<TC1_CCAEN_bp); // Compare A disconnected
639 # elif IRSND_OCx == IRSND_XMEGA_OC1B // use OC1B
640 XMEGA_Timer.CTRLB &= ~(1<<TC1_CCBEN_bp); // Compare B disconnected
641 # else
642 # error wrong value of IRSND_OCx
643 # endif // IRSND_OCx
644
645 # else //AVR
646
647 # if IRSND_OCx == IRSND_OC2 // use OC2
648 TCCR2 &= ~(1<<COM20); // normal port operation, OC2 disconnected.
649 # elif IRSND_OCx == IRSND_OC2A // use OC2A
650 TCCR2A &= ~(1<<COM2A0); // normal port operation, OC2A disconnected.
651 # elif IRSND_OCx == IRSND_OC2B // use OC2B
652 TCCR2A &= ~(1<<COM2B0); // normal port operation, OC2B disconnected.
653 # elif IRSND_OCx == IRSND_OC0 // use OC0
654 TCCR0 &= ~(1<<COM00); // normal port operation, OC0 disconnected.
655 # elif IRSND_OCx == IRSND_OC0A // use OC0A
656 TCCR0A &= ~(1<<COM0A0); // normal port operation, OC0A disconnected.
657 # elif IRSND_OCx == IRSND_OC0B // use OC0B
658 TCCR0A &= ~(1<<COM0B0); // normal port operation, OC0B disconnected.
659 # else
660 # error wrong value of IRSND_OCx
661 # endif // IRSND_OCx
662 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low
663 # endif //C18
664 #endif // ANALYZE
665
666 #if IRSND_USE_CALLBACK == 1
667 if (irsnd_callback_ptr)
668 {
669 (*irsnd_callback_ptr) (FALSE);
670 }
671 #endif // IRSND_USE_CALLBACK == 1
672
673 irsnd_is_on = FALSE;
674 }
675 }
676
677 /*---------------------------------------------------------------------------------------------------------------------------------------------------
678 * Set PWM frequency
679 * @details sets pwm frequency
680 *---------------------------------------------------------------------------------------------------------------------------------------------------
681 */
682 #if defined(__12F1840)
683 extern void pwm_init(uint16_t freq);
684 #include <stdio.h>
685 #endif
686
687 static void
688 irsnd_set_freq (IRSND_FREQ_TYPE freq)
689 {
690 #ifndef ANALYZE
691 # if defined(PIC_C18) // PIC C18 or XC8
692 # if defined(__12F1840) // XC8
693 TRISA2=0;
694 PR2=freq;
695 CCP1M0=1;
696 CCP1M1=1;
697 CCP1M2=1;
698 CCP1M3=1;
699 DC1B0=1;
700 DC1B1=0;
701 CCPR1L = 0b01101001;
702 TMR2IF = 0;
703 TMR2ON=1;
704 CCP1CON &=(~0b0011); // p 197 "active high"
705 # else // PIC C18
706 OpenPWM(freq);
707 SetDCPWM( (uint16_t) (freq * 2) + 1); // freq*2 = Duty cycles 50%
708 # endif
709 PWMoff();
710 # elif defined (ARM_STM32) // STM32
711 static uint32_t TimeBaseFreq = 0;
712
713 if (TimeBaseFreq == 0)
714 {
715 RCC_ClocksTypeDef RCC_ClocksStructure;
716 /* Get system clocks and store timer clock in variable */
717 RCC_GetClocksFreq(&RCC_ClocksStructure);
718 # if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))
719 if (RCC_ClocksStructure.PCLK1_Frequency == RCC_ClocksStructure.HCLK_Frequency)
720 {
721 TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency;
722 }
723 else
724 {
725 TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency * 2;
726 }
727 # else
728 if (RCC_ClocksStructure.PCLK2_Frequency == RCC_ClocksStructure.HCLK_Frequency)
729 {
730 TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency;
731 }
732 else
733 {
734 TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency * 2;
735 }
736 # endif
737 }
738
739 freq = TimeBaseFreq/freq;
740
741 /* Set frequency */
742 TIM_SetAutoreload(IRSND_TIMER, freq - 1);
743 /* Set duty cycle */
744 TIM_SetCompare1(IRSND_TIMER, (freq + 1) / 2);
745
746 # elif defined (TEENSY_ARM_CORTEX_M4)
747 analogWriteResolution(8); // 8 bit
748 analogWriteFrequency(IRSND_PIN, freq);
749 analogWrite(IRSND_PIN, 0); // pwm off, LOW level
750
751 #elif defined (__xtensa__)
752 // analogWriteRange(255);
753 analogWriteFreq(freq);
754 analogWrite(IRSND_PIN, 0); // pwm off, LOW level
755
756 # elif defined (__AVR_XMEGA__)
757 XMEGA_Timer.CCA = freq;
758
759 # else // AVR
760
761 # if IRSND_OCx == IRSND_OC2
762 OCR2 = freq; // use register OCR2 for OC2
763 # elif IRSND_OCx == IRSND_OC2A // use OC2A
764 OCR2A = freq; // use register OCR2A for OC2A and OC2B!
765 # elif IRSND_OCx == IRSND_OC2B // use OC2B
766 OCR2A = freq; // use register OCR2A for OC2A and OC2B!
767 # elif IRSND_OCx == IRSND_OC0 // use OC0
768 OCR0 = freq; // use register OCR2 for OC2
769 # elif IRSND_OCx == IRSND_OC0A // use OC0A
770 OCR0A = freq; // use register OCR0A for OC0A and OC0B!
771 # elif IRSND_OCx == IRSND_OC0B // use OC0B
772 OCR0A = freq; // use register OCR0A for OC0A and OC0B!
773 # else
774 # error wrong value of IRSND_OCx
775 # endif
776 # endif //PIC_C18
777 #endif // ANALYZE
778 }
779
780 /*---------------------------------------------------------------------------------------------------------------------------------------------------
781 * Initialize the PWM
782 * @details Configures 0CR0A, 0CR0B and 0CR2B as PWM channels
783 *---------------------------------------------------------------------------------------------------------------------------------------------------
784 */
785 void
786 irsnd_init (void)
787 {
788 #ifndef ANALYZE
789 # if defined(PIC_C18) // PIC C18 or XC8 compiler
790 # if ! defined(__12F1840) // only C18:
791 OpenTimer;
792 # endif
793 irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency
794 IRSND_PIN = 0; // set IO to outout
795 PWMoff();
796 # elif defined (ARM_STM32) // STM32
797 GPIO_InitTypeDef GPIO_InitStructure;
798 TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
799 TIM_OCInitTypeDef TIM_OCInitStructure;
800
801 /* GPIOx clock enable */
802 # if defined (ARM_STM32L1XX)
803 RCC_AHBPeriphClockCmd(IRSND_PORT_RCC, ENABLE);
804 # elif defined (ARM_STM32F10X)
805 RCC_APB2PeriphClockCmd(IRSND_PORT_RCC, ENABLE);
806 // RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); // only in case of remapping, not necessary for default port-timer mapping
807 # elif defined (ARM_STM32F4XX)
808 RCC_AHB1PeriphClockCmd(IRSND_PORT_RCC, ENABLE);
809 # endif
810
811 /* GPIO Configuration */
812 GPIO_InitStructure.GPIO_Pin = IRSND_BIT;
813 # if defined (ARM_STM32L1XX) || defined (ARM_STM32F4XX)
814 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
815 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
816 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
817 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
818 GPIO_Init(IRSND_PORT, &GPIO_InitStructure);
819 GPIO_PinAFConfig(IRSND_PORT, (uint8_t)IRSND_BIT_NUMBER, IRSND_GPIO_AF);
820 # elif defined (ARM_STM32F10X)
821 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
822 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
823 GPIO_Init(IRSND_PORT, &GPIO_InitStructure);
824 // GPIO_PinRemapConfig(GPIO_*Remap*_TIM[IRSND_TIMER_NUMBER], ENABLE); // only in case of remapping, not necessary for default port-timer mapping
825 # endif
826
827 /* TIMx clock enable */
828 # if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))
829 RCC_APB1PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);
830 # else
831 RCC_APB2PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);
832 # endif
833
834 /* Time base configuration */
835 TIM_TimeBaseStructure.TIM_Period = -1; // set dummy value (don't set to 0), will be initialized later
836 TIM_TimeBaseStructure.TIM_Prescaler = 0;
837 TIM_TimeBaseStructure.TIM_ClockDivision = 0;
838 TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
839 TIM_TimeBaseInit(IRSND_TIMER, &TIM_TimeBaseStructure);
840
841 /* PWM1 Mode configuration */
842 TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
843 TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
844 TIM_OCInitStructure.TIM_Pulse = 0; // will be initialized later
845 TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
846 TIM_OC1Init(IRSND_TIMER, &TIM_OCInitStructure);
847
848 /* Preload configuration */
849 TIM_ARRPreloadConfig(IRSND_TIMER, ENABLE);
850 TIM_OC1PreloadConfig(IRSND_TIMER, TIM_OCPreload_Enable);
851
852 irsnd_set_freq (IRSND_FREQ_36_KHZ); // set default frequency
853
854 # elif defined (TEENSY_ARM_CORTEX_M4)
855 if (!digitalPinHasPWM(IRSND_PIN))
856 {
857 return;
858 }
859
860 # elif defined (__xtensa__)
861 pinMode(IRSND_PIN, OUTPUT);
862 irsnd_set_freq (IRSND_FREQ_36_KHZ);
863
864 # elif defined (__AVR_XMEGA__)
865 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low
866 IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output
867
868 XMEGA_Timer.PER = 0xFFFF; //Topwert
869 XMEGA_Timer.CTRLB |= TC_WGMODE_FRQ_gc; //Modus: Frequenz entspricht CTC
870
871 # if AVR_PRESCALER == 8
872 XMEGA_Timer.CTRLA |= TC_CLKSEL_DIV8_gc; // start Timer prescaler = 8
873 # else
874 XMEGA_Timer.CTRLA |= TC_CLKSEL_DIV1_gc; // start Timer prescaler = 1
875 # endif
876
877 # else // AVR
878 IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low
879 IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output
880
881 # if IRSND_OCx == IRSND_OC2 // use OC2
882 TCCR2 = (1<<WGM21); // CTC mode
883 # if AVR_PRESCALER == 8
884 TCCR2 |= (1<<CS21); // start Timer 2, prescaler = 8
885 # else
886 TCCR2 |= (1<<CS20); // start Timer 2, prescaler = 1
887 # endif
888 # elif IRSND_OCx == IRSND_OC2A || IRSND_OCx == IRSND_OC2B // use OC2A or OC2B
889 TCCR2A = (1<<WGM21); // CTC mode
890 # if AVR_PRESCALER == 8
891 TCCR2B = (1<<CS21); // start Timer 2, prescaler = 8
892 # else
893 TCCR2B = (1<<CS20); // start Timer 2, prescaler = 1
894 # endif
895 # elif IRSND_OCx == IRSND_OC0 // use OC0
896 TCCR0 = (1<<WGM01); // CTC mode
897 # if AVR_PRESCALER == 8
898 TCCR0 |= (1<<CS01); // start Timer 0, prescaler = 8
899 # else
900 TCCR0 |= (1<<CS00); // start Timer 0, prescaler = 1
901 # endif
902 # elif IRSND_OCx == IRSND_OC0A || IRSND_OCx == IRSND_OC0B // use OC0A or OC0B
903 TCCR0A = (1<<WGM01); // CTC mode
904 # if AVR_PRESCALER == 8
905 TCCR0B = (1<<CS01); // start Timer 0, prescaler = 8
906 # else
907 TCCR0B = (1<<CS00); // start Timer 0, prescaler = 1
908 # endif
909 # else
910 # error wrong value of IRSND_OCx
911 # endif
912 irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency
913 # endif //PIC_C18
914 #endif // ANALYZE
915 }
916
917 #if IRSND_USE_CALLBACK == 1
918 void
919 irsnd_set_callback_ptr (void (*cb)(uint8_t))
920 {
921 irsnd_callback_ptr = cb;
922 }
923 #endif // IRSND_USE_CALLBACK == 1
924
925 uint8_t
926 irsnd_is_busy (void)
927 {
928 return irsnd_busy;
929 }
930
931 static uint16_t
932 bitsrevervse (uint16_t x, uint8_t len)
933 {
934 uint16_t xx = 0;
935
936 while(len)
937 {
938 xx <<= 1;
939 if (x & 1)
940 {
941 xx |= 1;
942 }
943 x >>= 1;
944 len--;
945 }
946 return xx;
947 }
948
949
950 #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1
951 static uint8_t sircs_additional_bitlen;
952 #endif // IRSND_SUPPORT_SIRCS_PROTOCOL == 1
953
954 uint8_t
955 irsnd_send_data (IRMP_DATA * irmp_data_p, uint8_t do_wait)
956 {
957 #if IRSND_SUPPORT_RECS80_PROTOCOL == 1
958 static uint8_t toggle_bit_recs80;
959 #endif
960 #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1
961 static uint8_t toggle_bit_recs80ext;
962 #endif
963 #if IRSND_SUPPORT_RC5_PROTOCOL == 1
964 static uint8_t toggle_bit_rc5;
965 #endif
966 #if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1
967 static uint8_t toggle_bit_rc6;
968 #endif
969 #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1
970 static uint8_t toggle_bit_thomson;
971 #endif
972 uint16_t address;
973 uint16_t command;
974
975 if (do_wait)
976 {
977 while (irsnd_busy)
978 {
979 // do nothing;
980 }
981 }
982 else if (irsnd_busy)
983 {
984 return (FALSE);
985 }
986
987 irsnd_protocol = irmp_data_p->protocol;
988 irsnd_repeat = irmp_data_p->flags & IRSND_REPETITION_MASK;
989
990 switch (irsnd_protocol)
991 {
992 #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1
993 case IRMP_SIRCS_PROTOCOL:
994 {
995 // uint8_t sircs_additional_command_len;
996 uint8_t sircs_additional_address_len;
997
998 sircs_additional_bitlen = (irmp_data_p->address & 0xFF00) >> 8; // additional bitlen
999
1000 if (sircs_additional_bitlen > 15 - SIRCS_MINIMUM_DATA_LEN)
1001 {
1002 // sircs_additional_command_len = 15 - SIRCS_MINIMUM_DATA_LEN;
1003 sircs_additional_address_len = sircs_additional_bitlen - (15 - SIRCS_MINIMUM_DATA_LEN);
1004 }
1005 else
1006 {
1007 // sircs_additional_command_len = sircs_additional_bitlen;
1008 sircs_additional_address_len = 0;
1009 }
1010
1011 command = bitsrevervse (irmp_data_p->command, 15);
1012
1013 irsnd_buffer[0] = (command & 0x7F80) >> 7; // CCCCCCCC
1014 irsnd_buffer[1] = (command & 0x007F) << 1; // CCCC****
1015
1016 if (sircs_additional_address_len > 0)
1017 {
1018 address = bitsrevervse (irmp_data_p->address, 5);
1019 irsnd_buffer[1] |= (address & 0x0010) >> 4;
1020 irsnd_buffer[2] = (address & 0x000F) << 4;
1021 }
1022 irsnd_busy = TRUE;
1023 break;
1024 }
1025 #endif
1026 #if IRSND_SUPPORT_NEC_PROTOCOL == 1
1027 case IRMP_APPLE_PROTOCOL:
1028 {
1029 command = irmp_data_p->command | (irmp_data_p->address << 8); // store address as ID in upper byte of command
1030 address = 0x87EE; // set fixed NEC-lookalike address (customer ID of apple)
1031
1032 address = bitsrevervse (address, NEC_ADDRESS_LEN);
1033 command = bitsrevervse (command, NEC_COMMAND_LEN);
1034
1035 irsnd_protocol = IRMP_NEC_PROTOCOL; // APPLE protocol is NEC with id instead of inverted command
1036
1037 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1038 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1039 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC
1040 irsnd_buffer[3] = 0x8B; // 10001011 (id)
1041 irsnd_busy = TRUE;
1042 break;
1043 }
1044 case IRMP_NEC_PROTOCOL:
1045 {
1046 address = bitsrevervse (irmp_data_p->address, NEC_ADDRESS_LEN);
1047 command = bitsrevervse (irmp_data_p->command, NEC_COMMAND_LEN);
1048
1049 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1050 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1051 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC
1052 irsnd_buffer[3] = ~((command & 0xFF00) >> 8); // cccccccc
1053 irsnd_busy = TRUE;
1054 break;
1055 }
1056 #endif
1057 #if IRSND_SUPPORT_NEC16_PROTOCOL == 1
1058 case IRMP_NEC16_PROTOCOL:
1059 {
1060 address = bitsrevervse (irmp_data_p->address, NEC16_ADDRESS_LEN);
1061 command = bitsrevervse (irmp_data_p->command, NEC16_COMMAND_LEN);
1062
1063 irsnd_buffer[0] = (address & 0x00FF); // AAAAAAAA
1064 irsnd_buffer[1] = (command & 0x00FF); // CCCCCCCC
1065 irsnd_busy = TRUE;
1066 break;
1067 }
1068 #endif
1069 #if IRSND_SUPPORT_NEC42_PROTOCOL == 1
1070 case IRMP_NEC42_PROTOCOL:
1071 {
1072 address = bitsrevervse (irmp_data_p->address, NEC42_ADDRESS_LEN);
1073 command = bitsrevervse (irmp_data_p->command, NEC42_COMMAND_LEN);
1074
1075 irsnd_buffer[0] = ( (address & 0x1FE0) >> 5); // AAAAAAAA
1076 irsnd_buffer[1] = ( (address & 0x001F) << 3) | ((~address & 0x1C00) >> 10); // AAAAAaaa
1077 irsnd_buffer[2] = ((~address & 0x03FC) >> 2); // aaaaaaaa
1078 irsnd_buffer[3] = ((~address & 0x0003) << 6) | ( (command & 0x00FC) >> 2); // aaCCCCCC
1079 irsnd_buffer[4] = ( (command & 0x0003) << 6) | ((~command & 0x00FC) >> 2); // CCcccccc
1080 irsnd_buffer[5] = ((~command & 0x0003) << 6); // cc
1081 irsnd_busy = TRUE;
1082 break;
1083 }
1084 #endif
1085 #if IRSND_SUPPORT_LGAIR_PROTOCOL == 1
1086 case IRMP_LGAIR_PROTOCOL:
1087 {
1088 address = irmp_data_p->address;
1089 command = irmp_data_p->command;
1090
1091 irsnd_buffer[0] = ( (address & 0x00FF)); // AAAAAAAA
1092 irsnd_buffer[1] = ( (command & 0xFF00) >> 8); // CCCCCCCC
1093 irsnd_buffer[2] = ( (command & 0x00FF)); // CCCCCCCC
1094 irsnd_buffer[3] = (( ((command & 0xF000) >> 12) + // checksum
1095 ((command & 0x0F00) >> 8) +
1096 ((command & 0x00F0) >>4 ) +
1097 ((command & 0x000F))) & 0x000F) << 4;
1098 irsnd_busy = TRUE;
1099 break;
1100 }
1101 #endif
1102 #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1
1103 case IRMP_SAMSUNG_PROTOCOL:
1104 {
1105 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);
1106 command = bitsrevervse (irmp_data_p->command, SAMSUNG_COMMAND_LEN);
1107
1108 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1109 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1110 irsnd_buffer[2] = (command & 0x00F0) | ((command & 0xF000) >> 12); // IIIICCCC
1111 irsnd_buffer[3] = ((command & 0x0F00) >> 4) | ((~(command & 0xF000) >> 12) & 0x0F); // CCCCcccc
1112 irsnd_buffer[4] = (~(command & 0x0F00) >> 4) & 0xF0; // cccc0000
1113 irsnd_busy = TRUE;
1114 break;
1115 }
1116 case IRMP_SAMSUNG32_PROTOCOL:
1117 {
1118 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);
1119 command = bitsrevervse (irmp_data_p->command, SAMSUNG32_COMMAND_LEN);
1120
1121 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1122 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1123 irsnd_buffer[2] = (command & 0xFF00) >> 8; // CCCCCCCC
1124 irsnd_buffer[3] = (command & 0x00FF); // CCCCCCCC
1125 irsnd_busy = TRUE;
1126 break;
1127 }
1128 #endif
1129 #if IRSND_SUPPORT_SAMSUNG48_PROTOCOL == 1
1130 case IRMP_SAMSUNG48_PROTOCOL:
1131 {
1132 address = bitsrevervse (irmp_data_p->address, SAMSUNG_ADDRESS_LEN);
1133 command = bitsrevervse (irmp_data_p->command, 16);
1134
1135 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1136 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1137 irsnd_buffer[2] = ((command & 0xFF00) >> 8); // CCCCCCCC
1138 irsnd_buffer[3] = ~((command & 0xFF00) >> 8); // cccccccc
1139 irsnd_buffer[4] = (command & 0x00FF); // CCCCCCCC
1140 irsnd_buffer[5] = ~(command & 0x00FF); // cccccccc
1141 irsnd_busy = TRUE;
1142 break;
1143 }
1144 #endif
1145 #if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1
1146 case IRMP_MATSUSHITA_PROTOCOL:
1147 {
1148 address = bitsrevervse (irmp_data_p->address, MATSUSHITA_ADDRESS_LEN);
1149 command = bitsrevervse (irmp_data_p->command, MATSUSHITA_COMMAND_LEN);
1150
1151 irsnd_buffer[0] = (command & 0x0FF0) >> 4; // CCCCCCCC
1152 irsnd_buffer[1] = ((command & 0x000F) << 4) | ((address & 0x0F00) >> 8); // CCCCAAAA
1153 irsnd_buffer[2] = (address & 0x00FF); // AAAAAAAA
1154 irsnd_busy = TRUE;
1155 break;
1156 }
1157 #endif
1158 #if IRSND_SUPPORT_TECHNICS_PROTOCOL == 1
1159 case IRMP_TECHNICS_PROTOCOL:
1160 {
1161 command = bitsrevervse (irmp_data_p->command, TECHNICS_COMMAND_LEN);
1162
1163 irsnd_buffer[0] = (command & 0x07FC) >> 3; // CCCCCCCC
1164 irsnd_buffer[1] = ((command & 0x0007) << 5) | ((~command & 0x07C0) >> 6); // CCCccccc
1165 irsnd_buffer[2] = (~command & 0x003F) << 2; // cccccc
1166 irsnd_busy = TRUE;
1167 break;
1168 }
1169 #endif
1170 #if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1
1171 case IRMP_KASEIKYO_PROTOCOL:
1172 {
1173 uint8_t xor_value;
1174 uint16_t genre2;
1175
1176 address = bitsrevervse (irmp_data_p->address, KASEIKYO_ADDRESS_LEN);
1177 command = bitsrevervse (irmp_data_p->command, KASEIKYO_COMMAND_LEN + 4);
1178 genre2 = bitsrevervse ((irmp_data_p->flags & ~IRSND_REPETITION_MASK) >> 4, 4);
1179
1180 xor_value = ((address & 0x000F) ^ ((address & 0x00F0) >> 4) ^ ((address & 0x0F00) >> 8) ^ ((address & 0xF000) >> 12)) & 0x0F;
1181
1182 irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA
1183 irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA
1184 irsnd_buffer[2] = xor_value << 4 | (command & 0x000F); // XXXXCCCC
1185 irsnd_buffer[3] = (genre2 << 4) | (command & 0xF000) >> 12; // ggggCCCC
1186 irsnd_buffer[4] = (command & 0x0FF0) >> 4; // CCCCCCCC
1187
1188 xor_value = irsnd_buffer[2] ^ irsnd_buffer[3] ^ irsnd_buffer[4];
1189
1190 irsnd_buffer[5] = xor_value;
1191 irsnd_busy = TRUE;
1192 break;
1193 }
1194 #endif
1195 #if IRSND_SUPPORT_PANASONIC_PROTOCOL == 1
1196 case IRMP_PANASONIC_PROTOCOL:
1197 {
1198 address = bitsrevervse (irmp_data_p->address, PANASONIC_ADDRESS_LEN);
1199 command = bitsrevervse (irmp_data_p->command, PANASONIC_COMMAND_LEN);
1200
1201 irsnd_buffer[0] = 0x40; // 01000000
1202 irsnd_buffer[1] = 0x04; // 00000100
1203 irsnd_buffer[2] = 0x01; // 00000001
1204 irsnd_buffer[3] = (address & 0xFF00) >> 8; // AAAAAAAA
1205 irsnd_buffer[4] = (address & 0x00FF); // AAAAAAAA
1206 irsnd_buffer[5] = (command & 0xFF00) >> 8; // CCCCCCCC
1207 irsnd_buffer[6] = (command & 0x00FF); // CCCCCCCC
1208
1209 irsnd_busy = TRUE;
1210 break;
1211 }
1212 #endif
1213 #if IRSND_SUPPORT_MITSU_HEAVY_PROTOCOL == 1
1214 case IRMP_MITSU_HEAVY_PROTOCOL:
1215 {
1216 address = irmp_data_p->address;
1217 command = irmp_data_p->command;
1218
1219 irsnd_buffer[0] = 0x4A;
1220 irsnd_buffer[1] = 0x75;
1221 irsnd_buffer[2] = 0xC3;
1222 irsnd_buffer[3] = 0x64;
1223 irsnd_buffer[4] = 0x9B;
1224 irsnd_buffer[5] = ~(address & 0xFF00) >> 8;
1225 irsnd_buffer[6] = (address & 0xFF00) >> 8;
1226 irsnd_buffer[7] = ~(address & 0x00FF);
1227 irsnd_buffer[8] = (address & 0x00FF);
1228 irsnd_buffer[9] = ~(command & 0x00FF);
1229 irsnd_buffer[10] = (command & 0x00FF);
1230
1231 irsnd_busy = TRUE;
1232 break;
1233 }
1234 #endif
1235 #if IRSND_SUPPORT_RECS80_PROTOCOL == 1
1236 case IRMP_RECS80_PROTOCOL:
1237 {
1238 toggle_bit_recs80 = toggle_bit_recs80 ? 0x00 : 0x80;
1239
1240 irsnd_buffer[0] = toggle_bit_recs80 | ((irmp_data_p->address & 0x000F) << 4) |
1241 ((irmp_data_p->command & 0x003C) >> 2); // TAAACCCC
1242 irsnd_buffer[1] = (irmp_data_p->command & 0x03) << 6; // CC000000
1243 irsnd_busy = TRUE;
1244 break;
1245 }
1246 #endif
1247 #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1
1248 case IRMP_RECS80EXT_PROTOCOL:
1249 {
1250 toggle_bit_recs80ext = toggle_bit_recs80ext ? 0x00 : 0x40;
1251
1252 irsnd_buffer[0] = 0x80 | toggle_bit_recs80ext | ((irmp_data_p->address & 0x000F) << 2) |
1253 ((irmp_data_p->command & 0x0030) >> 4); // STAAAACC
1254 irsnd_buffer[1] = (irmp_data_p->command & 0x0F) << 4; // CCCC0000
1255 irsnd_busy = TRUE;
1256 break;
1257 }
1258 #endif
1259 #if IRSND_SUPPORT_RC5_PROTOCOL == 1
1260 case IRMP_RC5_PROTOCOL:
1261 {
1262 toggle_bit_rc5 = toggle_bit_rc5 ? 0x00 : 0x40;
1263
1264 irsnd_buffer[0] = ((irmp_data_p->command & 0x40) ? 0x00 : 0x80) | toggle_bit_rc5 |
1265 ((irmp_data_p->address & 0x001F) << 1) | ((irmp_data_p->command & 0x20) >> 5); // CTAAAAAC
1266 irsnd_buffer[1] = (irmp_data_p->command & 0x1F) << 3; // CCCCC000
1267 irsnd_busy = TRUE;
1268 break;
1269 }
1270 #endif
1271 #if IRSND_SUPPORT_RC6_PROTOCOL == 1
1272 case IRMP_RC6_PROTOCOL:
1273 {
1274 toggle_bit_rc6 = toggle_bit_rc6 ? 0x00 : 0x08;
1275
1276 irsnd_buffer[0] = 0x80 | toggle_bit_rc6 | ((irmp_data_p->address & 0x00E0) >> 5); // 1MMMTAAA, MMM = 000
1277 irsnd_buffer[1] = ((irmp_data_p->address & 0x001F) << 3) | ((irmp_data_p->command & 0xE0) >> 5); // AAAAACCC
1278 irsnd_buffer[2] = (irmp_data_p->command & 0x1F) << 3; // CCCCC
1279 irsnd_busy = TRUE;
1280 break;
1281 }
1282 #endif
1283 #if IRSND_SUPPORT_RC6A_PROTOCOL == 1
1284 case IRMP_RC6A_PROTOCOL:
1285 {
1286 toggle_bit_rc6 = toggle_bit_rc6 ? 0x00 : 0x08;
1287
1288 irsnd_buffer[0] = 0x80 | 0x60 | ((irmp_data_p->address & 0x3000) >> 12); // 1MMMT0AA, MMM = 110
1289 irsnd_buffer[1] = ((irmp_data_p->address & 0x0FFF) >> 4) ; // AAAAAAAA
1290 irsnd_buffer[2] = ((irmp_data_p->address & 0x000F) << 4) | ((irmp_data_p->command & 0xF000) >> 12) | toggle_bit_rc6; // AAAACCCC
1291 irsnd_buffer[3] = (irmp_data_p->command & 0x0FF0) >> 4; // CCCCCCCC
1292 irsnd_buffer[4] = (irmp_data_p->command & 0x000F) << 4; // CCCC
1293 irsnd_busy = TRUE;
1294 break;
1295 }
1296 #endif
1297 #if IRSND_SUPPORT_DENON_PROTOCOL == 1
1298 case IRMP_DENON_PROTOCOL:
1299 {
1300 irsnd_buffer[0] = ((irmp_data_p->address & 0x1F) << 3) | ((irmp_data_p->command & 0x0380) >> 7); // AAAAACCC (1st frame)
1301 irsnd_buffer[1] = (irmp_data_p->command & 0x7F) << 1; // CCCCCCC
1302 irsnd_buffer[2] = ((irmp_data_p->address & 0x1F) << 3) | (((~irmp_data_p->command) & 0x0380) >> 7); // AAAAAccc (2nd frame)
1303 irsnd_buffer[3] = (~(irmp_data_p->command) & 0x7F) << 1; // ccccccc
1304 irsnd_busy = TRUE;
1305 break;
1306 }
1307 #endif
1308 #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1
1309 case IRMP_THOMSON_PROTOCOL:
1310 {
1311 toggle_bit_thomson = toggle_bit_thomson ? 0x00 : 0x08;
1312
1313 irsnd_buffer[0] = ((irmp_data_p->address & 0x0F) << 4) | toggle_bit_thomson | ((irmp_data_p->command & 0x0070) >> 4); // AAAATCCC (1st frame)
1314 irsnd_buffer[1] = (irmp_data_p->command & 0x0F) << 4; // CCCC
1315 irsnd_busy = TRUE;
1316 break;
1317 }
1318 #endif
1319 #if IRSND_SUPPORT_BOSE_PROTOCOL == 1
1320 case IRMP_BOSE_PROTOCOL:
1321 {
1322 command = bitsrevervse (irmp_data_p->command, BOSE_COMMAND_LEN);
1323
1324 irsnd_buffer[0] = (command & 0xFF00) >> 8; // CCCCCCCC
1325 irsnd_buffer[1] = ~((command & 0xFF00) >> 8); // cccccccc
1326 irsnd_busy = TRUE;
1327 break;
1328 }
1329 #endif
1330 #if IRSND_SUPPORT_NUBERT_PROTOCOL == 1
1331 case IRMP_NUBERT_PROTOCOL:
1332 {
1333 irsnd_buffer[0] = irmp_data_p->command >> 2; // CCCCCCCC
1334 irsnd_buffer[1] = (irmp_data_p->command & 0x0003) << 6; // CC000000
1335 irsnd_busy = TRUE;
1336 break;
1337 }
1338 #endif
1339 #if IRSND_SUPPORT_FAN_PROTOCOL == 1
1340 case IRMP_FAN_PROTOCOL:
1341 {
1342 irsnd_buffer[0] = irmp_data_p->command >> 3; // CCCCCCCC
1343 irsnd_buffer[1] = (irmp_data_p->command & 0x0007) << 5; // CCC00000
1344 irsnd_busy = TRUE;
1345 break;
1346 }
1347 #endif
1348 #if IRSND_SUPPORT_SPEAKER_PROTOCOL == 1
1349 case IRMP_SPEAKER_PROTOCOL:
1350 {
1351 irsnd_buffer[0] = irmp_data_p->command >> 2; // CCCCCCCC
1352 irsnd_buffer[1] = (irmp_data_p->command & 0x0003) << 6; // CC000000
1353 irsnd_busy = TRUE;
1354 break;
1355 }
1356 #endif
1357 #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1
1358 case IRMP_BANG_OLUFSEN_PROTOCOL:
1359 {
1360 irsnd_buffer[0] = irmp_data_p->command >> 11; // SXSCCCCC
1361 irsnd_buffer[1] = irmp_data_p->command >> 3; // CCCCCCCC
1362 irsnd_buffer[2] = (irmp_data_p->command & 0x0007) << 5; // CCC00000
1363 irsnd_busy = TRUE;
1364 break;
1365 }
1366 #endif
1367 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1
1368 case IRMP_GRUNDIG_PROTOCOL:
1369 {
1370 command = bitsrevervse (irmp_data_p->command, TELEFUNKEN_COMMAND_LEN);
1371
1372 irsnd_buffer[0] = 0xFF; // S1111111 (1st frame)
1373 irsnd_buffer[1] = 0xC0; // 11
1374 irsnd_buffer[2] = 0x80 | (command >> 2); // SCCCCCCC (2nd frame)
1375 irsnd_buffer[3] = (command << 6) & 0xC0; // CC
1376
1377 irsnd_busy = TRUE;
1378 break;
1379 }
1380 #endif
1381 #if IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1
1382 case IRMP_TELEFUNKEN_PROTOCOL:
1383 {
1384 irsnd_buffer[0] = irmp_data_p->command >> 7; // CCCCCCCC
1385 irsnd_buffer[1] = (irmp_data_p->command << 1) & 0xff; // CCCCCCC
1386
1387 irsnd_busy = TRUE;
1388 break;
1389 }
1390 #endif
1391 #if IRSND_SUPPORT_IR60_PROTOCOL == 1
1392 case IRMP_IR60_PROTOCOL:
1393 {
1394 command = (bitsrevervse (0x7d, IR60_COMMAND_LEN) << 7) | bitsrevervse (irmp_data_p->command, IR60_COMMAND_LEN);
1395 #if 0
1396 irsnd_buffer[0] = command >> 6 | 0x01; // 1011111S (start instruction frame)
1397 irsnd_buffer[1] = (command & 0x7F) << 1; // CCCCCCC_ (2nd frame)
1398 #else
1399 irsnd_buffer[0] = ((command & 0x7F) << 1) | 0x01; // CCCCCCCS (1st frame)
1400 irsnd_buffer[1] = command >> 6; // 1011111_ (start instruction frame)
1401 #endif
1402
1403 irsnd_busy = TRUE;
1404 break;
1405 }
1406 #endif
1407 #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1
1408 case IRMP_NOKIA_PROTOCOL:
1409 {
1410 address = bitsrevervse (irmp_data_p->address, NOKIA_ADDRESS_LEN);
1411 command = bitsrevervse (irmp_data_p->command, NOKIA_COMMAND_LEN);
1412
1413 irsnd_buffer[0] = 0xBF; // S0111111 (1st + 3rd frame)
1414 irsnd_buffer[1] = 0xFF; // 11111111
1415 irsnd_buffer[2] = 0x80; // 1
1416 irsnd_buffer[3] = 0x80 | command >> 1; // SCCCCCCC (2nd frame)
1417 irsnd_buffer[4] = (command << 7) | (address >> 1); // CAAAAAAA
1418 irsnd_buffer[5] = (address << 7); // A
1419
1420 irsnd_busy = TRUE;
1421 break;
1422 }
1423 #endif
1424 #if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1
1425 case IRMP_SIEMENS_PROTOCOL:
1426 {
1427 irsnd_buffer[0] = ((irmp_data_p->address & 0x07FF) >> 3); // AAAAAAAA
1428 irsnd_buffer[1] = ((irmp_data_p->address & 0x0007) << 5) | ((irmp_data_p->command >> 5) & 0x1F); // AAACCCCC
1429 irsnd_buffer[2] = ((irmp_data_p->command & 0x001F) << 3) | ((~irmp_data_p->command & 0x01) << 2); // CCCCCc
1430
1431 irsnd_busy = TRUE;
1432 break;
1433 }
1434 #endif
1435 #if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1
1436 case IRMP_RUWIDO_PROTOCOL:
1437 {
1438 irsnd_buffer[0] = ((irmp_data_p->address & 0x01FF) >> 1); // AAAAAAAA
1439 irsnd_buffer[1] = ((irmp_data_p->address & 0x0001) << 7) | ((irmp_data_p->command & 0x7F)); // ACCCCCCC
1440 irsnd_buffer[2] = ((~irmp_data_p->command & 0x01) << 7); // c
1441 irsnd_busy = TRUE;
1442 break;
1443 }
1444 #endif
1445 #if IRSND_SUPPORT_FDC_PROTOCOL == 1
1446 case IRMP_FDC_PROTOCOL:
1447 {
1448 address = bitsrevervse (irmp_data_p->address, FDC_ADDRESS_LEN);
1449 command = bitsrevervse (irmp_data_p->command, FDC_COMMAND_LEN);
1450
1451 irsnd_buffer[0] = (address & 0xFF); // AAAAAAAA
1452 irsnd_buffer[1] = 0; // 00000000
1453 irsnd_buffer[2] = 0; // 0000RRRR
1454 irsnd_buffer[3] = (command & 0xFF); // CCCCCCCC
1455 irsnd_buffer[4] = ~(command & 0xFF); // cccccccc
1456 irsnd_busy = TRUE;
1457 break;
1458 }
1459 #endif
1460 #if IRSND_SUPPORT_RCCAR_PROTOCOL == 1
1461 case IRMP_RCCAR_PROTOCOL:
1462 {
1463 address = bitsrevervse (irmp_data_p->address, 2); // A0 A1
1464 command = bitsrevervse (irmp_data_p->command, RCCAR_COMMAND_LEN - 2); // D0 D1 D2 D3 D4 D5 D6 D7 C0 C1 V
1465
1466 irsnd_buffer[0] = ((command & 0x06) << 5) | ((address & 0x0003) << 4) | ((command & 0x0780) >> 7); // C0 C1 A0 A1 D0 D1 D2 D3
1467 irsnd_buffer[1] = ((command & 0x78) << 1) | ((command & 0x0001) << 3); // D4 D5 D6 D7 V 0 0 0
1468
1469 irsnd_busy = TRUE;
1470 break;
1471 }
1472 #endif
1473 #if IRSND_SUPPORT_JVC_PROTOCOL == 1
1474 case IRMP_JVC_PROTOCOL:
1475 {
1476 address = bitsrevervse (irmp_data_p->address, JVC_ADDRESS_LEN);
1477 command = bitsrevervse (irmp_data_p->command, JVC_COMMAND_LEN);
1478
1479 irsnd_buffer[0] = ((address & 0x000F) << 4) | (command & 0x0F00) >> 8; // AAAACCCC
1480 irsnd_buffer[1] = (command & 0x00FF); // CCCCCCCC
1481
1482 irsnd_busy = TRUE;
1483 break;
1484 }
1485 #endif
1486 #if IRSND_SUPPORT_NIKON_PROTOCOL == 1
1487 case IRMP_NIKON_PROTOCOL:
1488 {
1489 irsnd_buffer[0] = (irmp_data_p->command & 0x0003) << 6; // CC
1490 irsnd_busy = TRUE;
1491 break;
1492 }
1493 #endif
1494 #if IRSND_SUPPORT_LEGO_PROTOCOL == 1
1495 case IRMP_LEGO_PROTOCOL:
1496 {
1497 uint8_t crc = 0x0F ^ ((irmp_data_p->command & 0x0F00) >> 8) ^ ((irmp_data_p->command & 0x00F0) >> 4) ^ (irmp_data_p->command & 0x000F);
1498
1499 irsnd_buffer[0] = (irmp_data_p->command & 0x0FF0) >> 4; // CCCCCCCC
1500 irsnd_buffer[1] = ((irmp_data_p->command & 0x000F) << 4) | crc; // CCCCcccc
1501 irsnd_busy = TRUE;
1502 break;
1503 }
1504 #endif
1505 #if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1
1506 case IRMP_A1TVBOX_PROTOCOL:
1507 {
1508 irsnd_buffer[0] = 0x80 | (irmp_data_p->address >> 2); // 10AAAAAA
1509 irsnd_buffer[1] = (irmp_data_p->address << 6) | (irmp_data_p->command >> 2); // AACCCCCC
1510 irsnd_buffer[2] = (irmp_data_p->command << 6); // CC
1511
1512 irsnd_busy = TRUE;
1513 break;
1514 }
1515 #endif
1516 #if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1
1517 case IRMP_ROOMBA_PROTOCOL:
1518 {
1519 irsnd_buffer[0] = (irmp_data_p->command & 0x7F) << 1; // CCCCCCC.
1520 irsnd_busy = TRUE;
1521 break;
1522 }
1523 #endif
1524 #if IRSND_SUPPORT_PENTAX_PROTOCOL == 1
1525 case IRMP_PENTAX_PROTOCOL:
1526 {
1527 irsnd_buffer[0] = (irmp_data_p->command & 0x3F) << 2; // CCCCCC..
1528 irsnd_busy = TRUE;
1529 break;
1530 }
1531 #endif
1532 #if IRSND_SUPPORT_ACP24_PROTOCOL == 1
1533 # define ACP_SET_BIT(acp24_bitno, c, irmp_bitno) \
1534 do \
1535 { \
1536 if ((c) & (1<<(irmp_bitno))) \
1537 { \
1538 irsnd_buffer[((acp24_bitno)>>3)] |= 1 << (((7 - (acp24_bitno)) & 0x07)); \
1539 } \
1540 } while (0)
1541
1542 case IRMP_ACP24_PROTOCOL:
1543 {
1544 uint16_t cmd = irmp_data_p->command;
1545 uint8_t i;
1546
1547 address = bitsrevervse (irmp_data_p->address, ACP24_ADDRESS_LEN);
1548
1549 for (i = 0; i < 8; i++)
1550 {
1551 irsnd_buffer[i] = 0x00; // CCCCCCCC
1552 }
1553
1554 // ACP24-Frame:
1555 // 1 2 3 4 5 6
1556 // 0123456789012345678901234567890123456789012345678901234567890123456789
1557 // N VVMMM ? ??? t vmA x y TTTT
1558 //
1559 // irmp_data_p->command:
1560 //
1561 // 5432109876543210
1562 // NAVVvMMMmtxyTTTT
1563
1564 ACP_SET_BIT( 0, cmd, 15);
1565 ACP_SET_BIT(24, cmd, 14);
1566 ACP_SET_BIT( 2, cmd, 13);
1567 ACP_SET_BIT( 3, cmd, 12);
1568 ACP_SET_BIT(22, cmd, 11);
1569 ACP_SET_BIT( 4, cmd, 10);
1570 ACP_SET_BIT( 5, cmd, 9);
1571 ACP_SET_BIT( 6, cmd, 8);
1572 ACP_SET_BIT(23, cmd, 7);
1573 ACP_SET_BIT(20, cmd, 6);
1574 ACP_SET_BIT(26, cmd, 5);
1575 ACP_SET_BIT(44, cmd, 4);
1576 ACP_SET_BIT(66, cmd, 3);
1577 ACP_SET_BIT(67, cmd, 2);
1578 ACP_SET_BIT(68, cmd, 1);
1579 ACP_SET_BIT(69, cmd, 0);
1580
1581 irsnd_busy = TRUE;
1582 break;
1583 }
1584 #endif
1585
1586 default:
1587 {
1588 break;
1589 }
1590 }
1591
1592 return irsnd_busy;
1593 }
1594
1595 void
1596 irsnd_stop (void)
1597 {
1598 irsnd_repeat = 0;
1599 }
1600
1601 /*---------------------------------------------------------------------------------------------------------------------------------------------------
1602 * ISR routine
1603 * @details ISR routine, called 10000 times per second
1604 *---------------------------------------------------------------------------------------------------------------------------------------------------
1605 */
1606 uint8_t
1607 irsnd_ISR (void)
1608 {
1609 static uint8_t send_trailer = FALSE;
1610 static uint8_t current_bit = 0xFF;
1611 static uint8_t pulse_counter = 0;
1612 static IRSND_PAUSE_LEN pause_counter = 0;
1613 static uint8_t startbit_pulse_len = 0;
1614 static IRSND_PAUSE_LEN startbit_pause_len = 0;
1615 static uint8_t pulse_1_len = 0;
1616 static uint8_t pause_1_len = 0;
1617 static uint8_t pulse_0_len = 0;
1618 static uint8_t pause_0_len = 0;
1619 static uint8_t has_stop_bit = 0;
1620 static uint8_t new_frame = TRUE;
1621 static uint8_t complete_data_len = 0;
1622 static uint8_t n_repeat_frames = 0; // number of repetition frames
1623 static uint8_t n_auto_repetitions = 0; // number of auto_repetitions
1624 static uint8_t auto_repetition_counter = 0; // auto_repetition counter
1625 static uint16_t auto_repetition_pause_len = 0; // pause before auto_repetition, uint16_t!
1626 static uint16_t auto_repetition_pause_counter = 0; // pause before auto_repetition, uint16_t!
1627 static uint8_t repeat_counter = 0; // repeat counter
1628 static uint16_t repeat_frame_pause_len = 0; // pause before repeat, uint16_t!
1629 static uint16_t packet_repeat_pause_counter = 0; // pause before repeat, uint16_t!
1630 #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1
1631 static uint8_t last_bit_value;
1632 #endif
1633 static uint8_t pulse_len = 0xFF;
1634 static IRSND_PAUSE_LEN pause_len = 0xFF;
1635
1636 if (irsnd_busy)
1637 {
1638 if (current_bit == 0xFF && new_frame) // start of transmission...
1639 {
1640 if (auto_repetition_counter > 0)
1641 {
1642 auto_repetition_pause_counter++;
1643
1644 if (auto_repetition_pause_counter >= auto_repetition_pause_len)
1645 {
1646 auto_repetition_pause_counter = 0;
1647
1648 #if IRSND_SUPPORT_DENON_PROTOCOL == 1
1649 if (irsnd_protocol == IRMP_DENON_PROTOCOL) // n'th denon frame
1650 {
1651 current_bit = 16;
1652 complete_data_len = 2 * DENON_COMPLETE_DATA_LEN + 1;
1653 }
1654 else
1655 #endif
1656 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1
1657 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL) // n'th grundig frame
1658 {
1659 current_bit = 15;
1660 complete_data_len = 16 + GRUNDIG_COMPLETE_DATA_LEN;
1661 }
1662 else
1663 #endif
1664 #if IRSND_SUPPORT_IR60_PROTOCOL == 1
1665 if (irsnd_protocol == IRMP_IR60_PROTOCOL) // n'th IR60 frame
1666 {
1667 current_bit = 7;
1668 complete_data_len = 2 * IR60_COMPLETE_DATA_LEN + 1;
1669 }
1670 else
1671 #endif
1672 #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1
1673 if (irsnd_protocol == IRMP_NOKIA_PROTOCOL) // n'th nokia frame
1674 {
1675 if (auto_repetition_counter + 1 < n_auto_repetitions)
1676 {
1677 current_bit = 23;
1678 complete_data_len = 24 + NOKIA_COMPLETE_DATA_LEN;
1679 }
1680 else // nokia stop frame
1681 {
1682 current_bit = 0xFF;
1683 complete_data_len = NOKIA_COMPLETE_DATA_LEN;
1684 }
1685 }
1686 else
1687 #endif
1688 {
1689 ;
1690 }
1691 }
1692 else
1693 {
1694 #ifdef ANALYZE
1695 if (irsnd_is_on)
1696 {
1697 putchar ('0');
1698 }
1699 else
1700 {
1701 putchar ('1');
1702 }
1703 #endif
1704 return irsnd_busy;
1705 }
1706 }
1707 else if (packet_repeat_pause_counter < repeat_frame_pause_len)
1708 {
1709 packet_repeat_pause_counter++;
1710 #ifdef ANALYZE
1711 if (irsnd_is_on)
1712 {
1713 putchar ('0');
1714 }
1715 else
1716 {
1717 putchar ('1');
1718 }
1719 #endif
1720 return irsnd_busy;
1721 }
1722 else
1723 {
1724 if (send_trailer)
1725 {
1726 irsnd_busy = FALSE;
1727 send_trailer = FALSE;
1728 return irsnd_busy;
1729 }
1730
1731 n_repeat_frames = irsnd_repeat;
1732
1733 if (n_repeat_frames == IRSND_ENDLESS_REPETITION)
1734 {
1735 n_repeat_frames = 255;
1736 }
1737
1738 packet_repeat_pause_counter = 0;
1739 pulse_counter = 0;
1740 pause_counter = 0;
1741
1742 switch (irsnd_protocol)
1743 {
1744 #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1
1745 case IRMP_SIRCS_PROTOCOL:
1746 {
1747 startbit_pulse_len = SIRCS_START_BIT_PULSE_LEN;
1748 startbit_pause_len = SIRCS_START_BIT_PAUSE_LEN - 1;
1749 pulse_1_len = SIRCS_1_PULSE_LEN;
1750 pause_1_len = SIRCS_PAUSE_LEN - 1;
1751 pulse_0_len = SIRCS_0_PULSE_LEN;
1752 pause_0_len = SIRCS_PAUSE_LEN - 1;
1753 has_stop_bit = SIRCS_STOP_BIT;
1754 complete_data_len = SIRCS_MINIMUM_DATA_LEN + sircs_additional_bitlen;
1755 n_auto_repetitions = (repeat_counter == 0) ? SIRCS_FRAMES : 1; // 3 frames auto repetition if first frame
1756 auto_repetition_pause_len = SIRCS_AUTO_REPETITION_PAUSE_LEN; // 25ms pause
1757 repeat_frame_pause_len = SIRCS_FRAME_REPEAT_PAUSE_LEN;
1758 irsnd_set_freq (IRSND_FREQ_40_KHZ);
1759 break;
1760 }
1761 #endif
1762 #if IRSND_SUPPORT_NEC_PROTOCOL == 1
1763 case IRMP_NEC_PROTOCOL:
1764 {
1765 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;
1766
1767 if (repeat_counter > 0)
1768 {
1769 startbit_pause_len = NEC_REPEAT_START_BIT_PAUSE_LEN - 1;
1770 complete_data_len = 0;
1771 }
1772 else
1773 {
1774 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;
1775 complete_data_len = NEC_COMPLETE_DATA_LEN;
1776 }
1777
1778 pulse_1_len = NEC_PULSE_LEN;
1779 pause_1_len = NEC_1_PAUSE_LEN - 1;
1780 pulse_0_len = NEC_PULSE_LEN;
1781 pause_0_len = NEC_0_PAUSE_LEN - 1;
1782 has_stop_bit = NEC_STOP_BIT;
1783 n_auto_repetitions = 1; // 1 frame
1784 auto_repetition_pause_len = 0;
1785 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;
1786 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1787 break;
1788 }
1789 #endif
1790 #if IRSND_SUPPORT_NEC16_PROTOCOL == 1
1791 case IRMP_NEC16_PROTOCOL:
1792 {
1793 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;
1794 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;
1795 pulse_1_len = NEC_PULSE_LEN;
1796 pause_1_len = NEC_1_PAUSE_LEN - 1;
1797 pulse_0_len = NEC_PULSE_LEN;
1798 pause_0_len = NEC_0_PAUSE_LEN - 1;
1799 has_stop_bit = NEC_STOP_BIT;
1800 complete_data_len = NEC16_COMPLETE_DATA_LEN + 1; // 1 more: sync bit
1801 n_auto_repetitions = 1; // 1 frame
1802 auto_repetition_pause_len = 0;
1803 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;
1804 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1805 break;
1806 }
1807 #endif
1808 #if IRSND_SUPPORT_NEC42_PROTOCOL == 1
1809 case IRMP_NEC42_PROTOCOL:
1810 {
1811 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;
1812 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;
1813 pulse_1_len = NEC_PULSE_LEN;
1814 pause_1_len = NEC_1_PAUSE_LEN - 1;
1815 pulse_0_len = NEC_PULSE_LEN;
1816 pause_0_len = NEC_0_PAUSE_LEN - 1;
1817 has_stop_bit = NEC_STOP_BIT;
1818 complete_data_len = NEC42_COMPLETE_DATA_LEN;
1819 n_auto_repetitions = 1; // 1 frame
1820 auto_repetition_pause_len = 0;
1821 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;
1822 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1823 break;
1824 }
1825 #endif
1826 #if IRSND_SUPPORT_LGAIR_PROTOCOL == 1
1827 case IRMP_LGAIR_PROTOCOL:
1828 {
1829 startbit_pulse_len = NEC_START_BIT_PULSE_LEN;
1830 startbit_pause_len = NEC_START_BIT_PAUSE_LEN - 1;
1831 pulse_1_len = NEC_PULSE_LEN;
1832 pause_1_len = NEC_1_PAUSE_LEN - 1;
1833 pulse_0_len = NEC_PULSE_LEN;
1834 pause_0_len = NEC_0_PAUSE_LEN - 1;
1835 has_stop_bit = NEC_STOP_BIT;
1836 complete_data_len = LGAIR_COMPLETE_DATA_LEN;
1837 n_auto_repetitions = 1; // 1 frame
1838 auto_repetition_pause_len = 0;
1839 repeat_frame_pause_len = NEC_FRAME_REPEAT_PAUSE_LEN;
1840 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1841 break;
1842 }
1843 #endif
1844 #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1
1845 case IRMP_SAMSUNG_PROTOCOL:
1846 {
1847 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;
1848 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;
1849 pulse_1_len = SAMSUNG_PULSE_LEN;
1850 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;
1851 pulse_0_len = SAMSUNG_PULSE_LEN;
1852 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;
1853 has_stop_bit = SAMSUNG_STOP_BIT;
1854 complete_data_len = SAMSUNG_COMPLETE_DATA_LEN;
1855 n_auto_repetitions = 1; // 1 frame
1856 auto_repetition_pause_len = 0;
1857 repeat_frame_pause_len = SAMSUNG_FRAME_REPEAT_PAUSE_LEN;
1858 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1859 break;
1860 }
1861
1862 case IRMP_SAMSUNG32_PROTOCOL:
1863 {
1864 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;
1865 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;
1866 pulse_1_len = SAMSUNG_PULSE_LEN;
1867 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;
1868 pulse_0_len = SAMSUNG_PULSE_LEN;
1869 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;
1870 has_stop_bit = SAMSUNG_STOP_BIT;
1871 complete_data_len = SAMSUNG32_COMPLETE_DATA_LEN;
1872 n_auto_repetitions = SAMSUNG32_FRAMES; // 1 frame
1873 auto_repetition_pause_len = SAMSUNG32_AUTO_REPETITION_PAUSE_LEN; // 47 ms pause
1874 repeat_frame_pause_len = SAMSUNG32_FRAME_REPEAT_PAUSE_LEN;
1875 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1876 break;
1877 }
1878 #endif
1879 #if IRSND_SUPPORT_SAMSUNG48_PROTOCOL == 1
1880 case IRMP_SAMSUNG48_PROTOCOL:
1881 {
1882 startbit_pulse_len = SAMSUNG_START_BIT_PULSE_LEN;
1883 startbit_pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;
1884 pulse_1_len = SAMSUNG_PULSE_LEN;
1885 pause_1_len = SAMSUNG_1_PAUSE_LEN - 1;
1886 pulse_0_len = SAMSUNG_PULSE_LEN;
1887 pause_0_len = SAMSUNG_0_PAUSE_LEN - 1;
1888 has_stop_bit = SAMSUNG_STOP_BIT;
1889 complete_data_len = SAMSUNG48_COMPLETE_DATA_LEN;
1890 n_auto_repetitions = SAMSUNG48_FRAMES; // 1 frame
1891 auto_repetition_pause_len = SAMSUNG48_AUTO_REPETITION_PAUSE_LEN; // 47 ms pause
1892 repeat_frame_pause_len = SAMSUNG48_FRAME_REPEAT_PAUSE_LEN;
1893 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1894 break;
1895 }
1896 #endif
1897 #if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1
1898 case IRMP_MATSUSHITA_PROTOCOL:
1899 {
1900 startbit_pulse_len = MATSUSHITA_START_BIT_PULSE_LEN;
1901 startbit_pause_len = MATSUSHITA_START_BIT_PAUSE_LEN - 1;
1902 pulse_1_len = MATSUSHITA_PULSE_LEN;
1903 pause_1_len = MATSUSHITA_1_PAUSE_LEN - 1;
1904 pulse_0_len = MATSUSHITA_PULSE_LEN;
1905 pause_0_len = MATSUSHITA_0_PAUSE_LEN - 1;
1906 has_stop_bit = MATSUSHITA_STOP_BIT;
1907 complete_data_len = MATSUSHITA_COMPLETE_DATA_LEN;
1908 n_auto_repetitions = 1; // 1 frame
1909 auto_repetition_pause_len = 0;
1910 repeat_frame_pause_len = MATSUSHITA_FRAME_REPEAT_PAUSE_LEN;
1911 irsnd_set_freq (IRSND_FREQ_36_KHZ);
1912 break;
1913 }
1914 #endif
1915 #if IRSND_SUPPORT_TECHNICS_PROTOCOL == 1
1916 case IRMP_TECHNICS_PROTOCOL:
1917 {
1918 startbit_pulse_len = MATSUSHITA_START_BIT_PULSE_LEN;
1919 startbit_pause_len = MATSUSHITA_START_BIT_PAUSE_LEN - 1;
1920 pulse_1_len = MATSUSHITA_PULSE_LEN;
1921 pause_1_len = MATSUSHITA_1_PAUSE_LEN - 1;
1922 pulse_0_len = MATSUSHITA_PULSE_LEN;
1923 pause_0_len = MATSUSHITA_0_PAUSE_LEN - 1;
1924 has_stop_bit = MATSUSHITA_STOP_BIT;
1925 complete_data_len = TECHNICS_COMPLETE_DATA_LEN; // here TECHNICS
1926 n_auto_repetitions = 1; // 1 frame
1927 auto_repetition_pause_len = 0;
1928 repeat_frame_pause_len = MATSUSHITA_FRAME_REPEAT_PAUSE_LEN;
1929 irsnd_set_freq (IRSND_FREQ_36_KHZ);
1930 break;
1931 }
1932 #endif
1933 #if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1
1934 case IRMP_KASEIKYO_PROTOCOL:
1935 {
1936 startbit_pulse_len = KASEIKYO_START_BIT_PULSE_LEN;
1937 startbit_pause_len = KASEIKYO_START_BIT_PAUSE_LEN - 1;
1938 pulse_1_len = KASEIKYO_PULSE_LEN;
1939 pause_1_len = KASEIKYO_1_PAUSE_LEN - 1;
1940 pulse_0_len = KASEIKYO_PULSE_LEN;
1941 pause_0_len = KASEIKYO_0_PAUSE_LEN - 1;
1942 has_stop_bit = KASEIKYO_STOP_BIT;
1943 complete_data_len = KASEIKYO_COMPLETE_DATA_LEN;
1944 n_auto_repetitions = (repeat_counter == 0) ? KASEIKYO_FRAMES : 1; // 2 frames auto repetition if first frame
1945 auto_repetition_pause_len = KASEIKYO_AUTO_REPETITION_PAUSE_LEN; // 75 ms pause
1946 repeat_frame_pause_len = KASEIKYO_FRAME_REPEAT_PAUSE_LEN;
1947 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1948 break;
1949 }
1950 #endif
1951 #if IRSND_SUPPORT_PANASONIC_PROTOCOL == 1
1952 case IRMP_PANASONIC_PROTOCOL:
1953 {
1954 startbit_pulse_len = PANASONIC_START_BIT_PULSE_LEN;
1955 startbit_pause_len = PANASONIC_START_BIT_PAUSE_LEN - 1;
1956 pulse_1_len = PANASONIC_PULSE_LEN;
1957 pause_1_len = PANASONIC_1_PAUSE_LEN - 1;
1958 pulse_0_len = PANASONIC_PULSE_LEN;
1959 pause_0_len = PANASONIC_0_PAUSE_LEN - 1;
1960 has_stop_bit = PANASONIC_STOP_BIT;
1961 complete_data_len = PANASONIC_COMPLETE_DATA_LEN;
1962 n_auto_repetitions = PANASONIC_FRAMES; // 1 frame
1963 auto_repetition_pause_len = PANASONIC_AUTO_REPETITION_PAUSE_LEN; // 40 ms pause
1964 repeat_frame_pause_len = PANASONIC_FRAME_REPEAT_PAUSE_LEN;
1965 irsnd_set_freq (IRSND_FREQ_38_KHZ);
1966 break;
1967 }
1968 #endif
1969 #if IRSND_SUPPORT_MITSU_HEAVY_PROTOCOL == 1
1970 case IRMP_MITSU_HEAVY_PROTOCOL:
1971 {
1972 startbit_pulse_len = MITSU_HEAVY_START_BIT_PULSE_LEN;
1973 startbit_pause_len = MITSU_HEAVY_START_BIT_PAUSE_LEN - 1;
1974 pulse_1_len = MITSU_HEAVY_PULSE_LEN;
1975 pause_1_len = MITSU_HEAVY_1_PAUSE_LEN - 1;
1976 pulse_0_len = MITSU_HEAVY_PULSE_LEN;
1977 pause_0_len = MITSU_HEAVY_0_PAUSE_LEN - 1;
1978 has_stop_bit = MITSU_HEAVY_STOP_BIT;
1979 complete_data_len = MITSU_HEAVY_COMPLETE_DATA_LEN;
1980 n_auto_repetitions = MITSU_HEAVY_FRAMES; // 1 frame
1981 auto_repetition_pause_len = 0;;
1982 repeat_frame_pause_len = MITSU_HEAVY_FRAME_REPEAT_PAUSE_LEN;
1983 irsnd_set_freq (IRSND_FREQ_40_KHZ);
1984 break;
1985 }
1986 #endif
1987 #if IRSND_SUPPORT_RECS80_PROTOCOL == 1
1988 case IRMP_RECS80_PROTOCOL:
1989 {
1990 startbit_pulse_len = RECS80_START_BIT_PULSE_LEN;
1991 startbit_pause_len = RECS80_START_BIT_PAUSE_LEN - 1;
1992 pulse_1_len = RECS80_PULSE_LEN;
1993 pause_1_len = RECS80_1_PAUSE_LEN - 1;
1994 pulse_0_len = RECS80_PULSE_LEN;
1995 pause_0_len = RECS80_0_PAUSE_LEN - 1;
1996 has_stop_bit = RECS80_STOP_BIT;
1997 complete_data_len = RECS80_COMPLETE_DATA_LEN;
1998 n_auto_repetitions = 1; // 1 frame
1999 auto_repetition_pause_len = 0;
2000 repeat_frame_pause_len = RECS80_FRAME_REPEAT_PAUSE_LEN;
2001 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2002 break;
2003 }
2004 #endif
2005 #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1
2006 case IRMP_RECS80EXT_PROTOCOL:
2007 {
2008 startbit_pulse_len = RECS80EXT_START_BIT_PULSE_LEN;
2009 startbit_pause_len = RECS80EXT_START_BIT_PAUSE_LEN - 1;
2010 pulse_1_len = RECS80EXT_PULSE_LEN;
2011 pause_1_len = RECS80EXT_1_PAUSE_LEN - 1;
2012 pulse_0_len = RECS80EXT_PULSE_LEN;
2013 pause_0_len = RECS80EXT_0_PAUSE_LEN - 1;
2014 has_stop_bit = RECS80EXT_STOP_BIT;
2015 complete_data_len = RECS80EXT_COMPLETE_DATA_LEN;
2016 n_auto_repetitions = 1; // 1 frame
2017 auto_repetition_pause_len = 0;
2018 repeat_frame_pause_len = RECS80EXT_FRAME_REPEAT_PAUSE_LEN;
2019 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2020 break;
2021 }
2022 #endif
2023 #if IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1
2024 case IRMP_TELEFUNKEN_PROTOCOL:
2025 {
2026 startbit_pulse_len = TELEFUNKEN_START_BIT_PULSE_LEN;
2027 startbit_pause_len = TELEFUNKEN_START_BIT_PAUSE_LEN - 1;
2028 pulse_1_len = TELEFUNKEN_PULSE_LEN;
2029 pause_1_len = TELEFUNKEN_1_PAUSE_LEN - 1;
2030 pulse_0_len = TELEFUNKEN_PULSE_LEN;
2031 pause_0_len = TELEFUNKEN_0_PAUSE_LEN - 1;
2032 has_stop_bit = TELEFUNKEN_STOP_BIT;
2033 complete_data_len = TELEFUNKEN_COMPLETE_DATA_LEN;
2034 n_auto_repetitions = 1; // 1 frames
2035 auto_repetition_pause_len = 0; // TELEFUNKEN_AUTO_REPETITION_PAUSE_LEN; // xx ms pause
2036 repeat_frame_pause_len = TELEFUNKEN_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause
2037 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2038 break;
2039 }
2040 #endif
2041 #if IRSND_SUPPORT_RC5_PROTOCOL == 1
2042 case IRMP_RC5_PROTOCOL:
2043 {
2044 startbit_pulse_len = RC5_BIT_LEN;
2045 startbit_pause_len = RC5_BIT_LEN;
2046 pulse_len = RC5_BIT_LEN;
2047 pause_len = RC5_BIT_LEN;
2048 has_stop_bit = RC5_STOP_BIT;
2049 complete_data_len = RC5_COMPLETE_DATA_LEN;
2050 n_auto_repetitions = 1; // 1 frame
2051 auto_repetition_pause_len = 0;
2052 repeat_frame_pause_len = RC5_FRAME_REPEAT_PAUSE_LEN;
2053 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2054 break;
2055 }
2056 #endif
2057 #if IRSND_SUPPORT_RC6_PROTOCOL == 1
2058 case IRMP_RC6_PROTOCOL:
2059 {
2060 startbit_pulse_len = RC6_START_BIT_PULSE_LEN;
2061 startbit_pause_len = RC6_START_BIT_PAUSE_LEN - 1;
2062 pulse_len = RC6_BIT_LEN;
2063 pause_len = RC6_BIT_LEN;
2064 has_stop_bit = RC6_STOP_BIT;
2065 complete_data_len = RC6_COMPLETE_DATA_LEN_SHORT;
2066 n_auto_repetitions = 1; // 1 frame
2067 auto_repetition_pause_len = 0;
2068 repeat_frame_pause_len = RC6_FRAME_REPEAT_PAUSE_LEN;
2069 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2070 break;
2071 }
2072 #endif
2073 #if IRSND_SUPPORT_RC6A_PROTOCOL == 1
2074 case IRMP_RC6A_PROTOCOL:
2075 {
2076 startbit_pulse_len = RC6_START_BIT_PULSE_LEN;
2077 startbit_pause_len = RC6_START_BIT_PAUSE_LEN - 1;
2078 pulse_len = RC6_BIT_LEN;
2079 pause_len = RC6_BIT_LEN;
2080 has_stop_bit = RC6_STOP_BIT;
2081 complete_data_len = RC6_COMPLETE_DATA_LEN_LONG;
2082 n_auto_repetitions = 1; // 1 frame
2083 auto_repetition_pause_len = 0;
2084 repeat_frame_pause_len = RC6_FRAME_REPEAT_PAUSE_LEN;
2085 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2086 break;
2087 }
2088 #endif
2089 #if IRSND_SUPPORT_DENON_PROTOCOL == 1
2090 case IRMP_DENON_PROTOCOL:
2091 {
2092 startbit_pulse_len = 0x00;
2093 startbit_pause_len = 0x00;
2094 pulse_1_len = DENON_PULSE_LEN;
2095 pause_1_len = DENON_1_PAUSE_LEN - 1;
2096 pulse_0_len = DENON_PULSE_LEN;
2097 pause_0_len = DENON_0_PAUSE_LEN - 1;
2098 has_stop_bit = DENON_STOP_BIT;
2099 complete_data_len = DENON_COMPLETE_DATA_LEN;
2100 n_auto_repetitions = DENON_FRAMES; // 2 frames, 2nd with inverted command
2101 auto_repetition_pause_len = DENON_AUTO_REPETITION_PAUSE_LEN; // 65 ms pause after 1st frame
2102 repeat_frame_pause_len = DENON_FRAME_REPEAT_PAUSE_LEN;
2103 irsnd_set_freq (IRSND_FREQ_36_KHZ); // in theory 32kHz, in practice 36kHz is better
2104 break;
2105 }
2106 #endif
2107 #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1
2108 case IRMP_THOMSON_PROTOCOL:
2109 {
2110 startbit_pulse_len = 0x00;
2111 startbit_pause_len = 0x00;
2112 pulse_1_len = THOMSON_PULSE_LEN;
2113 pause_1_len = THOMSON_1_PAUSE_LEN - 1;
2114 pulse_0_len = THOMSON_PULSE_LEN;
2115 pause_0_len = THOMSON_0_PAUSE_LEN - 1;
2116 has_stop_bit = THOMSON_STOP_BIT;
2117 complete_data_len = THOMSON_COMPLETE_DATA_LEN;
2118 n_auto_repetitions = THOMSON_FRAMES; // only 1 frame
2119 auto_repetition_pause_len = THOMSON_AUTO_REPETITION_PAUSE_LEN;
2120 repeat_frame_pause_len = THOMSON_FRAME_REPEAT_PAUSE_LEN;
2121 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2122 break;
2123 }
2124 #endif
2125 #if IRSND_SUPPORT_BOSE_PROTOCOL == 1
2126 case IRMP_BOSE_PROTOCOL:
2127 {
2128 startbit_pulse_len = BOSE_START_BIT_PULSE_LEN;
2129 startbit_pause_len = BOSE_START_BIT_PAUSE_LEN - 1;
2130 pulse_1_len = BOSE_PULSE_LEN;
2131 pause_1_len = BOSE_1_PAUSE_LEN - 1;
2132 pulse_0_len = BOSE_PULSE_LEN;
2133 pause_0_len = BOSE_0_PAUSE_LEN - 1;
2134 has_stop_bit = BOSE_STOP_BIT;
2135 complete_data_len = BOSE_COMPLETE_DATA_LEN;
2136 n_auto_repetitions = BOSE_FRAMES; // 1 frame
2137 auto_repetition_pause_len = BOSE_AUTO_REPETITION_PAUSE_LEN; // 40 ms pause
2138 repeat_frame_pause_len = BOSE_FRAME_REPEAT_PAUSE_LEN;
2139 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2140 break;
2141 }
2142 #endif
2143 #if IRSND_SUPPORT_NUBERT_PROTOCOL == 1
2144 case IRMP_NUBERT_PROTOCOL:
2145 {
2146 startbit_pulse_len = NUBERT_START_BIT_PULSE_LEN;
2147 startbit_pause_len = NUBERT_START_BIT_PAUSE_LEN - 1;
2148 pulse_1_len = NUBERT_1_PULSE_LEN;
2149 pause_1_len = NUBERT_1_PAUSE_LEN - 1;
2150 pulse_0_len = NUBERT_0_PULSE_LEN;
2151 pause_0_len = NUBERT_0_PAUSE_LEN - 1;
2152 has_stop_bit = NUBERT_STOP_BIT;
2153 complete_data_len = NUBERT_COMPLETE_DATA_LEN;
2154 n_auto_repetitions = NUBERT_FRAMES; // 2 frames
2155 auto_repetition_pause_len = NUBERT_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause
2156 repeat_frame_pause_len = NUBERT_FRAME_REPEAT_PAUSE_LEN;
2157 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2158 break;
2159 }
2160 #endif
2161 #if IRSND_SUPPORT_FAN_PROTOCOL == 1
2162 case IRMP_FAN_PROTOCOL:
2163 {
2164 startbit_pulse_len = FAN_START_BIT_PULSE_LEN;
2165 startbit_pause_len = FAN_START_BIT_PAUSE_LEN - 1;
2166 pulse_1_len = FAN_1_PULSE_LEN;
2167 pause_1_len = FAN_1_PAUSE_LEN - 1;
2168 pulse_0_len = FAN_0_PULSE_LEN;
2169 pause_0_len = FAN_0_PAUSE_LEN - 1;
2170 has_stop_bit = FAN_STOP_BIT;
2171 complete_data_len = FAN_COMPLETE_DATA_LEN;
2172 n_auto_repetitions = FAN_FRAMES; // only 1 frame
2173 auto_repetition_pause_len = FAN_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause
2174 repeat_frame_pause_len = FAN_FRAME_REPEAT_PAUSE_LEN;
2175 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2176 break;
2177 }
2178 #endif
2179 #if IRSND_SUPPORT_SPEAKER_PROTOCOL == 1
2180 case IRMP_SPEAKER_PROTOCOL:
2181 {
2182 startbit_pulse_len = SPEAKER_START_BIT_PULSE_LEN;
2183 startbit_pause_len = SPEAKER_START_BIT_PAUSE_LEN - 1;
2184 pulse_1_len = SPEAKER_1_PULSE_LEN;
2185 pause_1_len = SPEAKER_1_PAUSE_LEN - 1;
2186 pulse_0_len = SPEAKER_0_PULSE_LEN;
2187 pause_0_len = SPEAKER_0_PAUSE_LEN - 1;
2188 has_stop_bit = SPEAKER_STOP_BIT;
2189 complete_data_len = SPEAKER_COMPLETE_DATA_LEN;
2190 n_auto_repetitions = SPEAKER_FRAMES; // 2 frames
2191 auto_repetition_pause_len = SPEAKER_AUTO_REPETITION_PAUSE_LEN; // 35 ms pause
2192 repeat_frame_pause_len = SPEAKER_FRAME_REPEAT_PAUSE_LEN;
2193 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2194 break;
2195 }
2196 #endif
2197 #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1
2198 case IRMP_BANG_OLUFSEN_PROTOCOL:
2199 {
2200 startbit_pulse_len = BANG_OLUFSEN_START_BIT1_PULSE_LEN;
2201 startbit_pause_len = BANG_OLUFSEN_START_BIT1_PAUSE_LEN - 1;
2202 pulse_1_len = BANG_OLUFSEN_PULSE_LEN;
2203 pause_1_len = BANG_OLUFSEN_1_PAUSE_LEN - 1;
2204 pulse_0_len = BANG_OLUFSEN_PULSE_LEN;
2205 pause_0_len = BANG_OLUFSEN_0_PAUSE_LEN - 1;
2206 has_stop_bit = BANG_OLUFSEN_STOP_BIT;
2207 complete_data_len = BANG_OLUFSEN_COMPLETE_DATA_LEN;
2208 n_auto_repetitions = 1; // 1 frame
2209 auto_repetition_pause_len = 0;
2210 repeat_frame_pause_len = BANG_OLUFSEN_FRAME_REPEAT_PAUSE_LEN;
2211 last_bit_value = 0;
2212 irsnd_set_freq (IRSND_FREQ_455_KHZ);
2213 break;
2214 }
2215 #endif
2216 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1
2217 case IRMP_GRUNDIG_PROTOCOL:
2218 {
2219 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2220 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;
2221 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2222 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2223 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;
2224 complete_data_len = GRUNDIG_COMPLETE_DATA_LEN;
2225 n_auto_repetitions = GRUNDIG_FRAMES; // 2 frames
2226 auto_repetition_pause_len = GRUNDIG_AUTO_REPETITION_PAUSE_LEN; // 20m sec pause
2227 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause
2228 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2229 break;
2230 }
2231 #endif
2232 #if IRSND_SUPPORT_IR60_PROTOCOL == 1
2233 case IRMP_IR60_PROTOCOL:
2234 {
2235 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2236 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;
2237 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2238 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2239 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;
2240 complete_data_len = IR60_COMPLETE_DATA_LEN;
2241 n_auto_repetitions = IR60_FRAMES; // 2 frames
2242 auto_repetition_pause_len = IR60_AUTO_REPETITION_PAUSE_LEN; // 20m sec pause
2243 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause
2244 irsnd_set_freq (IRSND_FREQ_30_KHZ);
2245 break;
2246 }
2247 #endif
2248 #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1
2249 case IRMP_NOKIA_PROTOCOL:
2250 {
2251 startbit_pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2252 startbit_pause_len = GRUNDIG_NOKIA_IR60_PRE_PAUSE_LEN - 1;
2253 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2254 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2255 has_stop_bit = GRUNDIG_NOKIA_IR60_STOP_BIT;
2256 complete_data_len = NOKIA_COMPLETE_DATA_LEN;
2257 n_auto_repetitions = NOKIA_FRAMES; // 2 frames
2258 auto_repetition_pause_len = NOKIA_AUTO_REPETITION_PAUSE_LEN; // 20 msec pause
2259 repeat_frame_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN; // 117 msec pause
2260 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2261 break;
2262 }
2263 #endif
2264 #if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1
2265 case IRMP_SIEMENS_PROTOCOL:
2266 {
2267 startbit_pulse_len = SIEMENS_BIT_LEN;
2268 startbit_pause_len = SIEMENS_BIT_LEN;
2269 pulse_len = SIEMENS_BIT_LEN;
2270 pause_len = SIEMENS_BIT_LEN;
2271 has_stop_bit = SIEMENS_OR_RUWIDO_STOP_BIT;
2272 complete_data_len = SIEMENS_COMPLETE_DATA_LEN;
2273 n_auto_repetitions = 1; // 1 frame
2274 auto_repetition_pause_len = 0;
2275 repeat_frame_pause_len = SIEMENS_FRAME_REPEAT_PAUSE_LEN;
2276 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2277 break;
2278 }
2279 #endif
2280 #if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1
2281 case IRMP_RUWIDO_PROTOCOL:
2282 {
2283 startbit_pulse_len = RUWIDO_START_BIT_PULSE_LEN;
2284 startbit_pause_len = RUWIDO_START_BIT_PAUSE_LEN;
2285 pulse_len = RUWIDO_BIT_PULSE_LEN;
2286 pause_len = RUWIDO_BIT_PAUSE_LEN;
2287 has_stop_bit = SIEMENS_OR_RUWIDO_STOP_BIT;
2288 complete_data_len = RUWIDO_COMPLETE_DATA_LEN;
2289 n_auto_repetitions = 1; // 1 frame
2290 auto_repetition_pause_len = 0;
2291 repeat_frame_pause_len = RUWIDO_FRAME_REPEAT_PAUSE_LEN;
2292 irsnd_set_freq (IRSND_FREQ_36_KHZ);
2293 break;
2294 }
2295 #endif
2296 #if IRSND_SUPPORT_FDC_PROTOCOL == 1
2297 case IRMP_FDC_PROTOCOL:
2298 {
2299 startbit_pulse_len = FDC_START_BIT_PULSE_LEN;
2300 startbit_pause_len = FDC_START_BIT_PAUSE_LEN - 1;
2301 complete_data_len = FDC_COMPLETE_DATA_LEN;
2302 pulse_1_len = FDC_PULSE_LEN;
2303 pause_1_len = FDC_1_PAUSE_LEN - 1;
2304 pulse_0_len = FDC_PULSE_LEN;
2305 pause_0_len = FDC_0_PAUSE_LEN - 1;
2306 has_stop_bit = FDC_STOP_BIT;
2307 n_auto_repetitions = 1; // 1 frame
2308 auto_repetition_pause_len = 0;
2309 repeat_frame_pause_len = FDC_FRAME_REPEAT_PAUSE_LEN;
2310 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2311 break;
2312 }
2313 #endif
2314 #if IRSND_SUPPORT_RCCAR_PROTOCOL == 1
2315 case IRMP_RCCAR_PROTOCOL:
2316 {
2317 startbit_pulse_len = RCCAR_START_BIT_PULSE_LEN;
2318 startbit_pause_len = RCCAR_START_BIT_PAUSE_LEN - 1;
2319 complete_data_len = RCCAR_COMPLETE_DATA_LEN;
2320 pulse_1_len = RCCAR_PULSE_LEN;
2321 pause_1_len = RCCAR_1_PAUSE_LEN - 1;
2322 pulse_0_len = RCCAR_PULSE_LEN;
2323 pause_0_len = RCCAR_0_PAUSE_LEN - 1;
2324 has_stop_bit = RCCAR_STOP_BIT;
2325 n_auto_repetitions = 1; // 1 frame
2326 auto_repetition_pause_len = 0;
2327 repeat_frame_pause_len = RCCAR_FRAME_REPEAT_PAUSE_LEN;
2328 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2329 break;
2330 }
2331 #endif
2332 #if IRSND_SUPPORT_JVC_PROTOCOL == 1
2333 case IRMP_JVC_PROTOCOL:
2334 {
2335 if (repeat_counter != 0) // skip start bit if repetition frame
2336 {
2337 current_bit = 0;
2338 }
2339
2340 startbit_pulse_len = JVC_START_BIT_PULSE_LEN;
2341 startbit_pause_len = JVC_START_BIT_PAUSE_LEN - 1;
2342 complete_data_len = JVC_COMPLETE_DATA_LEN;
2343 pulse_1_len = JVC_PULSE_LEN;
2344 pause_1_len = JVC_1_PAUSE_LEN - 1;
2345 pulse_0_len = JVC_PULSE_LEN;
2346 pause_0_len = JVC_0_PAUSE_LEN - 1;
2347 has_stop_bit = JVC_STOP_BIT;
2348 n_auto_repetitions = 1; // 1 frame
2349 auto_repetition_pause_len = 0;
2350 repeat_frame_pause_len = JVC_FRAME_REPEAT_PAUSE_LEN;
2351 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2352 break;
2353 }
2354 #endif
2355 #if IRSND_SUPPORT_NIKON_PROTOCOL == 1
2356 case IRMP_NIKON_PROTOCOL:
2357 {
2358 startbit_pulse_len = NIKON_START_BIT_PULSE_LEN;
2359 startbit_pause_len = NIKON_START_BIT_PAUSE_LEN;
2360 complete_data_len = NIKON_COMPLETE_DATA_LEN;
2361 pulse_1_len = NIKON_PULSE_LEN;
2362 pause_1_len = NIKON_1_PAUSE_LEN - 1;
2363 pulse_0_len = NIKON_PULSE_LEN;
2364 pause_0_len = NIKON_0_PAUSE_LEN - 1;
2365 has_stop_bit = NIKON_STOP_BIT;
2366 n_auto_repetitions = 1; // 1 frame
2367 auto_repetition_pause_len = 0;
2368 repeat_frame_pause_len = NIKON_FRAME_REPEAT_PAUSE_LEN;
2369 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2370 break;
2371 }
2372 #endif
2373 #if IRSND_SUPPORT_LEGO_PROTOCOL == 1
2374 case IRMP_LEGO_PROTOCOL:
2375 {
2376 startbit_pulse_len = LEGO_START_BIT_PULSE_LEN;
2377 startbit_pause_len = LEGO_START_BIT_PAUSE_LEN - 1;
2378 complete_data_len = LEGO_COMPLETE_DATA_LEN;
2379 pulse_1_len = LEGO_PULSE_LEN;
2380 pause_1_len = LEGO_1_PAUSE_LEN - 1;
2381 pulse_0_len = LEGO_PULSE_LEN;
2382 pause_0_len = LEGO_0_PAUSE_LEN - 1;
2383 has_stop_bit = LEGO_STOP_BIT;
2384 n_auto_repetitions = 1; // 1 frame
2385 auto_repetition_pause_len = 0;
2386 repeat_frame_pause_len = LEGO_FRAME_REPEAT_PAUSE_LEN;
2387 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2388 break;
2389 }
2390 #endif
2391 #if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1
2392 case IRMP_A1TVBOX_PROTOCOL:
2393 {
2394 startbit_pulse_len = A1TVBOX_BIT_PULSE_LEN; // don't use A1TVBOX_START_BIT_PULSE_LEN
2395 startbit_pause_len = A1TVBOX_BIT_PAUSE_LEN; // don't use A1TVBOX_START_BIT_PAUSE_LEN
2396 pulse_len = A1TVBOX_BIT_PULSE_LEN;
2397 pause_len = A1TVBOX_BIT_PAUSE_LEN;
2398 has_stop_bit = A1TVBOX_STOP_BIT;
2399 complete_data_len = A1TVBOX_COMPLETE_DATA_LEN + 1; // we send stop bit as data
2400 n_auto_repetitions = 1; // 1 frame
2401 auto_repetition_pause_len = 0;
2402 repeat_frame_pause_len = A1TVBOX_FRAME_REPEAT_PAUSE_LEN;
2403 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2404 break;
2405 }
2406 #endif
2407 #if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1
2408 case IRMP_ROOMBA_PROTOCOL:
2409 {
2410 startbit_pulse_len = ROOMBA_START_BIT_PULSE_LEN;
2411 startbit_pause_len = ROOMBA_START_BIT_PAUSE_LEN;
2412 pulse_1_len = ROOMBA_1_PULSE_LEN;
2413 pause_1_len = ROOMBA_1_PAUSE_LEN - 1;
2414 pulse_0_len = ROOMBA_0_PULSE_LEN;
2415 pause_0_len = ROOMBA_0_PAUSE_LEN - 1;
2416 has_stop_bit = ROOMBA_STOP_BIT;
2417 complete_data_len = ROOMBA_COMPLETE_DATA_LEN;
2418 n_auto_repetitions = ROOMBA_FRAMES; // 8 frames
2419 auto_repetition_pause_len = ROOMBA_FRAME_REPEAT_PAUSE_LEN;
2420 repeat_frame_pause_len = ROOMBA_FRAME_REPEAT_PAUSE_LEN;
2421 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2422 break;
2423 }
2424 #endif
2425 #if IRSND_SUPPORT_PENTAX_PROTOCOL == 1
2426 case IRMP_PENTAX_PROTOCOL:
2427 {
2428 startbit_pulse_len = PENTAX_START_BIT_PULSE_LEN;
2429 startbit_pause_len = PENTAX_START_BIT_PAUSE_LEN;
2430 complete_data_len = PENTAX_COMPLETE_DATA_LEN;
2431 pulse_1_len = PENTAX_PULSE_LEN;
2432 pause_1_len = PENTAX_1_PAUSE_LEN - 1;
2433 pulse_0_len = PENTAX_PULSE_LEN;
2434 pause_0_len = PENTAX_0_PAUSE_LEN - 1;
2435 has_stop_bit = PENTAX_STOP_BIT;
2436 n_auto_repetitions = 1; // 1 frame
2437 auto_repetition_pause_len = 0;
2438 repeat_frame_pause_len = PENTAX_FRAME_REPEAT_PAUSE_LEN;
2439 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2440 break;
2441 }
2442 #endif
2443 #if IRSND_SUPPORT_ACP24_PROTOCOL == 1
2444 case IRMP_ACP24_PROTOCOL:
2445 {
2446 startbit_pulse_len = ACP24_START_BIT_PULSE_LEN;
2447 startbit_pause_len = ACP24_START_BIT_PAUSE_LEN - 1;
2448 complete_data_len = ACP24_COMPLETE_DATA_LEN;
2449 pulse_1_len = ACP24_PULSE_LEN;
2450 pause_1_len = ACP24_1_PAUSE_LEN - 1;
2451 pulse_0_len = ACP24_PULSE_LEN;
2452 pause_0_len = ACP24_0_PAUSE_LEN - 1;
2453 has_stop_bit = ACP24_STOP_BIT;
2454 n_auto_repetitions = 1; // 1 frame
2455 auto_repetition_pause_len = 0;
2456 repeat_frame_pause_len = ACP24_FRAME_REPEAT_PAUSE_LEN;
2457 irsnd_set_freq (IRSND_FREQ_38_KHZ);
2458 break;
2459 }
2460 #endif
2461 default:
2462 {
2463 irsnd_busy = FALSE;
2464 break;
2465 }
2466 }
2467 }
2468 }
2469
2470 if (irsnd_busy)
2471 {
2472 new_frame = FALSE;
2473
2474 switch (irsnd_protocol)
2475 {
2476 #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1
2477 case IRMP_SIRCS_PROTOCOL:
2478 #endif
2479 #if IRSND_SUPPORT_NEC_PROTOCOL == 1
2480 case IRMP_NEC_PROTOCOL:
2481 #endif
2482 #if IRSND_SUPPORT_NEC16_PROTOCOL == 1
2483 case IRMP_NEC16_PROTOCOL:
2484 #endif
2485 #if IRSND_SUPPORT_NEC42_PROTOCOL == 1
2486 case IRMP_NEC42_PROTOCOL:
2487 #endif
2488 #if IRSND_SUPPORT_LGAIR_PROTOCOL == 1
2489 case IRMP_LGAIR_PROTOCOL:
2490 #endif
2491 #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1
2492 case IRMP_SAMSUNG_PROTOCOL:
2493 case IRMP_SAMSUNG32_PROTOCOL:
2494 #endif
2495 #if IRSND_SUPPORT_SAMSUNG48_PROTOCOL == 1
2496 case IRMP_SAMSUNG48_PROTOCOL:
2497 #endif
2498 #if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1
2499 case IRMP_MATSUSHITA_PROTOCOL:
2500 #endif
2501 #if IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1
2502 case IRMP_TECHNICS_PROTOCOL:
2503 #endif
2504 #if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1
2505 case IRMP_KASEIKYO_PROTOCOL:
2506 #endif
2507 #if IRSND_SUPPORT_PANASONIC_PROTOCOL == 1
2508 case IRMP_PANASONIC_PROTOCOL:
2509 #endif
2510 #if IRSND_SUPPORT_MITSU_HEAVY_PROTOCOL == 1
2511 case IRMP_MITSU_HEAVY_PROTOCOL:
2512 #endif
2513 #if IRSND_SUPPORT_RECS80_PROTOCOL == 1
2514 case IRMP_RECS80_PROTOCOL:
2515 #endif
2516 #if IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1
2517 case IRMP_RECS80EXT_PROTOCOL:
2518 #endif
2519 #if IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1
2520 case IRMP_TELEFUNKEN_PROTOCOL:
2521 #endif
2522 #if IRSND_SUPPORT_DENON_PROTOCOL == 1
2523 case IRMP_DENON_PROTOCOL:
2524 #endif
2525 #if IRSND_SUPPORT_BOSE_PROTOCOL == 1
2526 case IRMP_BOSE_PROTOCOL:
2527 #endif
2528 #if IRSND_SUPPORT_NUBERT_PROTOCOL == 1
2529 case IRMP_NUBERT_PROTOCOL:
2530 #endif
2531 #if IRSND_SUPPORT_FAN_PROTOCOL == 1
2532 case IRMP_FAN_PROTOCOL:
2533 #endif
2534 #if IRSND_SUPPORT_SPEAKER_PROTOCOL == 1
2535 case IRMP_SPEAKER_PROTOCOL:
2536 #endif
2537 #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1
2538 case IRMP_BANG_OLUFSEN_PROTOCOL:
2539 #endif
2540 #if IRSND_SUPPORT_FDC_PROTOCOL == 1
2541 case IRMP_FDC_PROTOCOL:
2542 #endif
2543 #if IRSND_SUPPORT_RCCAR_PROTOCOL == 1
2544 case IRMP_RCCAR_PROTOCOL:
2545 #endif
2546 #if IRSND_SUPPORT_JVC_PROTOCOL == 1
2547 case IRMP_JVC_PROTOCOL:
2548 #endif
2549 #if IRSND_SUPPORT_NIKON_PROTOCOL == 1
2550 case IRMP_NIKON_PROTOCOL:
2551 #endif
2552 #if IRSND_SUPPORT_LEGO_PROTOCOL == 1
2553 case IRMP_LEGO_PROTOCOL:
2554 #endif
2555 #if IRSND_SUPPORT_THOMSON_PROTOCOL == 1
2556 case IRMP_THOMSON_PROTOCOL:
2557 #endif
2558 #if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1
2559 case IRMP_ROOMBA_PROTOCOL:
2560 #endif
2561 #if IRSND_SUPPORT_PENTAX_PROTOCOL == 1
2562 case IRMP_PENTAX_PROTOCOL:
2563 #endif
2564 #if IRSND_SUPPORT_ACP24_PROTOCOL == 1
2565 case IRMP_ACP24_PROTOCOL:
2566 #endif
2567
2568 #if IRSND_SUPPORT_SIRCS_PROTOCOL == 1 || IRSND_SUPPORT_NEC_PROTOCOL == 1 || IRSND_SUPPORT_NEC16_PROTOCOL == 1 || IRSND_SUPPORT_NEC42_PROTOCOL == 1 || \
2569 IRSND_SUPPORT_LGAIR_PROTOCOL == 1 || IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1 || IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1 || IRSND_SUPPORT_TECHNICS_PROTOCOL == 1 || \
2570 IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1 || IRSND_SUPPORT_RECS80_PROTOCOL == 1 || IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1 || IRSND_SUPPORT_DENON_PROTOCOL == 1 || \
2571 IRSND_SUPPORT_NUBERT_PROTOCOL == 1 || IRSND_SUPPORT_FAN_PROTOCOL == 1 || IRSND_SUPPORT_SPEAKER_PROTOCOL == 1 || IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1 || \
2572 IRSND_SUPPORT_FDC_PROTOCOL == 1 || IRSND_SUPPORT_RCCAR_PROTOCOL == 1 || IRSND_SUPPORT_JVC_PROTOCOL == 1 || IRSND_SUPPORT_NIKON_PROTOCOL == 1 || \
2573 IRSND_SUPPORT_LEGO_PROTOCOL == 1 || IRSND_SUPPORT_THOMSON_PROTOCOL == 1 || IRSND_SUPPORT_ROOMBA_PROTOCOL == 1 || IRSND_SUPPORT_TELEFUNKEN_PROTOCOL == 1 || \
2574 IRSND_SUPPORT_PENTAX_PROTOCOL == 1 || IRSND_SUPPORT_ACP24_PROTOCOL == 1 || IRSND_SUPPORT_PANASONIC_PROTOCOL == 1 || IRSND_SUPPORT_BOSE_PROTOCOL == 1 || \
2575 IRSND_SUPPORT_MITSU_HEAVY_PROTOCOL == 1
2576 {
2577 if (pulse_counter == 0)
2578 {
2579 if (current_bit == 0xFF) // send start bit
2580 {
2581 pulse_len = startbit_pulse_len;
2582 pause_len = startbit_pause_len;
2583 }
2584 else if (current_bit < complete_data_len) // send n'th bit
2585 {
2586 #if IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1
2587 if (irsnd_protocol == IRMP_SAMSUNG_PROTOCOL)
2588 {
2589 if (current_bit < SAMSUNG_ADDRESS_LEN) // send address bits
2590 {
2591 pulse_len = SAMSUNG_PULSE_LEN;
2592 pause_len = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ?
2593 (SAMSUNG_1_PAUSE_LEN - 1) : (SAMSUNG_0_PAUSE_LEN - 1);
2594 }
2595 else if (current_bit == SAMSUNG_ADDRESS_LEN) // send SYNC bit (16th bit)
2596 {
2597 pulse_len = SAMSUNG_PULSE_LEN;
2598 pause_len = SAMSUNG_START_BIT_PAUSE_LEN - 1;
2599 }
2600 else if (current_bit < SAMSUNG_COMPLETE_DATA_LEN) // send n'th bit
2601 {
2602 uint8_t cur_bit = current_bit - 1; // sync skipped, offset = -1 !
2603
2604 pulse_len = SAMSUNG_PULSE_LEN;
2605 pause_len = (irsnd_buffer[cur_bit >> 3] & (1<<(7-(cur_bit & 7)))) ?
2606 (SAMSUNG_1_PAUSE_LEN - 1) : (SAMSUNG_0_PAUSE_LEN - 1);
2607 }
2608 }
2609 else
2610 #endif
2611
2612 #if IRSND_SUPPORT_NEC16_PROTOCOL == 1
2613 if (irsnd_protocol == IRMP_NEC16_PROTOCOL)
2614 {
2615 if (current_bit < NEC16_ADDRESS_LEN) // send address bits
2616 {
2617 pulse_len = NEC_PULSE_LEN;
2618 pause_len = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ?
2619 (NEC_1_PAUSE_LEN - 1) : (NEC_0_PAUSE_LEN - 1);
2620 }
2621 else if (current_bit == NEC16_ADDRESS_LEN) // send SYNC bit (8th bit)
2622 {
2623 pulse_len = NEC_PULSE_LEN;
2624 pause_len = NEC_START_BIT_PAUSE_LEN - 1;
2625 }
2626 else if (current_bit < NEC16_COMPLETE_DATA_LEN + 1) // send n'th bit
2627 {
2628 uint8_t cur_bit = current_bit - 1; // sync skipped, offset = -1 !
2629
2630 pulse_len = NEC_PULSE_LEN;
2631 pause_len = (irsnd_buffer[cur_bit >> 3] & (1<<(7-(cur_bit & 7)))) ?
2632 (NEC_1_PAUSE_LEN - 1) : (NEC_0_PAUSE_LEN - 1);
2633 }
2634 }
2635 else
2636 #endif
2637
2638 #if IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1
2639 if (irsnd_protocol == IRMP_BANG_OLUFSEN_PROTOCOL)
2640 {
2641 if (current_bit == 0) // send 2nd start bit
2642 {
2643 pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;
2644 pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN - 1;
2645 }
2646 else if (current_bit == 1) // send 3rd start bit
2647 {
2648 pulse_len = BANG_OLUFSEN_START_BIT3_PULSE_LEN;
2649 pause_len = BANG_OLUFSEN_START_BIT3_PAUSE_LEN - 1;
2650 }
2651 else if (current_bit == 2) // send 4th start bit
2652 {
2653 pulse_len = BANG_OLUFSEN_START_BIT2_PULSE_LEN;
2654 pause_len = BANG_OLUFSEN_START_BIT2_PAUSE_LEN - 1;
2655 }
2656 else if (current_bit == 19) // send trailer bit
2657 {
2658 pulse_len = BANG_OLUFSEN_PULSE_LEN;
2659 pause_len = BANG_OLUFSEN_TRAILER_BIT_PAUSE_LEN - 1;
2660 }
2661 else if (current_bit < BANG_OLUFSEN_COMPLETE_DATA_LEN) // send n'th bit
2662 {
2663 uint8_t cur_bit_value = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ? 1 : 0;
2664 pulse_len = BANG_OLUFSEN_PULSE_LEN;
2665
2666 if (cur_bit_value == last_bit_value)
2667 {
2668 pause_len = BANG_OLUFSEN_R_PAUSE_LEN - 1;
2669 }
2670 else
2671 {
2672 pause_len = cur_bit_value ? (BANG_OLUFSEN_1_PAUSE_LEN - 1) : (BANG_OLUFSEN_0_PAUSE_LEN - 1);
2673 last_bit_value = cur_bit_value;
2674 }
2675 }
2676 }
2677 else
2678 #endif
2679 if (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7))))
2680 {
2681 pulse_len = pulse_1_len;
2682 pause_len = pause_1_len;
2683 }
2684 else
2685 {
2686 pulse_len = pulse_0_len;
2687 pause_len = pause_0_len;
2688 }
2689 }
2690 else if (has_stop_bit) // send stop bit
2691 {
2692 pulse_len = pulse_0_len;
2693
2694 if (auto_repetition_counter < n_auto_repetitions)
2695 {
2696 pause_len = pause_0_len;
2697 }
2698 else
2699 {
2700 pause_len = 255; // last frame: pause of 255
2701 }
2702 }
2703 }
2704
2705 if (pulse_counter < pulse_len)
2706 {
2707 if (pulse_counter == 0)
2708 {
2709 irsnd_on ();
2710 }
2711 pulse_counter++;
2712 }
2713 else if (pause_counter < pause_len)
2714 {
2715 if (pause_counter == 0)
2716 {
2717 irsnd_off ();
2718 }
2719 pause_counter++;
2720 }
2721 else
2722 {
2723 current_bit++;
2724
2725 if (current_bit >= complete_data_len + has_stop_bit)
2726 {
2727 current_bit = 0xFF;
2728 auto_repetition_counter++;
2729
2730 if (auto_repetition_counter == n_auto_repetitions)
2731 {
2732 irsnd_busy = FALSE;
2733 auto_repetition_counter = 0;
2734 }
2735 new_frame = TRUE;
2736 }
2737
2738 pulse_counter = 0;
2739 pause_counter = 0;
2740 }
2741 break;
2742 }
2743 #endif
2744
2745 #if IRSND_SUPPORT_RC5_PROTOCOL == 1
2746 case IRMP_RC5_PROTOCOL:
2747 #endif
2748 #if IRSND_SUPPORT_RC6_PROTOCOL == 1
2749 case IRMP_RC6_PROTOCOL:
2750 #endif
2751 #if IRSND_SUPPORT_RC6A_PROTOCOL == 1
2752 case IRMP_RC6A_PROTOCOL:
2753 #endif
2754 #if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1
2755 case IRMP_SIEMENS_PROTOCOL:
2756 #endif
2757 #if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1
2758 case IRMP_RUWIDO_PROTOCOL:
2759 #endif
2760 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1
2761 case IRMP_GRUNDIG_PROTOCOL:
2762 #endif
2763 #if IRSND_SUPPORT_IR60_PROTOCOL == 1
2764 case IRMP_IR60_PROTOCOL:
2765 #endif
2766 #if IRSND_SUPPORT_NOKIA_PROTOCOL == 1
2767 case IRMP_NOKIA_PROTOCOL:
2768 #endif
2769 #if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1
2770 case IRMP_A1TVBOX_PROTOCOL:
2771 #endif
2772
2773 #if IRSND_SUPPORT_RC5_PROTOCOL == 1 || \
2774 IRSND_SUPPORT_RC6_PROTOCOL == 1 || \
2775 IRSND_SUPPORT_RC6A_PROTOCOL == 1 || \
2776 IRSND_SUPPORT_RUWIDO_PROTOCOL == 1 || \
2777 IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 || \
2778 IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || \
2779 IRSND_SUPPORT_IR60_PROTOCOL == 1 || \
2780 IRSND_SUPPORT_NOKIA_PROTOCOL == 1 || \
2781 IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1
2782 {
2783 if (pulse_counter == pulse_len && pause_counter == pause_len)
2784 {
2785 current_bit++;
2786
2787 if (current_bit >= complete_data_len)
2788 {
2789 current_bit = 0xFF;
2790
2791 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1
2792 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL || irsnd_protocol == IRMP_IR60_PROTOCOL || irsnd_protocol == IRMP_NOKIA_PROTOCOL)
2793 {
2794 auto_repetition_counter++;
2795
2796 if (repeat_counter > 0)
2797 { // set 117 msec pause time
2798 auto_repetition_pause_len = GRUNDIG_NOKIA_IR60_FRAME_REPEAT_PAUSE_LEN;
2799 }
2800
2801 if (repeat_counter < n_repeat_frames) // tricky: repeat n info frames per auto repetition before sending last stop frame
2802 {
2803 n_auto_repetitions++; // increment number of auto repetitions
2804 repeat_counter++;
2805 }
2806 else if (auto_repetition_counter == n_auto_repetitions)
2807 {
2808 irsnd_busy = FALSE;
2809 auto_repetition_counter = 0;
2810 }
2811 }
2812 else
2813 #endif
2814 {
2815 irsnd_busy = FALSE;
2816 }
2817
2818 new_frame = TRUE;
2819 irsnd_off ();
2820 }
2821
2822 pulse_counter = 0;
2823 pause_counter = 0;
2824 }
2825
2826 if (! new_frame)
2827 {
2828 uint8_t first_pulse;
2829
2830 #if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1
2831 if (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL || irsnd_protocol == IRMP_IR60_PROTOCOL || irsnd_protocol == IRMP_NOKIA_PROTOCOL)
2832 {
2833 if (current_bit == 0xFF || // start bit of start-frame
2834 (irsnd_protocol == IRMP_GRUNDIG_PROTOCOL && current_bit == 15) || // start bit of info-frame (Grundig)
2835 (irsnd_protocol == IRMP_IR60_PROTOCOL && current_bit == 7) || // start bit of data frame (IR60)
2836 (irsnd_protocol == IRMP_NOKIA_PROTOCOL && (current_bit == 23 || current_bit == 47))) // start bit of info- or stop-frame (Nokia)
2837 {
2838 pulse_len = startbit_pulse_len;
2839 pause_len = startbit_pause_len;
2840 first_pulse = TRUE;
2841 }
2842 else // send n'th bit
2843 {
2844 pulse_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2845 pause_len = GRUNDIG_NOKIA_IR60_BIT_LEN;
2846 first_pulse = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ? TRUE : FALSE;
2847 }
2848 }
2849 else // if (irsnd_protocol == IRMP_RC5_PROTOCOL || irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL ||
2850 // irsnd_protocol == IRMP_SIEMENS_PROTOCOL || irsnd_protocol == IRMP_RUWIDO_PROTOCOL)
2851 #endif
2852 {
2853 if (current_bit == 0xFF) // 1 start bit
2854 {
2855 #if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1
2856 if (irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL)
2857 {
2858 pulse_len = startbit_pulse_len;
2859 pause_len = startbit_pause_len;
2860 }
2861 else
2862 #endif
2863 #if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1
2864 if (irsnd_protocol == IRMP_A1TVBOX_PROTOCOL)
2865 {
2866 current_bit = 0;
2867 }
2868 else
2869 #endif
2870 {
2871 ;
2872 }
2873
2874 first_pulse = TRUE;
2875 }
2876 else // send n'th bit
2877 {
2878 #if IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1
2879 if (irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL)
2880 {
2881 pulse_len = RC6_BIT_LEN;
2882 pause_len = RC6_BIT_LEN;
2883
2884 if (irsnd_protocol == IRMP_RC6_PROTOCOL)
2885 {
2886 if (current_bit == 4) // toggle bit (double len)
2887 {
2888 pulse_len = RC6_BIT_2_LEN; // = 2 * RC_BIT_LEN
2889 pause_len = RC6_BIT_2_LEN; // = 2 * RC_BIT_LEN
2890 }
2891 }
2892 else // if (irsnd_protocol == IRMP_RC6A_PROTOCOL)
2893 {
2894 if (current_bit == 4) // toggle bit (double len)
2895 {
2896 pulse_len = RC6_BIT_3_LEN; // = 3 * RC6_BIT_LEN
2897 pause_len = RC6_BIT_2_LEN; // = 2 * RC6_BIT_LEN
2898 }
2899 else if (current_bit == 5) // toggle bit (double len)
2900 {
2901 pause_len = RC6_BIT_2_LEN; // = 2 * RC6_BIT_LEN
2902 }
2903 }
2904 }
2905 #endif
2906 first_pulse = (irsnd_buffer[current_bit >> 3] & (1<<(7-(current_bit & 7)))) ? TRUE : FALSE;
2907 }
2908
2909 if (irsnd_protocol == IRMP_RC5_PROTOCOL)
2910 {
2911 first_pulse = first_pulse ? FALSE : TRUE;
2912 }
2913 }
2914
2915 if (first_pulse)
2916 {
2917 // printf ("first_pulse: current_bit: %d %d < %d %d < %d\n", current_bit, pause_counter, pause_len, pulse_counter, pulse_len);
2918
2919 if (pulse_counter < pulse_len)
2920 {
2921 if (pulse_counter == 0)
2922 {
2923 irsnd_on ();
2924 }
2925 pulse_counter++;
2926 }
2927 else // if (pause_counter < pause_len)
2928 {
2929 if (pause_counter == 0)
2930 {
2931 irsnd_off ();
2932 }
2933 pause_counter++;
2934 }
2935 }
2936 else
2937 {
2938 // printf ("first_pause: current_bit: %d %d < %d %d < %d\n", current_bit, pause_counter, pause_len, pulse_counter, pulse_len);
2939
2940 if (pause_counter < pause_len)
2941 {
2942 if (pause_counter == 0)
2943 {
2944 irsnd_off ();
2945 }
2946 pause_counter++;
2947 }
2948 else // if (pulse_counter < pulse_len)
2949 {
2950 if (pulse_counter == 0)
2951 {
2952 irsnd_on ();
2953 }
2954 pulse_counter++;
2955 }
2956 }
2957 }
2958 break;
2959 }
2960 #endif // IRSND_SUPPORT_RC5_PROTOCOL == 1 || IRSND_SUPPORT_RC6_PROTOCOL == 1 || || IRSND_SUPPORT_RC6A_PROTOCOL == 1 || IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 ||
2961 // IRSND_SUPPORT_RUWIDO_PROTOCOL == 1 || IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1
2962
2963 default:
2964 {
2965 irsnd_busy = FALSE;
2966 break;
2967 }
2968 }
2969 }
2970
2971 if (! irsnd_busy)
2972 {
2973 if (repeat_counter < n_repeat_frames)
2974 {
2975 #if IRSND_SUPPORT_FDC_PROTOCOL == 1
2976 if (irsnd_protocol == IRMP_FDC_PROTOCOL)
2977 {
2978 irsnd_buffer[2] |= 0x0F;
2979 }
2980 #endif
2981 repeat_counter++;
2982 irsnd_busy = TRUE;
2983 }
2984 else
2985 {
2986 irsnd_busy = TRUE; //Rainer
2987 send_trailer = TRUE;
2988 n_repeat_frames = 0;
2989 repeat_counter = 0;
2990 }
2991 }
2992 }
2993
2994 #ifdef ANALYZE
2995 if (irsnd_is_on)
2996 {
2997 putchar ('0');
2998 }
2999 else
3000 {
3001 putchar ('1');
3002 }
3003 #endif
3004
3005 return irsnd_busy;
3006 }
3007
3008 #ifdef ANALYZE
3009
3010 // main function - for unix/linux + windows only!
3011 // AVR: see main.c!
3012 // Compile it under linux with:
3013 // cc irsnd.c -o irsnd
3014 //
3015 // usage: ./irsnd protocol hex-address hex-command >filename
3016
3017 int
3018 main (int argc, char ** argv)
3019 {
3020 int protocol;
3021 int address;
3022 int command;
3023 IRMP_DATA irmp_data;
3024
3025 if (argc != 4 && argc != 5)
3026 {
3027 fprintf (stderr, "usage: %s protocol hex-address hex-command [repeat] > filename\n", argv[0]);
3028 return 1;
3029 }
3030
3031 if (sscanf (argv[1], "%d", &protocol) == 1 &&
3032 sscanf (argv[2], "%x", &address) == 1 &&
3033 sscanf (argv[3], "%x", &command) == 1)
3034 {
3035 irmp_data.protocol = protocol;
3036 irmp_data.address = address;
3037 irmp_data.command = command;
3038
3039 if (argc == 5)
3040 {
3041 irmp_data.flags = atoi (argv[4]);
3042 }
3043 else
3044 {
3045 irmp_data.flags = 0;
3046 }
3047
3048 irsnd_init ();
3049
3050 (void) irsnd_send_data (&irmp_data, TRUE);
3051
3052 while (irsnd_busy)
3053 {
3054 irsnd_ISR ();
3055 }
3056
3057 putchar ('\n');
3058
3059 #if 1 // enable here to send twice
3060 (void) irsnd_send_data (&irmp_data, TRUE);
3061
3062 while (irsnd_busy)
3063 {
3064 irsnd_ISR ();
3065 }
3066
3067 putchar ('\n');
3068 #endif
3069 }
3070 else
3071 {
3072 fprintf (stderr, "%s: wrong arguments\n", argv[0]);
3073 return 1;
3074 }
3075 return 0;
3076 }
3077
3078 #endif // ANALYZE
Clone of IRMP - Infrared Muliti Protocol Decoder (https://www.mikrocontroller.net/articles/IRMP)