/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
* @file irsnd.c\r
*\r
- * Copyright (c) 2010-2012 Frank Meyer - frank(at)fli4l.de\r
+ * Copyright (c) 2010-2013 Frank Meyer - frank(at)fli4l.de\r
*\r
* Supported mikrocontrollers:\r
*\r
+ * ATtiny87, ATtiny167\r
* ATtiny45, ATtiny85\r
- * ATtiny84\r
+ * ATtiny44 ATtiny84\r
* ATmega8, ATmega16, ATmega32\r
* ATmega162\r
- * ATmega164, ATmega324, ATmega644, ATmega644P, ATmega1284\r
+ * ATmega164, ATmega324, ATmega644, ATmega644P, ATmega1284, ATmega1284P\r
* ATmega88, ATmega88P, ATmega168, ATmega168P, ATmega328P\r
*\r
- * $Id: irsnd.c,v 1.54 2012/05/23 12:26:26 fm Exp $\r
+ * $Id: irsnd.c,v 1.73 2014/05/19 18:55:43 fm Exp $\r
*\r
* This program is free software; you can redistribute it and/or modify\r
* it under the terms of the GNU General Public License as published by\r
\r
#include "irsnd.h"\r
\r
+#ifndef F_CPU\r
+# error F_CPU unkown\r
+#endif\r
+\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
* ATtiny pin definition of OC0A / OC0B\r
* ATmega pin definition of OC2 / OC2A / OC2B / OC0 / OC0A / OC0B\r
*---------------------------------------------------------------------------------------------------------------------------------------------------\r
*/\r
-#if defined (__AVR_ATtiny84__) // ATtiny84 uses OC0A = PB2 or OC0B = PA7\r
+#if defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) // ATtiny44/84 uses OC0A = PB2 or OC0B = PA7\r
# if IRSND_OCx == IRSND_OC0A // OC0A\r
-# define IRSND_PORT PORTB // port B\r
-# define IRSND_DDR DDRB // ddr B\r
-# define IRSND_BIT 2 // OC0A\r
+# define IRSND_PORT_LETTER B\r
+# define IRSND_BIT_NUMBER 2\r
# elif IRSND_OCx == IRSND_OC0B // OC0B\r
-# define IRSND_PORT PORTA // port A\r
-# define IRSND_DDR DDRA // ddr A\r
-# define IRSND_BIT 7 // OC0B\r
+# define IRSND_PORT_LETTER A\r
+# define IRSND_BIT_NUMBER 7\r
# else\r
# error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h\r
# endif // IRSND_OCx\r
#elif defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) // ATtiny45/85 uses OC0A = PB0 or OC0B = PB1\r
# if IRSND_OCx == IRSND_OC0A // OC0A\r
-# define IRSND_PORT PORTB // port B\r
-# define IRSND_DDR DDRB // ddr B\r
-# define IRSND_BIT 0 // OC0A\r
+# define IRSND_PORT_LETTER B\r
+# define IRSND_BIT_NUMBER 0\r
# elif IRSND_OCx == IRSND_OC0B // OC0B\r
-# define IRSND_PORT PORTB // port B\r
-# define IRSND_DDR DDRB // ddr B\r
-# define IRSND_BIT 1 // OC0B\r
+# define IRSND_PORT_LETTER B\r
+# define IRSND_BIT_NUMBER 1\r
# else\r
# error Wrong value for IRSND_OCx, choose IRSND_OC0A or IRSND_OC0B in irsndconfig.h\r
# endif // IRSND_OCx\r
+#elif defined (__AVR_ATtiny87__) || defined (__AVR_ATtiny167__) // ATtiny87/167 uses OC0A = PA2\r
+# if IRSND_OCx == IRSND_OC0A // OC0A\r
+# define IRSND_PORT_LETTER A\r
+# define IRSND_BIT_NUMBER 2\r
+# else\r
+# error Wrong value for IRSND_OCx, choose IRSND_OC0A in irsndconfig.h\r
+# endif // IRSND_OCx\r
#elif defined (__AVR_ATmega8__) // ATmega8 uses only OC2 = PB3\r
# if IRSND_OCx == IRSND_OC2 // OC0A\r
-# define IRSND_PORT PORTB // port B\r
-# define IRSND_DDR DDRB // ddr B\r
-# define IRSND_BIT 3 // OC0A\r
+# define IRSND_PORT_LETTER B\r
+# define IRSND_BIT_NUMBER 3\r
# else\r
# error Wrong value for IRSND_OCx, choose IRSND_OC2 in irsndconfig.h\r
# endif // IRSND_OCx\r
#elif defined (__AVR_ATmega16__) || defined (__AVR_ATmega32__) // ATmega16|32 uses OC2 = PD7\r
# if IRSND_OCx == IRSND_OC2 // OC2\r
-# define IRSND_PORT PORTD // port D\r
-# define IRSND_DDR DDRD // ddr D\r
-# define IRSND_BIT 7 // OC2\r
+# define IRSND_PORT_LETTER D\r
+# define IRSND_BIT_NUMBER 7\r
# else\r
# error Wrong value for IRSND_OCx, choose IRSND_OC2 in irsndconfig.h\r
# endif // IRSND_OCx\r
#elif defined (__AVR_ATmega162__) // ATmega162 uses OC2 = PB1 or OC0 = PB0\r
# if IRSND_OCx == IRSND_OC2 // OC2\r
-# define IRSND_PORT PORTB // port B\r
-# define IRSND_DDR DDRB // ddr B\r
-# define IRSND_BIT 1 // OC2\r
+# define IRSND_PORT_LETTER B\r
+# define IRSND_BIT_NUMBER 1\r
# elif IRSND_OCx == IRSND_OC0 // OC0\r
-# define IRSND_PORT PORTB // port B\r
-# define IRSND_DDR DDRB // ddr B\r
-# define IRSND_BIT 0 // OC0\r
+# define IRSND_PORT_LETTER B\r
+# define IRSND_BIT_NUMBER 0\r
# else\r
# error Wrong value for IRSND_OCx, choose IRSND_OC2 or IRSND_OC0 in irsndconfig.h\r
# endif // IRSND_OCx\r
|| defined (__AVR_ATmega1284__) \\r
|| defined (__AVR_ATmega1284P__) // ATmega164|324|644|644P|1284 uses OC2A = PD7 or OC2B = PD6 or OC0A = PB3 or OC0B = PB4\r
# if IRSND_OCx == IRSND_OC2A // OC2A\r
-# define IRSND_PORT PORTD // port D\r
-# define IRSND_DDR DDRD // ddr D\r
-# define IRSND_BIT 7 // OC2A\r
+# define IRSND_PORT_LETTER D\r
+# define IRSND_BIT_NUMBER 7\r
# elif IRSND_OCx == IRSND_OC2B // OC2B\r
-# define IRSND_PORT PORTD // port D\r
-# define IRSND_DDR DDRD // ddr D\r
-# define IRSND_BIT 6 // OC2B\r
+# define IRSND_PORT_LETTER D\r
+# define IRSND_BIT_NUMBER 6\r
# elif IRSND_OCx == IRSND_OC0A // OC0A\r
-# define IRSND_PORT PORTB // port B\r
-# define IRSND_DDR DDRB // ddr B\r
-# define IRSND_BIT 3 // OC0A\r
+# define IRSND_PORT_LETTER B\r
+# define IRSND_BIT_NUMBER 3\r
# elif IRSND_OCx == IRSND_OC0B // OC0B\r
-# define IRSND_PORT PORTB // port B\r
-# define IRSND_DDR DDRB // ddr B\r
-# define IRSND_BIT 4 // OC0B\r
+# define IRSND_PORT_LETTER B\r
+# define IRSND_BIT_NUMBER 4\r
# else\r
# error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h\r
# endif // IRSND_OCx\r
|| defined (__AVR_ATmega168P__) \\r
|| defined (__AVR_ATmega328P__) // ATmega48|88|168|168|328 uses OC2A = PB3 or OC2B = PD3 or OC0A = PD6 or OC0B = PD5\r
# if IRSND_OCx == IRSND_OC2A // OC2A\r
-# define IRSND_PORT PORTB // port B\r
-# define IRSND_DDR DDRB // ddr B\r
-# define IRSND_BIT 3 // OC2A\r
+# define IRSND_PORT_LETTER B\r
+# define IRSND_BIT_NUMBER 3\r
# elif IRSND_OCx == IRSND_OC2B // OC2B\r
-# define IRSND_PORT PORTD // port D\r
-# define IRSND_DDR DDRD // ddr D\r
-# define IRSND_BIT 3 // OC2B\r
+# define IRSND_PORT_LETTER D\r
+# define IRSND_BIT_NUMBER 3\r
# elif IRSND_OCx == IRSND_OC0A // OC0A\r
-# define IRSND_PORT PORTB // port B\r
-# define IRSND_DDR DDRB // ddr B\r
-# define IRSND_BIT 6 // OC0A\r
+# define IRSND_PORT_LETTER D\r
+# define IRSND_BIT_NUMBER 6\r
# elif IRSND_OCx == IRSND_OC0B // OC0B\r
-# define IRSND_PORT PORTD // port D\r
-# define IRSND_DDR DDRD // ddr D\r
-# define IRSND_BIT 5 // OC0B\r
+# define IRSND_PORT_LETTER D\r
+# define IRSND_BIT_NUMBER 5\r
# else\r
# error Wrong value for IRSND_OCx, choose IRSND_OC2A, IRSND_OC2B, IRSND_OC0A, or IRSND_OC0B in irsndconfig.h\r
# endif // IRSND_OCx\r
-#elif defined (__AVR_ATmega8515__) \r
+#elif defined (__AVR_ATmega8515__) // ATmega8515 uses OC0 = PB0 or OC1A = PD5 or OC1B = PE2\r
# if IRSND_OCx == IRSND_OC0 \r
-# define IRSND_PORT PORTB // port B\r
-# define IRSND_DDR DDRB // ddr B\r
-# define IRSND_BIT 0 // OC0\r
+# define IRSND_PORT_LETTER B\r
+# define IRSND_BIT_NUMBER 0\r
# elif IRSND_OCx == IRSND_OC1A \r
-# define IRSND_PORT PORTD // port D\r
-# define IRSND_DDR DDRD // ddr D\r
-# define IRSND_BIT 5 // OC1A\r
+# define IRSND_PORT_LETTER D\r
+# define IRSND_BIT_NUMBER 5\r
# elif IRSND_OCx == IRSND_OC1B \r
-# define IRSND_PORT PORTE // port E\r
-# define IRSND_DDR DDRE // ddr E\r
-# define IRSND_BIT 2 // OC1E\r
+# define IRSND_PORT_LETTER E\r
+# define IRSND_BIT_NUMBER 2\r
# else\r
# error Wrong value for IRSND_OCx, choose IRSND_OC0, IRSND_OC1A, or IRSND_OC1B in irsndconfig.h\r
# endif // IRSND_OCx\r
# endif // unix, WIN32\r
#endif // __AVR...\r
\r
+#if defined(ATMEL_AVR)\r
+# define _CONCAT(a,b) a##b\r
+# define CONCAT(a,b) _CONCAT(a,b)\r
+# define IRSND_PORT CONCAT(PORT, IRSND_PORT_LETTER)\r
+# define IRSND_DDR CONCAT(DDR, IRSND_PORT_LETTER)\r
+# define IRSND_BIT IRSND_BIT_NUMBER\r
+#endif\r
+\r
#if IRSND_SUPPORT_NIKON_PROTOCOL == 1\r
typedef uint16_t IRSND_PAUSE_LEN;\r
#else\r
#define SIEMENS_BIT_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)\r
#define SIEMENS_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
\r
+#define RUWIDO_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PULSE_TIME + 0.5)\r
+#define RUWIDO_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_START_BIT_PAUSE_TIME + 0.5)\r
+#define RUWIDO_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PULSE_TIME + 0.5)\r
+#define RUWIDO_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_BIT_PAUSE_TIME + 0.5)\r
+#define RUWIDO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * SIEMENS_OR_RUWIDO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
\r
#ifdef PIC_C18 // PIC C18\r
# define IRSND_FREQ_TYPE uint8_t\r
# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) (56000)\r
# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) (455000)\r
#else // AVR\r
+# if F_CPU >= 16000000L\r
+# define AVR_PRESCALER 8\r
+# else\r
+# define AVR_PRESCALER 1\r
+# endif\r
# define IRSND_FREQ_TYPE uint8_t\r
-# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / 2) - 1)\r
-# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / 2) - 1)\r
-# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / 2) - 1)\r
-# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / 2) - 1)\r
-# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / 2) - 1)\r
-# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / 2) - 1)\r
-# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / 2) - 1)\r
+# define IRSND_FREQ_30_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 30000 / AVR_PRESCALER / 2) - 1)\r
+# define IRSND_FREQ_32_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 32000 / AVR_PRESCALER / 2) - 1)\r
+# define IRSND_FREQ_36_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 36000 / AVR_PRESCALER / 2) - 1)\r
+# define IRSND_FREQ_38_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 38000 / AVR_PRESCALER / 2) - 1)\r
+# define IRSND_FREQ_40_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 40000 / AVR_PRESCALER / 2) - 1)\r
+# define IRSND_FREQ_56_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 56000 / AVR_PRESCALER / 2) - 1)\r
+# define IRSND_FREQ_455_KHZ (IRSND_FREQ_TYPE) ((F_CPU / 455000 / AVR_PRESCALER / 2) - 1)\r
#endif\r
\r
#define FDC_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * FDC_START_BIT_PULSE_TIME + 0.5)\r
#define LEGO_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * LEGO_0_PAUSE_TIME + 0.5)\r
#define LEGO_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * LEGO_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
\r
+#define A1TVBOX_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_START_BIT_PULSE_TIME + 0.5)\r
+#define A1TVBOX_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_START_BIT_PAUSE_TIME + 0.5)\r
+#define A1TVBOX_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_BIT_PULSE_TIME + 0.5)\r
+#define A1TVBOX_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * A1TVBOX_BIT_PAUSE_TIME + 0.5)\r
+#define A1TVBOX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * A1TVBOX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
+#define A1TVBOX_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * A1TVBOX_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
+\r
+#define ROOMBA_START_BIT_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_START_BIT_PULSE_TIME + 0.5)\r
+#define ROOMBA_START_BIT_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_START_BIT_PAUSE_TIME + 0.5)\r
+#define ROOMBA_1_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_1_PULSE_TIME + 0.5)\r
+#define ROOMBA_0_PULSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_0_PULSE_TIME + 0.5)\r
+#define ROOMBA_1_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_1_PAUSE_TIME + 0.5)\r
+#define ROOMBA_0_PAUSE_LEN (uint8_t)(F_INTERRUPTS * ROOMBA_0_PAUSE_TIME + 0.5)\r
+#define ROOMBA_FRAME_REPEAT_PAUSE_LEN (uint16_t)(F_INTERRUPTS * ROOMBA_FRAME_REPEAT_PAUSE_TIME + 0.5) // use uint16_t!\r
+\r
static volatile uint8_t irsnd_busy = 0;\r
static volatile uint8_t irsnd_protocol = 0;\r
static volatile uint8_t irsnd_buffer[6] = {0};\r
\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
* Switch PWM on\r
- * @details Switches PWM on with a narrow spike on all 3 channels -> leds glowing\r
*---------------------------------------------------------------------------------------------------------------------------------------------------\r
*/\r
static void\r
{\r
if (! irsnd_is_on)\r
{\r
-#ifndef DEBUG\r
+#ifndef ANALYZE\r
# if defined(PIC_C18) // PIC C18\r
- IRSND_PIN = 0; // output mode -> enable PWM outout pin (0=PWM on, 1=PWM off)\r
+ PWMon();\r
+ // IRSND_PIN = 0; // output mode -> enable PWM outout pin (0=PWM on, 1=PWM off)\r
# elif defined (ARM_STM32) // STM32\r
- TIM_Cmd(IRSND_TIMER, ENABLE); // TIMx enable counter\r
+ TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_OCMode_PWM1); // enable PWM as OC-mode\r
+ TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())\r
+ TIM_Cmd(IRSND_TIMER, ENABLE); // enable counter\r
# else // AVR\r
# if IRSND_OCx == IRSND_OC2 // use OC2\r
TCCR2 |= (1<<COM20)|(1<<WGM21); // toggle OC2 on compare match, clear Timer 2 at compare match OCR2\r
# error wrong value of IRSND_OCx\r
# endif // IRSND_OCx\r
# endif // C18\r
-#endif // DEBUG\r
+#endif // ANALYZE\r
\r
#if IRSND_USE_CALLBACK == 1\r
if (irsnd_callback_ptr)\r
{\r
if (irsnd_is_on)\r
{\r
-#ifndef DEBUG\r
+#ifndef ANALYZE\r
\r
# if defined(PIC_C18) // PIC C18\r
- IRSND_PIN = 1; //input mode -> disbale PWM output pin (0=PWM on, 1=PWM off)\r
+ PWMoff();\r
+ // IRSND_PIN = 1; //input mode -> disbale PWM output pin (0=PWM on, 1=PWM off)\r
# elif defined (ARM_STM32) // STM32\r
- TIM_Cmd(IRSND_TIMER, DISABLE); // TIMx enable counter\r
+ TIM_Cmd(IRSND_TIMER, DISABLE); // disable counter\r
+ TIM_SelectOCxM(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_ForcedAction_InActive); // force output inactive\r
+ TIM_CCxCmd(IRSND_TIMER, IRSND_TIMER_CHANNEL, TIM_CCx_Enable); // enable OC-output (is being disabled in TIM_SelectOCxM())\r
+ TIM_SetCounter(IRSND_TIMER, 0); // reset counter value\r
# else //AVR\r
\r
# if IRSND_OCx == IRSND_OC2 // use OC2\r
# endif // IRSND_OCx\r
IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low\r
# endif //C18\r
-#endif // DEBUG\r
+#endif // ANALYZE\r
\r
#if IRSND_USE_CALLBACK == 1\r
if (irsnd_callback_ptr)\r
static void\r
irsnd_set_freq (IRSND_FREQ_TYPE freq)\r
{\r
-#ifndef DEBUG\r
+#ifndef ANALYZE\r
# if defined(PIC_C18) // PIC C18\r
OpenPWM(freq); \r
- SetDCPWM( (uint16_t) freq * 2); // freq*2 = Duty cycles 50%\r
+ SetDCPWM( (uint16_t) (freq * 2) + 1); // freq*2 = Duty cycles 50%\r
+ PWMoff();\r
# elif defined (ARM_STM32) // STM32\r
- static uint32_t TimeBaseFreq = 0;\r
- TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;\r
- TIM_OCInitTypeDef TIM_OCInitStructure;\r
+ static uint32_t TimeBaseFreq = 0;\r
\r
if (TimeBaseFreq == 0)\r
{\r
/* Get system clocks and store timer clock in variable */\r
RCC_GetClocksFreq(&RCC_ClocksStructure);\r
# if ((IRSND_TIMER_NUMBER >= 2) && (IRSND_TIMER_NUMBER <= 5)) || ((IRSND_TIMER_NUMBER >= 12) && (IRSND_TIMER_NUMBER <= 14))\r
- TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency;\r
+ if (RCC_ClocksStructure.PCLK1_Frequency == RCC_ClocksStructure.HCLK_Frequency)\r
+ {\r
+ TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency;\r
+ }\r
+ else\r
+ {\r
+ TimeBaseFreq = RCC_ClocksStructure.PCLK1_Frequency * 2;\r
+ }\r
# else\r
- TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency;\r
+ if (RCC_ClocksStructure.PCLK2_Frequency == RCC_ClocksStructure.HCLK_Frequency)\r
+ {\r
+ TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency;\r
+ }\r
+ else\r
+ {\r
+ TimeBaseFreq = RCC_ClocksStructure.PCLK2_Frequency * 2;\r
+ }\r
# endif\r
}\r
\r
freq = TimeBaseFreq/freq;\r
\r
- /* Time base configuration */\r
- TIM_TimeBaseStructure.TIM_Period = freq;\r
- TIM_TimeBaseStructure.TIM_Prescaler = 0;\r
- TIM_TimeBaseStructure.TIM_ClockDivision = 0;\r
- TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;\r
- TIM_TimeBaseInit(IRSND_TIMER, &TIM_TimeBaseStructure);\r
-\r
- /* PWM1 Mode configuration: Channel1 */\r
- TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;\r
- TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;\r
- TIM_OCInitStructure.TIM_Pulse = (freq + 1) / 2;\r
- TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;\r
- TIM_OC1Init(IRSND_TIMER, &TIM_OCInitStructure);\r
-\r
+ /* Set frequency */\r
+ TIM_SetAutoreload(IRSND_TIMER, freq - 1);\r
+ /* Set duty cycle */\r
+ TIM_SetCompare1(IRSND_TIMER, (freq + 1) / 2);\r
# else // AVR\r
\r
# if IRSND_OCx == IRSND_OC2\r
# error wrong value of IRSND_OCx\r
# endif\r
# endif //PIC_C18\r
-#endif // DEBUG\r
+#endif // ANALYZE\r
}\r
\r
/*---------------------------------------------------------------------------------------------------------------------------------------------------\r
void\r
irsnd_init (void)\r
{\r
-#ifndef DEBUG\r
+#ifndef ANALYZE\r
# if defined(PIC_C18) // PIC C18\r
OpenTimer;\r
- irsnd_set_freq (IRSND_FREQ_36_KHZ); //default frequency\r
- IRSND_PIN = 1; //default PWM output pin off (0=PWM on, 1=PWM off)\r
+ irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency\r
+ IRSND_PIN = 0; // set IO to outout\r
+ PWMoff();\r
# elif defined (ARM_STM32) // STM32\r
- GPIO_InitTypeDef GPIO_InitStructure;\r
+ GPIO_InitTypeDef GPIO_InitStructure;\r
+ TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;\r
+ TIM_OCInitTypeDef TIM_OCInitStructure;\r
\r
/* GPIOx clock enable */\r
# if defined (ARM_STM32L1XX)\r
# else\r
RCC_APB2PeriphClockCmd(IRSND_TIMER_RCC, ENABLE);\r
# endif\r
- irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency\r
\r
- /* TIMx Configuration */\r
- TIM_OC1PreloadConfig(IRSND_TIMER, TIM_OCPreload_Enable);\r
+ /* Time base configuration */\r
+ TIM_TimeBaseStructure.TIM_Period = -1; // set dummy value (don't set to 0), will be initialized later\r
+ TIM_TimeBaseStructure.TIM_Prescaler = 0;\r
+ TIM_TimeBaseStructure.TIM_ClockDivision = 0;\r
+ TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;\r
+ TIM_TimeBaseInit(IRSND_TIMER, &TIM_TimeBaseStructure);\r
+\r
+ /* PWM1 Mode configuration */\r
+ TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;\r
+ TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;\r
+ TIM_OCInitStructure.TIM_Pulse = 0; // will be initialized later\r
+ TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;\r
+ TIM_OC1Init(IRSND_TIMER, &TIM_OCInitStructure);\r
+\r
+ /* Preload configuration */\r
TIM_ARRPreloadConfig(IRSND_TIMER, ENABLE);\r
- TIM_Cmd(IRSND_TIMER, ENABLE);\r
+ TIM_OC1PreloadConfig(IRSND_TIMER, TIM_OCPreload_Enable);\r
+\r
+ irsnd_set_freq (IRSND_FREQ_36_KHZ); // set default frequency\r
# else // AVR\r
IRSND_PORT &= ~(1<<IRSND_BIT); // set IRSND_BIT to low\r
IRSND_DDR |= (1<<IRSND_BIT); // set IRSND_BIT to output\r
\r
# if IRSND_OCx == IRSND_OC2 // use OC2\r
TCCR2 = (1<<WGM21); // CTC mode\r
- TCCR2 |= (1<<CS20); // 0x01, start Timer 2, no prescaling\r
+# if AVR_PRESCALER == 8\r
+ TCCR2 |= (1<<CS21); // start Timer 2, prescaler = 8\r
+# else\r
+ TCCR2 |= (1<<CS20); // start Timer 2, prescaler = 1\r
+# endif\r
# elif IRSND_OCx == IRSND_OC2A || IRSND_OCx == IRSND_OC2B // use OC2A or OC2B\r
TCCR2A = (1<<WGM21); // CTC mode\r
- TCCR2B |= (1<<CS20); // 0x01, start Timer 2, no prescaling\r
+# if AVR_PRESCALER == 8\r
+ TCCR2B = (1<<CS21); // start Timer 2, prescaler = 8\r
+# else\r
+ TCCR2B = (1<<CS20); // start Timer 2, prescaler = 1\r
+# endif\r
# elif IRSND_OCx == IRSND_OC0 // use OC0\r
TCCR0 = (1<<WGM01); // CTC mode\r
- TCCR0 |= (1<<CS00); // 0x01, start Timer 0, no prescaling\r
+# if AVR_PRESCALER == 8\r
+ TCCR0 |= (1<<CS01); // start Timer 0, prescaler = 8\r
+# else\r
+ TCCR0 |= (1<<CS00); // start Timer 0, prescaler = 1\r
+# endif\r
# elif IRSND_OCx == IRSND_OC0A || IRSND_OCx == IRSND_OC0B // use OC0A or OC0B\r
TCCR0A = (1<<WGM01); // CTC mode\r
- TCCR0B |= (1<<CS00); // 0x01, start Timer 0, no prescaling\r
+# if AVR_PRESCALER == 8\r
+ TCCR0B = (1<<CS01); // start Timer 0, prescaler = 8\r
+# else\r
+ TCCR0B = (1<<CS00); // start Timer 0, prescaler = 1\r
+# endif\r
# else\r
# error wrong value of IRSND_OCx\r
# endif\r
irsnd_set_freq (IRSND_FREQ_36_KHZ); // default frequency\r
# endif //PIC_C18\r
-#endif // DEBUG\r
+#endif // ANALYZE\r
}\r
\r
#if IRSND_USE_CALLBACK == 1\r
#if IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1\r
case IRMP_KASEIKYO_PROTOCOL:\r
{\r
- uint8_t xor;\r
+ uint8_t xor_value;\r
uint16_t genre2;\r
\r
address = bitsrevervse (irmp_data_p->address, KASEIKYO_ADDRESS_LEN);\r
command = bitsrevervse (irmp_data_p->command, KASEIKYO_COMMAND_LEN + 4);\r
genre2 = bitsrevervse ((irmp_data_p->flags & ~IRSND_REPETITION_MASK) >> 4, 4);\r
\r
- xor = ((address & 0x000F) ^ ((address & 0x00F0) >> 4) ^ ((address & 0x0F00) >> 8) ^ ((address & 0xF000) >> 12)) & 0x0F;\r
+ xor_value = ((address & 0x000F) ^ ((address & 0x00F0) >> 4) ^ ((address & 0x0F00) >> 8) ^ ((address & 0xF000) >> 12)) & 0x0F;\r
\r
irsnd_buffer[0] = (address & 0xFF00) >> 8; // AAAAAAAA\r
irsnd_buffer[1] = (address & 0x00FF); // AAAAAAAA\r
- irsnd_buffer[2] = xor << 4 | (command & 0x000F); // XXXXCCCC\r
+ irsnd_buffer[2] = xor_value << 4 | (command & 0x000F); // XXXXCCCC\r
irsnd_buffer[3] = (genre2 << 4) | (command & 0xF000) >> 12; // ggggCCCC\r
irsnd_buffer[4] = (command & 0x0FF0) >> 4; // CCCCCCCC\r
\r
- xor = irsnd_buffer[2] ^ irsnd_buffer[3] ^ irsnd_buffer[4];\r
+ xor_value = irsnd_buffer[2] ^ irsnd_buffer[3] ^ irsnd_buffer[4];\r
\r
- irsnd_buffer[5] = xor;\r
+ irsnd_buffer[5] = xor_value;\r
irsnd_busy = TRUE;\r
break;\r
}\r
#if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1\r
case IRMP_SIEMENS_PROTOCOL:\r
{\r
- irsnd_buffer[0] = ((irmp_data_p->address & 0x0FFF) >> 5); // SAAAAAAA\r
- irsnd_buffer[1] = ((irmp_data_p->address & 0x1F) << 3) | ((irmp_data_p->command & 0x7F) >> 5); // AAAAA0CC\r
- irsnd_buffer[2] = (irmp_data_p->command << 3) | ((~irmp_data_p->command & 0x01) << 2); // CCCCCc\r
+ irsnd_buffer[0] = ((irmp_data_p->address & 0x07FF) >> 3); // AAAAAAAA\r
+ irsnd_buffer[1] = ((irmp_data_p->address & 0x0007) << 5) | ((irmp_data_p->command >> 5) & 0x1F); // AAACCCCC\r
+ irsnd_buffer[2] = ((irmp_data_p->command & 0x001F) << 3) | ((~irmp_data_p->command & 0x01) << 2); // CCCCCc\r
\r
irsnd_busy = TRUE;\r
break;\r
}\r
#endif\r
+#if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1\r
+ case IRMP_RUWIDO_PROTOCOL:\r
+ {\r
+ irsnd_buffer[0] = ((irmp_data_p->address & 0x01FF) >> 1); // AAAAAAAA\r
+ irsnd_buffer[1] = ((irmp_data_p->address & 0x0001) << 7) | ((irmp_data_p->command & 0x7F)); // ACCCCCCC\r
+ irsnd_buffer[2] = ((~irmp_data_p->command & 0x01) << 7); // c\r
+ irsnd_busy = TRUE;\r
+ break;\r
+ }\r
+#endif\r
#if IRSND_SUPPORT_FDC_PROTOCOL == 1\r
case IRMP_FDC_PROTOCOL:\r
{\r
\r
irsnd_buffer[0] = (irmp_data_p->command & 0x0FF0) >> 4; // CCCCCCCC\r
irsnd_buffer[1] = ((irmp_data_p->command & 0x000F) << 4) | crc; // CCCCcccc\r
+ irsnd_busy = TRUE;\r
+ break;\r
+ }\r
+#endif\r
+#if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1\r
+ case IRMP_A1TVBOX_PROTOCOL:\r
+ {\r
+ irsnd_buffer[0] = 0x80 | (irmp_data_p->address >> 2); // 10AAAAAA\r
+ irsnd_buffer[1] = (irmp_data_p->address << 6) | (irmp_data_p->command >> 2); // AACCCCCC\r
+ irsnd_buffer[2] = (irmp_data_p->command << 6); // CC\r
\r
- irsnd_protocol = IRMP_LEGO_PROTOCOL;\r
+ irsnd_busy = TRUE;\r
+ break;\r
+ }\r
+#endif\r
+#if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1\r
+ case IRMP_ROOMBA_PROTOCOL:\r
+ {\r
+\r
+ irsnd_buffer[0] = (irmp_data_p->command & 0x7F) << 1; // CCCCCCC.\r
irsnd_busy = TRUE;\r
break;\r
}\r
}\r
else\r
{\r
-#ifdef DEBUG\r
+#ifdef ANALYZE\r
if (irsnd_is_on)\r
{\r
putchar ('0');\r
return irsnd_busy;\r
}\r
}\r
-#if 0\r
- else if (repeat_counter > 0 && packet_repeat_pause_counter < repeat_frame_pause_len)\r
-#else\r
else if (packet_repeat_pause_counter < repeat_frame_pause_len)\r
-#endif\r
{\r
packet_repeat_pause_counter++;\r
-\r
-#ifdef DEBUG\r
+#ifdef ANALYZE\r
if (irsnd_is_on)\r
{\r
putchar ('0');\r
pulse_len = SIEMENS_BIT_LEN;\r
pause_len = SIEMENS_BIT_LEN;\r
has_stop_bit = SIEMENS_OR_RUWIDO_STOP_BIT;\r
- complete_data_len = SIEMENS_COMPLETE_DATA_LEN - 1;\r
+ complete_data_len = SIEMENS_COMPLETE_DATA_LEN;\r
n_auto_repetitions = 1; // 1 frame\r
auto_repetition_pause_len = 0;\r
repeat_frame_pause_len = SIEMENS_FRAME_REPEAT_PAUSE_LEN;\r
break;\r
}\r
#endif\r
+#if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1\r
+ case IRMP_RUWIDO_PROTOCOL:\r
+ {\r
+ startbit_pulse_len = RUWIDO_START_BIT_PULSE_LEN;\r
+ startbit_pause_len = RUWIDO_START_BIT_PAUSE_LEN;\r
+ pulse_len = RUWIDO_BIT_PULSE_LEN;\r
+ pause_len = RUWIDO_BIT_PAUSE_LEN;\r
+ has_stop_bit = SIEMENS_OR_RUWIDO_STOP_BIT;\r
+ complete_data_len = RUWIDO_COMPLETE_DATA_LEN;\r
+ n_auto_repetitions = 1; // 1 frame\r
+ auto_repetition_pause_len = 0;\r
+ repeat_frame_pause_len = RUWIDO_FRAME_REPEAT_PAUSE_LEN;\r
+ irsnd_set_freq (IRSND_FREQ_36_KHZ);\r
+ break;\r
+ }\r
+#endif\r
#if IRSND_SUPPORT_FDC_PROTOCOL == 1\r
case IRMP_FDC_PROTOCOL:\r
{\r
case IRMP_NIKON_PROTOCOL:\r
{\r
startbit_pulse_len = NIKON_START_BIT_PULSE_LEN;\r
- startbit_pause_len = 271 - 1; // NIKON_START_BIT_PAUSE_LEN;\r
+ startbit_pause_len = NIKON_START_BIT_PAUSE_LEN;\r
complete_data_len = NIKON_COMPLETE_DATA_LEN;\r
pulse_1_len = NIKON_PULSE_LEN;\r
pause_1_len = NIKON_1_PAUSE_LEN - 1;\r
irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
break;\r
}\r
+#endif\r
+#if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1\r
+ case IRMP_A1TVBOX_PROTOCOL:\r
+ {\r
+ startbit_pulse_len = A1TVBOX_BIT_PULSE_LEN; // don't use A1TVBOX_START_BIT_PULSE_LEN\r
+ startbit_pause_len = A1TVBOX_BIT_PAUSE_LEN; // don't use A1TVBOX_START_BIT_PAUSE_LEN\r
+ pulse_len = A1TVBOX_BIT_PULSE_LEN;\r
+ pause_len = A1TVBOX_BIT_PAUSE_LEN;\r
+ has_stop_bit = A1TVBOX_STOP_BIT;\r
+ complete_data_len = A1TVBOX_COMPLETE_DATA_LEN + 1; // we send stop bit as data\r
+ n_auto_repetitions = 1; // 1 frame\r
+ auto_repetition_pause_len = 0;\r
+ repeat_frame_pause_len = A1TVBOX_FRAME_REPEAT_PAUSE_LEN;\r
+ irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
+ break;\r
+ }\r
+#endif\r
+#if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1\r
+ case IRMP_ROOMBA_PROTOCOL:\r
+ {\r
+ startbit_pulse_len = ROOMBA_START_BIT_PULSE_LEN;\r
+ startbit_pause_len = ROOMBA_START_BIT_PAUSE_LEN;\r
+ pulse_1_len = ROOMBA_1_PULSE_LEN;\r
+ pause_1_len = ROOMBA_1_PAUSE_LEN - 1;\r
+ pulse_0_len = ROOMBA_0_PULSE_LEN;\r
+ pause_0_len = ROOMBA_0_PAUSE_LEN - 1;\r
+ has_stop_bit = ROOMBA_STOP_BIT;\r
+ complete_data_len = ROOMBA_COMPLETE_DATA_LEN;\r
+ n_auto_repetitions = ROOMBA_FRAMES; // 8 frames\r
+ auto_repetition_pause_len = ROOMBA_FRAME_REPEAT_PAUSE_LEN;\r
+ repeat_frame_pause_len = ROOMBA_FRAME_REPEAT_PAUSE_LEN;\r
+ irsnd_set_freq (IRSND_FREQ_38_KHZ);\r
+ break;\r
+ }\r
#endif\r
default:\r
{\r
#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
case IRMP_DENON_PROTOCOL:\r
#endif\r
-#if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r
- case IRMP_THOMSON_PROTOCOL:\r
-#endif\r
#if IRSND_SUPPORT_NUBERT_PROTOCOL == 1\r
case IRMP_NUBERT_PROTOCOL:\r
#endif\r
#if IRSND_SUPPORT_LEGO_PROTOCOL == 1\r
case IRMP_LEGO_PROTOCOL:\r
#endif\r
-\r
+#if IRSND_SUPPORT_THOMSON_PROTOCOL == 1\r
+ case IRMP_THOMSON_PROTOCOL:\r
+#endif\r
+#if IRSND_SUPPORT_ROOMBA_PROTOCOL == 1\r
+ case IRMP_ROOMBA_PROTOCOL:\r
+#endif\r
\r
#if IRSND_SUPPORT_SIRCS_PROTOCOL == 1 || IRSND_SUPPORT_NEC_PROTOCOL == 1 || IRSND_SUPPORT_NEC16_PROTOCOL == 1 || IRSND_SUPPORT_NEC42_PROTOCOL == 1 || \\r
IRSND_SUPPORT_SAMSUNG_PROTOCOL == 1 || IRSND_SUPPORT_MATSUSHITA_PROTOCOL == 1 || \\r
IRSND_SUPPORT_KASEIKYO_PROTOCOL == 1 || IRSND_SUPPORT_RECS80_PROTOCOL == 1 || IRSND_SUPPORT_RECS80EXT_PROTOCOL == 1 || IRSND_SUPPORT_DENON_PROTOCOL == 1 || \\r
IRSND_SUPPORT_NUBERT_PROTOCOL == 1 || IRSND_SUPPORT_BANG_OLUFSEN_PROTOCOL == 1 || IRSND_SUPPORT_FDC_PROTOCOL == 1 || IRSND_SUPPORT_RCCAR_PROTOCOL == 1 || \\r
- IRSND_SUPPORT_JVC_PROTOCOL == 1 || IRSND_SUPPORT_NIKON_PROTOCOL == 1 || IRSND_SUPPORT_LEGO_PROTOCOL == 1 || IRSND_SUPPORT_THOMSON_PROTOCOL == 1 \r
+ IRSND_SUPPORT_JVC_PROTOCOL == 1 || IRSND_SUPPORT_NIKON_PROTOCOL == 1 || IRSND_SUPPORT_LEGO_PROTOCOL == 1 || IRSND_SUPPORT_THOMSON_PROTOCOL == 1 || \\r
+ IRSND_SUPPORT_ROOMBA_PROTOCOL == 1\r
{\r
#if IRSND_SUPPORT_DENON_PROTOCOL == 1\r
if (irsnd_protocol == IRMP_DENON_PROTOCOL)\r
#if IRSND_SUPPORT_SIEMENS_PROTOCOL == 1\r
case IRMP_SIEMENS_PROTOCOL:\r
#endif\r
+#if IRSND_SUPPORT_RUWIDO_PROTOCOL == 1\r
+ case IRMP_RUWIDO_PROTOCOL:\r
+#endif\r
#if IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1\r
case IRMP_GRUNDIG_PROTOCOL:\r
#endif\r
#if IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
case IRMP_NOKIA_PROTOCOL:\r
#endif\r
+#if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1\r
+ case IRMP_A1TVBOX_PROTOCOL:\r
+#endif\r
\r
-#if IRSND_SUPPORT_RC5_PROTOCOL == 1 || IRSND_SUPPORT_RC6_PROTOCOL == 1 || IRSND_SUPPORT_RC6A_PROTOCOL == 1 || IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 || \\r
- IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
+#if IRSND_SUPPORT_RC5_PROTOCOL == 1 || \\r
+ IRSND_SUPPORT_RC6_PROTOCOL == 1 || \\r
+ IRSND_SUPPORT_RC6A_PROTOCOL == 1 || \\r
+ IRSND_SUPPORT_RUWIDO_PROTOCOL == 1 || \\r
+ IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 || \\r
+ IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || \\r
+ IRSND_SUPPORT_IR60_PROTOCOL == 1 || \\r
+ IRSND_SUPPORT_NOKIA_PROTOCOL == 1 || \\r
+ IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1\r
{\r
if (pulse_counter == pulse_len && pause_counter == pause_len)\r
{\r
}\r
}\r
else // if (irsnd_protocol == IRMP_RC5_PROTOCOL || irsnd_protocol == IRMP_RC6_PROTOCOL || irsnd_protocol == IRMP_RC6A_PROTOCOL ||\r
- // irsnd_protocol == IRMP_SIEMENS_PROTOCOL)\r
+ // irsnd_protocol == IRMP_SIEMENS_PROTOCOL || irsnd_protocol == IRMP_RUWIDO_PROTOCOL)\r
#endif\r
{\r
if (current_bit == 0xFF) // 1 start bit\r
pulse_len = startbit_pulse_len;\r
pause_len = startbit_pause_len;\r
}\r
+ else\r
+#endif\r
+#if IRSND_SUPPORT_A1TVBOX_PROTOCOL == 1\r
+ if (irsnd_protocol == IRMP_A1TVBOX_PROTOCOL)\r
+ {\r
+ current_bit = 0;\r
+ }\r
+ else\r
#endif\r
+ {\r
+ ;\r
+ }\r
+\r
first_pulse = TRUE;\r
}\r
else // send n'th bit\r
\r
if (first_pulse)\r
{\r
+ // printf ("first_pulse: current_bit: %d %d < %d %d < %d\n", current_bit, pause_counter, pause_len, pulse_counter, pulse_len);\r
+\r
if (pulse_counter < pulse_len)\r
{\r
if (pulse_counter == 0)\r
}\r
else\r
{\r
+ // printf ("first_pause: current_bit: %d %d < %d %d < %d\n", current_bit, pause_counter, pause_len, pulse_counter, pulse_len);\r
+\r
if (pause_counter < pause_len)\r
{\r
if (pause_counter == 0)\r
break;\r
}\r
#endif // IRSND_SUPPORT_RC5_PROTOCOL == 1 || IRSND_SUPPORT_RC6_PROTOCOL == 1 || || IRSND_SUPPORT_RC6A_PROTOCOL == 1 || IRSND_SUPPORT_SIEMENS_PROTOCOL == 1 ||\r
- // IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
+ // IRSND_SUPPORT_RUWIDO_PROTOCOL == 1 || IRSND_SUPPORT_GRUNDIG_PROTOCOL == 1 || IRSND_SUPPORT_IR60_PROTOCOL == 1 || IRSND_SUPPORT_NOKIA_PROTOCOL == 1\r
\r
default:\r
{\r
}\r
}\r
\r
-#ifdef DEBUG\r
+#ifdef ANALYZE\r
if (irsnd_is_on)\r
{\r
putchar ('0');\r
return irsnd_busy;\r
}\r
\r
-#ifdef DEBUG\r
+#ifdef ANALYZE\r
\r
// main function - for unix/linux + windows only!\r
// AVR: see main.c!\r
}\r
\r
putchar ('\n');\r
+\r
+#if 1 // enable here to send twice\r
+ (void) irsnd_send_data (&irmp_data, TRUE);\r
+\r
+ while (irsnd_busy)\r
+ {\r
+ irsnd_ISR ();\r
+ }\r
+\r
+ putchar ('\n');\r
+#endif\r
}\r
else\r
{\r
return 0;\r
}\r
\r
-#endif // DEBUG\r
+#endif // ANALYZE\r
projects / irmp.git / blobdiff