*\r
* Copyright (c) 2009-2012 Frank Meyer - frank(at)fli4l.de\r
*\r
- * $Id: main.c,v 1.14 2012/05/15 10:25:21 fm Exp $\r
+ * $Id: main.c,v 1.15 2012/11/18 17:51:26 fm Exp $\r
*\r
* ATMEGA88 @ 8 MHz\r
*\r
TCCR1 = (1 << CTC1) | (1 << CS11) | (1 << CS10); // switch CTC Mode on, set prescaler to 4\r
#endif\r
\r
+#elif defined(STELLARIS_ARM_CORTEX_M4)\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);\r
+ TimerConfigure(TIMER1_BASE, TIMER_CFG_32_BIT_PER);\r
+\r
+ TimerLoadSet(TIMER1_BASE, TIMER_A, (F_CPU / F_INTERRUPTS) -1);\r
+ IntEnable(INT_TIMER1A);\r
+ TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);\r
+ TimerEnable(TIMER1_BASE, TIMER_A);\r
+ // Important: Timer1IntHandler has to be configured in startup_ccs.c !\r
#else // ATmegaXX:\r
OCR1A = (F_CPU / F_INTERRUPTS) - 1; // compare value: 1/15000 of CPU frequency\r
TCCR1B = (1 << WGM12) | (1 << CS10); // switch CTC Mode on, set prescaler to 1\r
#endif\r
\r
-#ifdef TIMSK1\r
+#if (!defined(STELLARIS_ARM_CORTEX_M4))\r
+# ifdef TIMSK1\r
TIMSK1 = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
-#else\r
+# else\r
TIMSK = 1 << OCIE1A; // OCIE1A: Interrupt by timer compare\r
+# endif\r
#endif\r
}\r
\r
*/\r
#ifdef TIM1_COMPA_vect // ATtiny84\r
ISR(TIM1_COMPA_vect)\r
+#elif defined(STELLARIS_ARM_CORTEX_M4)\r
+void Timer1IntHandler(void)\r
#else\r
ISR(TIMER1_COMPA_vect)\r
#endif\r
{\r
IRMP_DATA irmp_data;\r
\r
+#if defined(STELLARIS_ARM_CORTEX_M4)\r
+ ROM_FPUEnable();\r
+ ROM_FPUStackingEnable();\r
+ ROM_SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN);\r
+#endif\r
+\r
irmp_init(); // initialize irmp\r
timer1_init(); // initialize timer 1\r
sei (); // enable interrupts\r