Version 1.6.0: added FDC protocol, corrected DENON timing

[irmp.git] / irmp.h

diff --git a/irmp.h b/irmp.h
index 91283aa2635c9ac5a9e99939d04dd32bee0f1aa7..ba3beb7b16f98a9265f29c9277dd80cc90540b2d 100644 (file)
--- a/irmp.h
+++ b/irmp.h
@@ -3,7 +3,7 @@
  *\r
  * Copyright (c) 2009-2010 Frank Meyer - frank(at)fli4l.de\r
  *\r
- * $Id: irmp.h,v 1.23 2010/06/02 13:18:03 fm Exp $\r
+ * $Id: irmp.h,v 1.26 2010/06/08 23:34:14 fm Exp $\r
  *\r
  * ATMEGA88 @ 8 MHz\r
  *\r
@@ -43,6 +43,7 @@ extern "C"
 #define IRMP_GRUNDIG_PROTOCOL                   15                              // Grundig\r
 #define IRMP_NOKIA_PROTOCOL                     16                              // Nokia\r
 #define IRMP_SIEMENS_PROTOCOL                   17                              // Siemens, e.g. Gigaset\r
+#define IRMP_FDC_PROTOCOL                       18                              // FDC keyboard\r
 \r
 #define SIRCS_START_BIT_PULSE_TIME              2400.0e-6                       // 2400 usec pulse\r
 #define SIRCS_START_BIT_PAUSE_TIME               600.0e-6                       //  600 usec pause\r
@@ -153,7 +154,7 @@ extern "C"
 \r
 #define DENON_PULSE_TIME                        275.0e-6                        //  275 usec pulse\r
 #define DENON_1_PAUSE_TIME                      1900.0e-6                       // 1900 usec pause\r
-#define DENON_0_PAUSE_TIME                      1050.0e-6                       // 1050 usec pause\r
+#define DENON_0_PAUSE_TIME                       775.0e-6                       //  775 usec pause\r
 #define DENON_FRAMES                            2                               // DENON sends each frame 2 times\r
 #define DENON_AUTO_REPETITION_PAUSE_TIME          65.0e-3                       // inverted repetition after 65ms\r
 #define DENON_FRAME_REPEAT_PAUSE_TIME             65.0e-3                       // frame repeat after 65ms\r
@@ -264,6 +265,20 @@ extern "C"
 #define SIEMENS_STOP_BIT                        0                               // has no stop bit\r
 #define SIEMENS_LSB                             0                               // MSB...LSB\r
 \r
+#define FDC_START_BIT_PULSE_TIME                1390.0e-6                       // 1390 usec pulse\r
+#define FDC_START_BIT_PAUSE_TIME                 640.0e-6                       //  640 usec pause\r
+#define FDC_PULSE_TIME                           200.0e-6                       //  200 usec pulse\r
+#define FDC_1_PAUSE_TIME                         475.0e-6                       //  475 usec pause\r
+#define FDC_0_PAUSE_TIME                         145.0e-6                       //  145 usec pause\r
+#define FDC_FRAME_REPEAT_PAUSE_TIME               40.0e-3                       // frame repeat after 40ms\r
+#define FDC_ADDRESS_OFFSET                       0                              // skip 0 bits\r
+#define FDC_ADDRESS_LEN                         16                              // read 16 address bits\r
+#define FDC_COMMAND_OFFSET                      25                              // skip 25 bits (16 address + 9 0-bits)\r
+#define FDC_COMMAND_LEN                         12                              // read 12 bits\r
+#define FDC_COMPLETE_DATA_LEN                   40                              // complete length\r
+#define FDC_STOP_BIT                            1                               // has stop bit\r
+#define FDC_LSB                                 1                               // LSB...MSB\r
+\r
 #define AUTO_FRAME_REPETITION_TIME              50.0e-3                         // SIRCS/SAMSUNG32/NUBERT: automatic repetition after 25-50ms\r
 \r
 #define TRUE                                    1\r