1 title 'Boot loader module for CP/M 3.0'
5 public hwinit,?init,?ldccp,?rlccp
10 extrn pr.inln,pr.crlf,pr.dec,pr.decl
11 extrn ioini1l,msginit,mmuinit,intinit,cpu_frq
13 extrn @civec,@covec,@aivec,@aovec,@lovec
22 ; CP/M BDOS Function Interfaces
39 dseg ; init done from banked memory
59 ; ld hl,1000000000000000b ; assign console to AVRCON:
60 ld hl,0100000000000000b ; assign console to ASCI0:
63 ld hl,0000000000000000b ; assign printer to nothing:
65 ld hl,0100000000000000b ; assign AUX to ASCI0:
70 call intinit ; setup interrupts and vectors
71 call prt0ini ; init timer
74 call gs_rtc ; get time and date
77 ld (@cbnk),a ; right now in bank 0
79 call pr.inln ; print signon message
80 db 13,10,13,10,'CP/M Version 3.0, Z180-Stamp BIOS',13,10,0
83 db 'Estimated CPU clock [Hz]: ',0
92 cseg ; boot loading must be done from resident memory
94 ; This version of the boot loader loads the CCP from a file
95 ; called CCP.COM on the system drive (A:).
99 ; First time, load the A:CCP.COM file into TPA
103 ld (ccp$fcb+15),a ; zero extent
105 ld (fcb$nr),hl ; start at beginning of file
107 ld c,open ; open file containing CCP
110 jp z,no$ccp ; error if no file...
112 ld c,setdma ; start of TPA
115 ld c,setmulti ; allow up to 16k bytes
118 ld c,read ; load the thing
119 call bdos ; read records
121 ; copy CCP to bank 0 for reloading
123 ld bc,ccpsize ; clone 3K, just in case
125 push af ; save current bank
128 call ?bnksl ; select TPA
132 call ?bnksl ; select extra bank
134 ld (hl),a ; save the byte
135 cpi ; bump pointer, drop count
138 call ?bnksl ; restore original bank
141 no$ccp: ; here if we couldn't find the file
142 call pr.inln ; report this...
143 db 13,10,'BIOS Err on A: No CCP.COM file',0
145 call ?conin ; get a response
146 jp ?ldccp ; and try again
151 ld bc,ccpsize ; clone 3K
154 call ?bnksl ; select extra bank
155 ld a,(hl) ; get a byte
158 call ?bnksl ; select TPA
160 ld (hl),a ; save the byte
161 cpi ; bump pointer, drop count
166 ccp$fcb:db 1,'CCP ','COM',0,0,0,0
173 db (hwini0_e-$)/2 ;count
174 db rcr,CREFSH ;configure DRAM refresh
175 db dcntl,CWAITIO ;wait states
176 db ccr,M_NCD ;No Clock Divide
177 db cmr,PHI_X2 ;X2 Clock Multiplier
178 ;TODO: db omr, ;Operation Mode Control Register
183 f_cpu dw 0,0 ;detected CPU clock frequency [Hz]