cbios/config.inc

   1         .xlist
   2
   3 FALSE   equ     0
   4 TRUE    equ     NOT FALSE
   5
   6
   7 banked  equ     true
   8
   9 ;-----------------------------------------------------
  10 ; CPU and BANKING types
  11
  12
  13 CPU_Z180        equ     TRUE
  14 CPU_Z80         equ     FALSE
  15
  16 ROMSYS          equ     FALSE
  17
  18 AVRCLK          equ     18432           ;[KHz]
  19
  20     if CPU_Z180
  21
  22 ;-----------------------------------------------------
  23 ;FOSC           equ     AVRCLK/2        ;Oscillator frequency [KHz]
  24 ;PHI            equ     FOSC*2          ;CPU frequency (clock doubler enabled)
  25
  26 ;----------------------------------------------------------------------
  27 ; Baudrate Generator for x16 clock mode:
  28 ; TC = (f PHI / (32 * baudrate)) - 2
  29 ;
  30 ;     PHI [MHz]: 9.216 18.432
  31 ;     baudrate     TC     TC
  32 ;     ----------------------
  33 ;      115200       -      3
  34 ;       57600       3      8
  35 ;       38400       -     13
  36 ;       19200      13     28
  37 ;        9600      28     58
  38
  39
  40 ;-----------------------------------------------------
  41 ; Programmable Reload Timer (PRT)
  42
  43 PRT_PRE         equ     20              ;PRT prescaler
  44
  45 ;-----------------------------------------------------
  46 ; MMU
  47
  48 COMMON_SIZE     equ     4*1024          ;Common Area size in bytes
  49                                         ;must be multiple of 4K
  50 if (COMMON_SIZE mod 1000h)
  51         .printx COMMON_SIZE not multiple of 4K!
  52         end     ;stop assembly
  53 endif
  54 CMN_SIZE        equ     COMMON_SIZE/1000h               ;4K units
  55 BNK_SIZE        equ     64/4 - CMN_SIZE                 ;bank size (4K units)
  56 BANKS           equ     (512/4 - CMN_SIZE)/BNK_SIZE     ;max nr. of banks
  57
  58 ; Logical address space, CBAR values
  59
  60 CA              equ     10h - CMN_SIZE          ;common area start (64K - common size)
  61 BA              equ     0                       ;banked area start
  62
  63    if 0
  64
  65 SYS$CBR         equ     0
  66 SYS$CBAR        equ     CA*16 + CA      ;CBAR in system mode
  67 USR$CBAR        equ     CA*16 + BA      ;CBAR in user mode (CP/M)
  68
  69    endif
  70    if 1
  71
  72 SYS$CBR         equ     BNK_SIZE
  73 SYS$CBAR        equ     CA*16 + CA      ;CBAR in system mode
  74 USR$CBAR        equ     CA*16 + BA      ;CBAR in user mode (CP/M)
  75
  76    endif
  77
  78
  79 ;-----------------------------------------------------
  80
  81 CREFSH          equ     0               ;Refresh rate register (disable refresh)
  82 CWAITIO         equ     3 shl IWI0      ;Max I/O Wait States, 0 Memory Wait States
  83 PHI_X2          equ     0               ;set to M_X2CM to enable the clock doubler
  84
  85     endif               ;CPU_Z180
  86     if  CPU_Z80
  87
  88 PHI             equ     AVRCLK/5        ;CPU frequency [KHz]
  89 BAUDCLCK        equ     AVRCLK/10       ;Baudrate clock [KHz]
  90 ;BDCLK16                equ
  91
  92 SIOAD   EQU     0bch
  93 SIOAC   EQU     0bdh
  94 SIOBD   EQU     0beh
  95 SIOBC   EQU     0bfh
  96
  97 CTC0    EQU     0f4h
  98 CTC1    EQU     0f5h
  99 CTC2    EQU     0f6h
 100 CTC3    EQU     0f7h
 101
 102 ;
 103 ; Init Serial I/O for console input and output (SIO-A)
 104 ;
 105 ; Baudrate clock: 1843200 Hz (Bus connector pin A17)
 106 ;
 107 ; Baudrate   Divider    SIO     CTC
 108 ; ---------------------------------
 109 ; 115200          16     16       1
 110 ;  57600          32     16       2
 111 ;  38400          48     16       3
 112 ;  19200          96     16       6
 113 ;   9600         192     16      12
 114 ;   4800         384     16      24
 115 ;   2400         768     16      48
 116 ;   1200        1536     16      96
 117 ;    600        3072     16     192
 118 ;    300        6144     64      92
 119
 120     endif       ; CPU_Z80
 121
 122     if  ROMSYS
 123 c$rom           equ     0a5h
 124 ROM_EN          equ     0C0h
 125 ROM_DIS         equ     ROMEN+1
 126      if CPU_Z180
 127 CWAITROM        equ     2 shl MWI0
 128      endif
 129     endif
 130
 131
 132 DDTZRSTVEC      equ     030h            ;DDTZ Restart vector (breakpoints)
 133
 134 INIDONE         equ     03Fh            ;CP/M skip hw init, if this address
 135 INIDONEVAL      equ     080h            ;    is set to this value.
 136
 137 mtx.fifo_len    equ     64              ;Message transfer fifos
 138 mtx.fifo_id     equ     0               ;    This *must* have #0
 139 mrx.fifo_len    equ     64
 140 mrx.fifo_id     equ     1
 141
 142 ci.fifo_len     equ     32              ;AVRCON (USB0) Character I/O via AVR
 143 ci.fifo_id      equ     2
 144 co.fifo_len     equ     32
 145 co.fifo_id      equ     3
 146
 147 s0.rx_len       equ     128             ;Serial 0 (ASCI0) buffers
 148 s0.rx_id        equ     4               ;
 149 s0.tx_len       equ     128             ;
 150 s0.tx_id        equ     5               ;
 151
 152 s1.rx_len       equ     128             ;Serial 1 (ASCI1) buffers
 153 s1.rx_id        equ     6               ;
 154 s1.tx_len       equ     128             ;
 155 s1.tx_id        equ     7               ;
 156
 157 AVRINT5         equ     4Fh
 158 AVRINT6         equ     5Fh
 159 ;PMSG           equ     80h
 160
 161 IDEBASE         equ     60h
 162
 163 ;-----------------------------------------------------
 164 ; Definition of (logical) top 2 memory pages
 165
 166 sysram_start    equ     0FE00h
 167 bs$stack$size   equ     80
 168
 169 isvsw_loc       equ     0FEE0h
 170
 171 ivtab           equ     0ffc0h          ;int vector table
 172 iv2tab          equ     ivtab + 2*9
 173
 174
 175
 176 ;-----------------------------------------------------
 177
 178 o.id            equ     -4
 179 o.mask          equ     -3
 180 o.in_idx        equ     -2
 181 o.out_idx       equ     -1
 182
 183         ;.lall
 184
 185 mkbuf   macro   id,name,size
 186   if ((size AND (size-1)) NE 0) OR (size GT 256)
 187     .printx Error: buffer ^size must be power of 2 and in range 0..256!
 188     name&.mask equ ;wrong size error
 189   else
 190     db id
 191     db size-1
 192     ds 2
 193     name:: ds size
 194     name&.mask equ low (size-1)
 195     if size ne 0
 196       name&.end equ $-1
 197       name&.len equ size
 198       name&.id equ id
 199     endif
 200   endif
 201 endm
 202
 203 ;-----------------------------------------------------
 204
 205 inidat  macro
 206         cseg
 207 ??ps.a  defl    $
 208         endm
 209
 210 inidate macro
 211 ??ps.len defl   $ - ??ps.a
 212         dseg
 213         ds      ??ps.len
 214         endm
 215
 216 ;-----------------------------------------------------
 217
 218 b0call  macro   address
 219         call    _b0call
 220         dw      address
 221         endm
 222
 223 ;-----------------------------------------------------
 224 ; shift accu right logical n bits
 225
 226 srlan   macro   n
 227         if n > 7 or n < 0
 228          xor a
 229          exitm
 230         endif
 231
 232         if n > 4
 233          rept 8-n
 234           rlca
 235          endm
 236          and (1 << (8-n)) - 1
 237          exitm
 238         endif
 239
 240         if n > 2
 241          rept n
 242           rrca
 243          endm
 244          and (1 << (8-n)) - 1
 245          exitm
 246         endif
 247
 248         rept n
 249          srl a
 250         endm
 251         endm
 252
 253 ;-----------------------------------------------------
 254 ; convert bit mask to bit number
 255
 256 m2b     macro   name,mask
 257         local   n
 258         n defl  mask
 259         name defl 0
 260         rept 8
 261           n defl n/2
 262           if n = 0
 263             exitm
 264           endif
 265           name defl name+1
 266         endm
 267         endm
 268
 269         .list