cbios/misc.180

   1
   2         public intinit
   3         public cpu_frq
   4         public get_tmr
   5
   6         extrn div32_r,pr.inln
   7         extrn msg.sm,msg.recv,hwl2phy
   8
   9         maclib z180reg.inc
  10         maclib config.inc
  11
  12
  13 ;----------------------------------------------------------------------
  14
  15         dseg
  16
  17 intinit:
  18         ld      hl,ivtab        ;
  19         ld      a,h             ;
  20         ld      i,a             ;
  21         out0    (il),l          ;
  22         im      2
  23
  24 ; Let all vectors point to spurious int routines.
  25
  26         ld      de,sp.int0
  27         ld      bc,sp.int.len
  28         ld      a,9
  29 ivt_i1:
  30         ld      (hl),e
  31         inc     l
  32         ld      (hl),d
  33         inc     l
  34         ex      de,hl
  35         add     hl,bc
  36         ex      de,hl
  37         dec     a
  38         jr      nz,ivt_i1
  39         ret
  40
  41
  42 ;--------------------------------------------------------------------
  43 ; Spurious interrupt handler
  44
  45         cseg    ; common area
  46 sp.int0:
  47         ld      a,00h
  48         jr      sp.i.1
  49 sp.int.len equ  $-sp.int0
  50         ld      a,01h
  51         jr      sp.i.1
  52         ld      a,02h
  53         jr      sp.i.1
  54         ld      a,03h
  55         jr      sp.i.1
  56         ld      a,04h
  57         jr      sp.i.1
  58         ld      a,05h
  59         jr      sp.i.1
  60         ld      a,06h
  61         jr      sp.i.1
  62         ld      a,07h
  63         jr      sp.i.1
  64         ld      a,08h
  65 sp.i.1:
  66 ;       out     (80h),a
  67
  68         add     a,'0'
  69         ld      (spi$nr),a
  70         call    pr.inln
  71         db      13,10,'Spurious Int: '
  72 spi$nr: db      '0'
  73         db      0
  74 sp.i.2:
  75         halt
  76         jr      sp.i.2
  77
  78 ;--------------------------------------------------------------------
  79 ;
  80 ; Get/compute CPU clock
  81 ;
  82 ;    return:
  83 ;       hlde:   CPU frequency (Hz)
  84 ;
  85
  86         dseg
  87
  88 cpu_frq:
  89         ld      hl,0
  90         ld      d,h
  91         ld      e,l
  92         call    get_tmr
  93         push    de
  94         push    hl
  95
  96 ; delay  ~8ms @ 18.432MHz  --> 147456 clock cycles
  97 ; delay ~10ms @ 18.432MHz  --> 184320 clock cycles
  98 ;
  99
 100 ;       ld      hl,8192         ; 147456/18
 101         ld      hl,(10240-100)*5 ; 184320/18
 102         ld      de,1
 103         or      a
 104 dly_lp:
 105         sbc     hl,de           ; 10
 106         jr      nz,dly_lp       ; 6/8  -> 18 cycles
 107
 108         pop     hl
 109         pop     de
 110         call    get_tmr
 111
 112         ld      b,h
 113         ld      c,l
 114         ld      de,036EEh       ;18432000/(2**16) * 50
 115         ld      hl,08000h       ;18432000%(2**16) * 50
 116
 117         ld      a,b
 118         or      a
 119         jr      nz,cpuf_div
 120         ld      a,c
 121         cp      2
 122         jr      c,cpuf_done
 123 cpuf_div:
 124         call    div32_r
 125 cpuf_done:
 126         ret
 127
 128 ;--------------------------------------------------------------------
 129
 130         dseg
 131 get_tmr:
 132         push    de
 133         push    hl
 134         ld      hl,1*256 + 3            ; h = subcommand, l = command
 135         push    hl
 136         ld      hl,0
 137         add     hl,sp
 138         ld      b,6
 139         call    msg.sm
 140
 141         dec     sp
 142         ld      hl,0
 143         add     hl,sp
 144         ld      b,7                     ; max receive message len
 145         call    msg.recv
 146
 147         pop     bc
 148         inc     sp
 149         pop     hl
 150         pop     de
 151         ret
 152
 153 ;----------------------------------------------------------------------
 154
 155         end