cbios/ascip.180

   1         page    200
   2
   3 ; Simple polling drivers for ASCI0 and ASCI1
   4
   5         extrn   ioiniml
   6
   7         global  as0init
   8         global  as0ista,as0inp
   9         global  as0osta,as0out
  10         global  as1init
  11         global  as1ista,as1inp
  12         global  as1osta,as1out
  13
  14         include config.inc
  15         include z180reg.inc
  16
  17
  18 ;--------------------------------------------------------------
  19 ;
  20 ;
  21 ; TC = (f PHI /(2*baudrate*Clock_mode)) - 2
  22 ;
  23 ; TC = (f PHI / (32 * baudrate)) - 2
  24 ;
  25
  26         cseg
  27 ;
  28 ; Init Serial I/O for console input and output (ASCI1)
  29 ;
  30
  31 ; TODO: set baudrate
  32
  33 as0init:
  34         ld      hl,initab0
  35         jp      ioiniml
  36
  37 as1init:
  38         ld      hl,initab1
  39         jp      ioiniml
  40
  41
  42
  43
  44 initab0:
  45         db      1,stat0,0               ;Disable rx/tx interrupts
  46                                         ;Enable baud rate generator
  47         db      1,asext0,M_BRGMOD+M_DCD0DIS+M_CTS0DIS
  48         db      2,astc0l,low 28, high 28
  49         db      1,cntlb0,M_MPBT         ;No MP Mode, X16
  50         db      1,cntla0,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1
  51         db      0
  52
  53 initab1:
  54         db      1,stat1,0               ;Disable rx/tx ints, disable CTS1
  55         db      1,asext1,M_BRGMOD       ;Enable baud rate generator
  56         db      2,astc1l,low 3, high 3
  57         db      1,cntlb1,M_MPBT         ;No MP Mode, X16
  58         db      1,cntla1,M_RE+M_TE+M_MOD2 ;Rx/Tx enable, 8N1
  59         db      0
  60
  61
  62 ;--------------------------------------------------------------
  63
  64 as0ista:
  65         in0     a,(stat0)
  66         and     M_RDRF
  67         ret     z
  68         or      0ffh
  69         ret
  70
  71 as1ista:
  72         in0     a,(stat1)
  73         and     M_RDRF
  74         ret     z
  75         or      0ffh
  76         ret
  77
  78
  79 as0inp:
  80         in0     a,(stat0)
  81         rlca
  82         jr      nc,as0inp
  83         in0     a,rdr0
  84         ret
  85
  86 as1inp:
  87         in0     a,(stat1)
  88         rlca
  89         jr      nc,as1inp
  90         in0     a,rdr1
  91         ret
  92
  93
  94
  95 as0osta:
  96         in0     a,(stat0)
  97         and     M_TDRE
  98         ret     z
  99         or      0ffh
 100         ret
 101
 102 as1osta:
 103         in0     a,(stat1)
 104         and     M_TDRE
 105         ret     z
 106         or      0ffh
 107         ret
 108
 109
 110 as0out:
 111         in0     a,(stat0)
 112         and     M_TDRE
 113         jr      z,as0out
 114         out0    (tdr0),c
 115         ld      a,c
 116         ret
 117
 118 as1out:
 119         in0     a,(stat1)
 120         and     M_TDRE
 121         jr      z,as1out
 122         out0    (tdr1),c
 123         ld      a,c
 124         ret
 125
 126         end